Optical communication transmitting assembly and method of manufacturing the same

Abstract

The application provides an optical communication transmitting assembly and a preparation method thereof, and solves the problems of fragmentation and material residue caused by uneven support when a Micro-LED array is heterogeneously integrated with a driving wafer. Both paths are realized by alternately bonding and removing a double-sided temporary substrate, combined with the fabrication of a first TSV column and a second wiring layer on the back surface, to ensure that the first wafer is supported during thinning and back surface processing, and to avoid warping and fragmentation. Path one integrates the Micro-LED array and forms a light-transmitting protective layer first, and then performs back surface processing. The light-transmitting protective layer uniformly distributes the support pressure, permanently retains the light-emitting function, avoids pollution, and improves the light extraction efficiency. Path two completes the back surface processing first, and then integrates the Micro-LED array, so that the light-emitting material is not affected by high temperature. Finally, the same structure of the integrated Micro-LED array, the first TSV column and the second wiring layer is obtained, and the two are electrically connected through the TSV. The emitting element is bonded to the interlayer through the second wiring layer, and three-dimensional packaging is realized.

Description

Technical Field

[0001] This invention belongs to the field of optical interconnection and relates to an optical communication transmitting component and its preparation method. Background Technology

[0002] The performance of light-emitting components is crucial in the field of optical interconnects, especially in the area of ​​Micro-LED-based optical interconnects. Micro-LEDs are widely used in micro-displays and high-density displays due to their advantages such as high brightness, low power consumption, fast response speed, and long lifespan. In Micro-LED-based optical interconnect architectures, to achieve precise driving of the Micro-LED array, it is usually necessary to integrate the Micro-LED array with a wafer containing the driving circuitry, and to achieve electrical connection between the two through wiring layers.

[0003] As device integration and packaging density continue to increase, relying solely on the front side of the wafer for electrical connections and packaged leads is no longer sufficient to meet the demands of high-density interconnects. Therefore, it is typically necessary to form a TSV structure and a back-side wiring layer on the back side of the wafer to bring the front-side wiring structure to the back side and facilitate subsequent electrical connections with the interposer or packaging substrate. However, during these processes, the wafer is prone to warping, breakage, or deformation. The Micro-LED array, wiring layer, and driving circuitry may also be affected by mechanical and thermal stresses, leading to device damage, electrical connection failures, or reduced yield.

[0004] Therefore, how to improve the structural protection capability and packaging reliability during the process while realizing the integration of light-emitting element arrays and driving circuits and the back electrical lead-out has become a technical problem that urgently needs to be solved in this field.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an optical communication transmitting component and its fabrication method, so as to ensure that the wafer always receives effective mechanical support to avoid breakage during the fabrication of the back-side interconnect structure, thereby reliably obtaining a transmitting component structure with both double-sided interconnect functions.

[0007] As described above, the present invention provides an optical communication transmitting component and a method for manufacturing the same, the method comprising:

[0008] A first wafer is provided, the first wafer including driving circuitry near the front side of the first wafer;

[0009] A first wiring layer is formed on the front side of the first wafer, and the first wiring layer is electrically connected to the driving circuit.

[0010] A structure to be cut is formed based on a first temporary substrate, a second temporary substrate, and a light-transmitting protective layer; wherein:

[0011] The structure to be cut includes a first TSV pillar formed on the back side of the self-thinned first wafer and electrically connected to the first wiring layer; an array of light-emitting elements on the surface of the first wiring layer; and a second wiring layer on the back side of the first wafer electrically connected to the first wiring layer through the first TSV pillar.

[0012] The light-transmitting protective layer is formed on the surface of the light-emitting element array. The first temporary substrate is bonded to the side of the first wiring layer away from the second wiring layer. The second temporary substrate is bonded to the surface of the second wiring layer. The first temporary substrate is removed based on the second temporary substrate to form the structure to be cut, which includes the light-transmitting protective layer.

[0013] The structure to be cut is cut to form multiple emitting elements, each emitting element integrating the light-emitting element array and the driving circuit.

[0014] Optionally, the light-emitting element array is a Micro-LED array.

[0015] Optionally, the steps following providing the first wafer and forming the first wiring layer specifically include:

[0016] The light-emitting element array is formed on the surface of the first wiring layer, and the light-emitting element array is electrically connected to the first wiring layer;

[0017] A light-transmitting protective layer is formed on the surface of the light-emitting element array, the light-transmitting protective layer covers the light-emitting element array and fills its gaps, and the surface of the light-transmitting protective layer is higher than the surface of the light-emitting element array;

[0018] Provide the first temporary substrate and bond the first temporary substrate to the surface of the light-transmitting protective layer;

[0019] Thin the back side of the first wafer; form a first TSV via downward from the back side of the first wafer, and fill it to form the first TSV pillar, the first TSV pillar being electrically connected to the first wiring layer;

[0020] A second wiring layer is formed on the back side of the first wafer, and the second wiring layer is electrically connected to the first wiring layer through the first TSV pillar;

[0021] Provide the second temporary substrate and bond the second temporary substrate to the surface of the second wiring layer;

[0022] Remove the first temporary substrate to expose the light-transmitting protective layer;

[0023] Remove the second temporary substrate to expose the second wiring layer, thereby forming the structure to be cut;

[0024] The structure to be cut is cut to form multiple emitting elements, each emitting element integrating the Micro-LED array and the driving circuit.

[0025] Optionally, the steps following providing the first wafer and forming the first wiring layer specifically include:

[0026] Provide the first temporary substrate and bond the first temporary substrate to the first wiring layer;

[0027] Thin the back side of the first wafer; form a first TSV via downward from the back side of the first wafer, and fill it to form the first TSV pillar, the first TSV pillar being electrically connected to the first wiring layer;

[0028] A second wiring layer is formed on the back side of the first wafer, and the second wiring layer is electrically connected to the first wiring layer through the first TSV pillar;

[0029] Provide the second temporary substrate and bond the second temporary substrate to the surface of the second wiring layer;

[0030] Remove the first temporary substrate to expose the first wiring layer;

[0031] The Micro-LED array is formed above the first wiring layer, and the Micro-LED array is electrically connected to the first wiring layer;

[0032] A light-transmitting protective layer is formed on the surface of the Micro-LED array, the light-transmitting protective layer covers the Micro-LED array and fills its gaps, and the surface of the light-transmitting protective layer is higher than the surface of the Micro-LED array;

[0033] Remove the second temporary substrate to expose the second wiring layer, thereby forming the structure to be cut;

[0034] The structure to be cut is cut to form multiple emitting elements, each emitting element integrating the Micro-LED array and the driving circuit.

[0035] Optionally, a microstructure is formed based on the light-transmitting protective layer, and the microstructure acts as an optical coupler to couple the light emitted by the Micro-LED array to an optical communication receiver.

[0036] Optionally, the material of the light-transmitting protective layer includes at least one of silicon oxide, silicon nitride, spin-coated glass, or transparent organic resin.

[0037] Optionally, the Micro-LED array is electrically connected to the first wiring layer via flip-chip bonding, metal-to-metal bonding, or hybrid bonding.

[0038] Optionally, a receiving circuit is further formed in the first wafer, and the electrical signals of the driving circuit and the receiving circuit are independent of each other; the first wiring layer includes a driving wiring area and a receiving wiring area that are electrically isolated from each other;

[0039] A photodiode (PD) layer is formed above the first wiring layer, and the PD layer is patterned to form a photosensitive area and a non-photosensitive area; the photosensitive area is electrically connected to the receiving wiring area.

[0040] A conductive via is formed in the non-photosensitive area, penetrating the PD layer, and a conductive material is filled into the conductive via to form a fourth TSV pillar;

[0041] The Micro-LED array is fabricated above the patterned PD layer, and the Micro-LED array is electrically connected to the driving wiring area through the fourth TSV pillar.

[0042] Optionally, it also includes:

[0043] An intermediary layer is provided, the transmitting element is bonded to the intermediary layer through the second wiring layer, and the second wiring layer is electrically connected to the intermediary layer;

[0044] A receiving element is provided, the receiving element having a receiving circuit and a third wiring layer located on the surface of the receiving element, and is bonded in parallel to the transmitting element to the intermediate layer through the third wiring layer, the third wiring layer being electrically connected to the intermediate layer;

[0045] A molding layer is formed on the surface of the intermediate layer, and the molding layer covers the transmitting element and the receiving element;

[0046] A second TSV post is formed from the surface of the interposer away from the molding layer inward, penetrating the interposer. One end of the second TSV post is electrically connected to the second wiring layer and the third wiring layer, respectively. The other end of the second TSV post is exposed on the side of the interposer away from the molding layer.

[0047] A packaging substrate is provided, wherein the side of the interposer opposite to the molding layer is bonded to the packaging substrate, and the second TSV pillar is electrically connected to the packaging substrate;

[0048] A metal bump is formed on the side of the packaging substrate away from the interlayer, and the metal bump is electrically connected to the packaging substrate.

[0049] Optionally, the driving circuit integrates a serializer circuit; the receiving circuit integrates a deserializer circuit.

[0050] Optionally, it further includes: providing at least one SerDes chip, and bonding the SerDes chip to the interposer layer, arranging it side by side with the transmitting element and the receiving element, and electrically connecting the SerDes chip to the interposer layer; the SerDes chip is electrically connected to the transmitting element and the receiving element respectively through interconnect traces inside the interposer layer.

[0051] This application also provides an optical communication transmitting component, the transmitting component including a transmitting element, the transmitting element comprising:

[0052] A first wafer, the first wafer including a driving circuit near the front side of the first wafer;

[0053] The first wiring layer is located on the front side of the first wafer and is electrically connected to the driving circuit.

[0054] A micro-LED array is integrated on the surface of the first wiring layer and is electrically connected to the first wiring layer;

[0055] A light-transmitting protective layer covers the surface of the Micro-LED array and fills the gaps between the Micro-LED arrays, and the surface of the light-transmitting protective layer is higher than the surface of the Micro-LED array;

[0056] A first TSV pillar extends from the back of the first wafer through the first wiring layer to the first wiring layer and is electrically connected to the first wiring layer; a second wiring layer is located on the back of the first wafer and is electrically connected to the first wiring layer through the first TSV pillar.

[0057] Optionally, the light-transmitting protective layer has a microstructure, which acts as an optical coupler to couple the light emitted by the Micro-LED array to an optical communication receiver.

[0058] Optionally, the cross-sectional profile of the microstructure corresponding to the Micro-LED array is trapezoidal, and the apex of the trapezoid is chamfered or rounded.

[0059] Optionally, it further includes: an interposer layer, wherein the second wiring layer is bonded to the interposer layer and electrically connected to the interposer layer;

[0060] A receiving element having a receiving circuit and a third wiring layer located on the surface of the receiving element, and being bonded in parallel to the transmitting element to the intermediate layer via the third wiring layer, wherein the third wiring layer is electrically connected to the intermediate layer;

[0061] A molding compound is located on the surface of the intermediate layer, and the molding compound covers the transmitting element and the receiving element;

[0062] A packaging substrate is disposed on the side of the interposer layer opposite to the first wafer;

[0063] The second TSV pillar penetrates the interposer layer. One end of the second TSV pillar is electrically connected to the second wiring layer and the third wiring layer, respectively, and the other end of the second TSV pillar is electrically connected to the packaging substrate.

[0064] Metal bumps are located on the side of the packaging substrate away from the interposer layer and are electrically connected to the packaging substrate.

[0065] Optionally, the driving circuit integrates a serializer circuit; the receiving circuit integrates a deserializer circuit.

[0066] Optionally, it further includes: at least one SerDes chip, which is bonded to the interposer layer and arranged side by side with the transmitting element and the receiving element, and the SerDes chip is electrically connected to the interposer layer; the SerDes chip is electrically connected to the transmitting element and the receiving element respectively through interconnect traces inside the interposer layer.

[0067] Optionally, it also includes:

[0068] A receiving circuit is disposed in the first wafer, and the electrical signals of the driving circuit and the receiving circuit are independent of each other;

[0069] A PD layer is disposed between the Micro-LED array and the first wiring layer;

[0070] The PD layer includes a non-photosensitive area and a photosensitive area. Along a first direction perpendicular to the surface of the first wafer, the non-photosensitive area overlaps with the projection of the Micro-LED array, and the photosensitive area overlaps with the projection of the receiving circuit. The first wiring layer includes a driving wiring area and a receiving wiring area that are electrically isolated from each other. The Micro-LED array is electrically connected to the driving wiring area through a fourth TSV pillar penetrating the non-photosensitive area, and the photosensitive area is electrically connected to the receiving wiring area.

[0071] Optionally, the light-transmitting protective layer includes at least one of a silicon oxide layer, a silicon nitride layer, a spin-coated glass layer, or a transparent organic resin layer.

[0072] Optionally, the light-transmitting protective layer covers the PD layer and has a first microstructure corresponding to the Micro-LED array and a second microstructure corresponding to the photodetector of the photosensitive area.

[0073] In summary, this invention provides an optical communication transmitting component and its fabrication method, aiming to solve problems such as uneven support, residual contamination of temporary bonding materials, and easy warping and breakage of the thinned wafer encountered during back-side thinning, through-silicon via (TSV) and rewiring processes after heterogeneous integration of micro-LED arrays and driving circuit wafers. The core concept of this invention lies in adjusting the relative order of the Micro-LED array integration process with the back-side TSV process of the first wafer and the fabrication process of the second wiring layer to adapt to the process compatibility requirements of different device material systems. Both paths involve alternating bonding and removal of dual-sided temporary substrates, combined with the fabrication of the first TSV pillar and the second wiring layer on the back side, ensuring that the first wafer receives support during thinning and back-side processes, thus avoiding warping and breakage. In Option 1, after completing the electrical connection between the Micro-LED array and the first wiring layer on the front side of the wafer, a light-transmitting protective layer that functions as both a flat support surface and a permanent light-emitting window is prepared on the surface of the Micro-LED array. The light-transmitting protective layer is used for bi-directional time bonding and sequential debonding, ensuring that the first wafer is supported throughout the process while achieving back-side thinning and interconnection. Option 2, on the other hand, moves the high-temperature processes such as the first TSV hole etching process, insulating layer deposition, metal deposition, and metal annealing to the front side. After the back-side interconnection structure is completed, the Micro-LED array is then transferred and integrated onto the front side of the wafer.

[0074] Both of the above schemes ultimately form a second wiring layer on the back side of the driver wafer, allowing the emitting element to be directly bonded to the interposer layer through this wiring layer, achieving high-precision side-by-side integration and three-dimensional system-in-package with the receiving element. Scheme 1 avoids residual contamination from temporary bonding adhesive and improves light extraction efficiency through a permanent protective layer, while Scheme 2 effectively avoids potential thermal damage to the luminous efficiency and reliability of Micro-LEDs through pre-calculation of thermal budget. Both can be flexibly selected according to the characteristics of Micro-LED materials, balancing fabrication yield and device performance. Attached Figure Description

[0075] Figure 1 The diagram shows a process flow chart of the fabrication method of the optical communication transmitting component in an embodiment of the present invention.

[0076] Figure 2 The diagram shows a process flow chart of the optical communication transmitting component fabrication method in Embodiment 1 of the present invention.

[0077] Figure 3 The diagram shows a first wafer provided in Embodiment 1 of the present invention, after the first wiring layer has been formed.

[0078] Figure 4 The diagram shown is a schematic diagram of the structure after forming a Micro-LED array and a light-transmitting protective layer in Embodiment 1 of the present invention.

[0079] Figure 5 The diagram shows the structure of the first temporary substrate after it has been bonded to the light-transmitting protective layer in Embodiment 1 of the present invention.

[0080] Figure 6 The diagram shows the structure after the first TSV pillar is formed on the back side of the first wafer in Embodiment 1 of the present invention, and the second wiring layer is formed on the back side of the first wafer.

[0081] Figure 7 The diagram shows the structure of the second temporary substrate after it is bonded to the second wiring layer in Embodiment 1 of the present invention.

[0082] Figure 8 The diagram shows the structure after removing the first temporary substrate in Embodiment 1 of the present invention.

[0083] Figure 9 The diagram shows a process flow chart of the optical communication transmitting component fabrication method in Embodiment 2 of the present invention.

[0084] Figure 10 The diagram shows the structure of the first temporary substrate after it has been bonded to the first wiring layer in Embodiment 2 of the present invention.

[0085] Figure 11 The diagram shown is a schematic representation of the structure of the first wafer after thinning in Embodiment 2 of the present invention.

[0086] Figure 12 The diagram shows the structure after the first TSV pillar is formed by thinning the back side of the first wafer in Embodiment 2 of the present invention, and the second wiring layer is formed on the back side of the first wafer.

[0087] Figure 13 This is a schematic diagram of the structure after the second temporary substrate is bonded to the second wiring layer in Embodiment 2 of the present invention.

[0088] Figure 14 The diagram shows the structure after removing the first temporary substrate in Embodiment 2 of the present invention.

[0089] Figure 15 The diagram shows the structure after forming the Micro-LED array and the light-transmitting protective layer in Embodiment 2 of the present invention.

[0090] Figure 16The diagram shows the structure after removing the second temporary substrate in an embodiment of the present invention.

[0091] Figure 17 The diagram shown is a schematic representation of the structure after the transmitting element is bonded to the intermediary layer in an embodiment of the present invention.

[0092] Figure 18 The diagram shown is a schematic diagram of the structure after the light-transmitting protective layer is formed into a microstructure in an embodiment of the present invention, and the microstructure outline is trapezoidal.

[0093] Figure 19 The diagram shows the structure of the transmitting element and the receiving element bonded side by side to the interposer layer in an embodiment of the present invention, and then integrated into the packaging substrate.

[0094] Figure 20 The diagram shown is a structural schematic of the SerDes chip provided in an embodiment of the present invention.

[0095] Figure 21 The diagram shows the structure of the SerDes chip after it has been bonded to the intermediary layer in an embodiment of the present invention.

[0096] Figure 22 The diagram shows the structure after the transmitting element, receiving element, and SerDes chip are bonded side by side to the interposer, then bonded to the packaging substrate, and finally integrated into the PCB board in an embodiment of the present invention.

[0097] Figure 23 The diagram shows the structure of the Micro-LED array after it is electrically connected to the first wiring layer via the fourth TSV pillar in an embodiment of the present invention.

[0098] Explanation of reference numerals in the attached figures

[0099] 11. Emitter element; 12. Receiver element; 13. SerDes chip; 100. First wafer; 110. First wiring layer; 111. First lead-out structure; 112. Driver wiring layer; 113. Receiver wiring area; 120. Micro-LED array; 121. First bump; 122. Light-transmitting protective layer; 123. Microstructure; 130. Second wiring layer; 131. Second lead-out structure; 132. First bonding wiring area; 133. Second bonding wiring area; 140. First TSV pillar; 210. First temporary substrate; 230. Third wiring layer; 300. Second temporary substrate; 400. Intermediate layer; 500, Packaging substrate; 510, Second TSV pillar; 520, Molding layer; 530, Third TSV pillar; 540, Metal bump; 600, PCB board; 700, SerDes wafer; 710, Sixth wiring layer; 800, PD layer; 810, Fourth TSV pillar. Detailed Implementation

[0100] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0101] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0102] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0103] Please see Figures 1-23 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of components in implementation. In actual implementation, the type, quantity, and proportion of each component can be arbitrarily changed, and the component layout may also be more complex. This embodiment provides a method for fabricating an optical communication transmitting component; please refer to [link to relevant documentation]. Figure 1 , Figure 8 and Figure 9 The diagram shows the fabrication process of an optical communication transmitting component, including:

[0104] A first wafer 100 is provided, the first wafer 100 including driving circuitry near the front side of the first wafer 100;

[0105] A first wiring layer 110 is formed on the front side of the first wafer 100, and the first wiring layer 110 is electrically connected to the driving circuit.

[0106] A structure to be cut is formed based on a first temporary substrate 210, a second temporary substrate 300, and a light-transmitting protective layer 122; wherein:

[0107] The structure to be cut includes a first TSV pillar 140 formed from the back side of the first wafer 100 and electrically connected to the first wiring layer 110; an array of light-emitting elements on the surface of the first wiring layer 110; and a second wiring layer 130 on the back side of the first wafer 100 that is electrically connected to the first wiring layer 110 through the first TSV pillar 140.

[0108] The light-transmitting protective layer 122 is formed on the surface of the light-emitting element array. The first temporary substrate 210 is bonded to the side of the first wiring layer 110 away from the second wiring layer 130. The second temporary substrate 300 is bonded to the surface of the second wiring layer 130. The first temporary substrate 210 is removed based on the second temporary substrate 300 to form the cut structure including the light-transmitting protective layer 122. In addition, the light-emitting element array can be a Micro-LED array 120. As mentioned above, the integration of Micro-LED arrays is crucial in the field of optical interconnects. The following implementations are all described with the light-emitting element array being a Micro-LED array.

[0109] The structure to be cut is cut to form a plurality of emitting elements 11, wherein the emitting elements 11 integrate the light-emitting element array and the driving circuit.

[0110] The following will describe specific embodiments one and two. The core difference between embodiments one and two lies in the process sequence of integrating the Micro-LED array 120 and forming the light-transmitting protective layer 122. In embodiment one, the integration of the Micro-LED array 120 and the formation of the light-transmitting protective layer 122 are completed before the back-side thinning and TSV processes, while in embodiment two, these two steps are postponed to after the back-side processes. Specifically: First, a first wiring layer 110 is formed on the front side of the first wafer 100, and a first temporary substrate 210 is bonded to the surface of the first wiring layer 110. Then, back-side thinning, the first TSV via, and the fabrication of the back-side second wiring layer 130 are performed. Subsequently, a second temporary substrate 300 is bonded and the first temporary substrate 210 is removed. Next, the Micro-LED array 120 is integrated on the exposed surface of the first wiring layer 110 on the front side of the first wafer 100, and a light-transmitting protective layer 1220 is formed. Finally, the second temporary substrate 300 is removed.

[0111] Please refer to the following for details:

[0112] Example 1

[0113] This embodiment provides a method for fabricating an optical communication transmitting component. Please refer to [link / reference]. Figure 2 The diagram shows the fabrication process of an optical communication transmitting component, including:

[0114] See Figure 2 and Figure 3 Step S1-1 is executed, providing a first wafer 100, the first wafer 100 including a driving circuit near the front side of the first wafer 100.

[0115] Specifically, the driving circuit is integrated within the first wafer 100, and is located close to the front side of the first wafer 100 for providing driving signals to the Micro-LED array 120. The driving circuit may include, for example, CMOS transistors, row / column scanning circuits, etc., and can be specifically designed according to the scale of the Micro-LED array 120 to be driven and the application scenario. The first wafer 100 may be a silicon wafer or a silicon-on-insulator (SOI) wafer, and its front side is typically chemically mechanically polished (CMP) to have a flat surface to facilitate the formation of subsequent wiring layers.

[0116] As an example, the drive circuit integrates a serializer circuit.

[0117] Specifically, the serializer circuit is integrated inside the driver circuit, which can convert parallel data into high-speed serial signals to drive the Micro-LED array 120. This integration method eliminates the need for an external independent SerDes chip 13 (serializer / deserializer chip), reduces the package area, and lowers signal transmission delay and power consumption.

[0118] Next, refer to Figure 2 and Figure 3 In step S1-2, a first wiring layer 110 is formed on the front side of the first wafer 100, and the first wiring layer 110 is electrically connected to the driving circuit.

[0119] Specifically, one or more metal interconnect structures can be formed through processes such as depositing a dielectric layer, photolithography, etching, and electroplating. The first wiring layer 110 is electrically connected to the output terminal of the driving circuit. The first wiring layer 110 may include conductive materials such as aluminum or copper, and its top may be provided with a first lead-out portion 111 for subsequent integration of the Micro-LED array 120. The first lead-out portion 111 may be a first pad or a bonding metal layer. The first wiring layer 110 not only serves as a redistribution layer for the driving signal but also acts as a bridge connecting the driving circuit and the Micro-LED array 120. To improve reliability, a passivation layer can be formed on the surface of the first wiring layer 110, and the first lead-out portion 111 can be planarized and exposed to ensure that the bonding surface of the subsequent Micro-LED array 120 has good flatness.

[0120] Next, refer to Figure 2 and Figure 4Steps S1-3 are executed to integrate a Micro-LED array 120 on the surface of the first wiring layer 110, wherein the Micro-LED array 120 is electrically connected to the first wiring layer 110.

[0121] As an example, the Micro-LED array 120 is electrically connected to the first wiring layer 110 by flip-chip bonding, metal-to-metal bonding or hybrid bonding. The heterogeneous integration of the Micro-LED array 120 with the first wafer 100 can be achieved by mass transfer or by die-to-wafer.

[0122] Specifically, the pre-prepared Micro-LED array 120 can be transferred to the first lead-out portion 111 and electrically connected through flip-chip bonding, metal-to-metal thermoforming bonding, or hybrid bonding. During transfer, an elastic mold or electrostatic adsorption head can be used to massively transfer the Micro-LED array 120 to the wafer-level driving substrate. After precise alignment, pressure and heating are applied to ensure stable and reliable contact between the first bump 121 at the bottom of the Micro-LED array 120 and the first lead-out portion 111. After integration, the cathode and anode of the Micro-LED array 120 are connected to the output terminals of the corresponding driving circuits through the first wiring layer 110, thereby enabling control of each Micro-LED. To ensure bonding quality, annealing can be performed after bonding to improve the intermetallic bonding strength and reduce contact resistance. It is understood that the electrical connection structure at the bottom of the Micro-LED array 120 is not limited to the first bump 121; other forms such as metal layers or direct bonding interfaces can also be used, depending on the actual bonding process.

[0123] Next, refer to Figure 2 and Figure 4 Steps S1-4 are executed to form a light-transmitting protective layer 122 on the surface of the Micro-LED array 120. The light-transmitting protective layer 122 covers the Micro-LED array 120 and fills its gaps, and the surface of the light-transmitting protective layer 122 is higher than the surface of the Micro-LED array 120.

[0124] As an example, the material of the light-transmitting protective layer 122 includes at least one of silicon oxide, silicon nitride, spin-coated glass, or transparent organic resin.

[0125] Specifically, the light-transmitting protective layer 122 can be made of a transparent material with a refractive index between that of the light-emitting layer material of the Micro-LED array 120 and air, to reduce total internal reflection, improve light extraction efficiency, and fill the gaps in the Micro-LED array 120, facilitating subsequent back-side processes. The spin-coated glass (SOG) has good flow and filling properties, allowing it to fully penetrate the gaps in the Micro-LED array 120 and form a flat surface. The transparent organic resin, such as polyimide or benzocyclobutene (BCB), provides a lower curing temperature and better mechanical flexibility. The silicon oxide or silicon nitride can be deposited via chemical vapor deposition to form a dense inorganic protective layer, exhibiting excellent heat resistance and chemical corrosion resistance. The above materials can be selected based on specific process compatibility and optical requirements. In the integrated optical communication system of this embodiment, the light-transmitting protective layer 122 preferably uses spin-coated glass (SOG) or benzocyclobutene (BCB), both of which have good filling properties, high light transmittance, and process compatibility.

[0126] As an example, after forming the light-transmitting protective layer 122, the upper surface of the light-transmitting protective layer 122 is further subjected to chemical mechanical polishing to flatten it, so as to eliminate local surface unevenness and thickness fluctuation, and provide a high-flatness interface for subsequent uniform bonding with the first temporary substrate 210, avoiding uneven support and residual contamination that occur in subsequent thinning processes and back-side processes.

[0127] Next, refer to Figure 2 and Figure 5 Steps S1-5 are executed, a first temporary substrate 210 is provided, and the first temporary substrate 210 is bonded to the surface of the light-transmitting protective layer 122.

[0128] Specifically, a first temporary substrate 210 is provided. The first temporary substrate 210 can be a glass substrate, a silicon substrate, or other rigid carrier plate. A first temporary bonding layer is pre-coated on its surface. The light-transmitting protective layer 122 is aligned with the bonding surface of the first temporary substrate 210. Temporary bonding is achieved by applying hot pressing, ultraviolet irradiation, or vacuum lamination to ensure that the upper surface of the light-transmitting protective layer 122 is tightly bonded to the first temporary bonding layer on the first temporary substrate 210. The temperature, pressure, and time of the bonding process need to be optimized based on the material properties of the first temporary bonding layer. This ensures sufficient adhesion strength to withstand subsequent thinning and back-side processes while avoiding thermal damage to the Micro-LED array 120 and the driving circuit due to high temperatures. After bonding, the light-transmitting protective layer 122 forms a strong temporary connection with the first temporary substrate 210, effectively supporting and protecting the surface of the Micro-LED array 120, providing a stable mechanical foundation for subsequent wafer thinning and back-side TSV processing.

[0129] Next, refer to Figure 2 and Figure 6 In steps S1-6, the back side of the first wafer 100 is thinned, and a first TSV hole is formed downward from the back side of the first wafer 100 and filled to form a first TSV pillar 140. The first TSV pillar 140 is electrically connected to the first wiring layer 110.

[0130] Specifically, a combination of mechanical grinding and chemical mechanical polishing (CMP) is used to remove a certain thickness of silicon material from the back side of the first wafer 100, thinning the first wafer 100 to the target thickness. After thinning, the first wafer 100 is firmly supported on its front side by the light-transmitting protective layer 122 and the first temporary substrate 210, effectively suppressing the risk of warping and breakage. After thinning, the opening positions of the first TSV (Through Silicon Via) are defined on the back side of the first wafer 100 using photolithography. Deep reactive ion etching (DRIE, such as the Bosch process) or laser drilling is then used to etch vertically through the first TSV from the back side downwards until the metal pads or conductive areas at the bottom of the first wiring layer 110 are exposed. After etching, the first TSV is cleaned to remove residual polymer. Then, an insulating layer (such as silicon dioxide or silicon nitride), a diffusion barrier layer (such as titanium, tantalum, or titanium nitride), and a seed layer (such as copper) are sequentially deposited on the sidewalls and bottom of the hole. An insulating layer isolates the first TSV via from the silicon substrate, and the barrier layer and seed layer provide a conductive base for subsequent electroplating. Finally, a conductive material (such as copper) is electroplated to fill the first TSV via, and excess metal on the back side is removed by chemical mechanical polishing, forming a flat first TSV pillar 140. One end of the first TSV pillar 140 forms an ohmic contact with the first wiring layer 110, thereby achieving a low-resistance electrical connection from the back side of the wafer to the front-side drive circuitry.

[0131] Next, refer to Figure 2 and Figure 6 Steps S1-7 are executed to form a second wiring layer 130 on the back side of the first wafer 100. The second wiring layer 130 is electrically connected to the first wiring layer 110 through the first TSV pillar 140.

[0132] Specifically, firstly, an insulating dielectric layer (such as silicon dioxide, silicon nitride, or polyimide) is deposited on the back side of the first wafer 100 using chemical vapor deposition or spin coating. Then, openings are made at positions corresponding to the first TSV pillars 140 using photolithography and etching processes, exposing the end faces of the first TSV pillars 140. Subsequently, a metal seed layer is formed using physical vapor deposition or electroplating. Then, one or more layers of metal wiring (materials such as copper, aluminum, or titanium / copper composite layers) are patterned through photolithography, electroplating, and etching steps, enabling reliable ohmic contact between the metal wiring layer and the first TSV pillars 140. If necessary, the dielectric layer deposition, opening, and metallization processes can be repeated to form a multi-layer rewiring structure (e.g., 2-4 layers) to meet high-density interconnect requirements. Finally, the upper surface of the second wiring layer 130 is planarized using chemical mechanical polishing or planarization to facilitate subsequent bonding with the second temporary substrate 300. The second wiring layer 130 is electrically connected to the first wiring layer 110 on the front side through the first TSV pillar 140, thereby leading the electrical signal of the driving circuit from the front side of the first wafer 100 to the back side, realizing the high-density interconnection of the back side of the transmitting element 11.

[0133] It should be noted that the formation method of the second wiring layer 130 is only an example. Those skilled in the art can also adopt other conventional wiring layer fabrication processes (such as damask process, direct metal deposition method, etc.) or further extend the wiring layer to form a fan-out structure according to actual needs, as long as it can achieve electrical connection with the first TSV pillar 140 and meet the subsequent bonding requirements.

[0134] Next, refer to Figure 2 and Figure 7 Steps S1-8 are executed, a second temporary substrate 300 is provided, and the second temporary substrate 300 is bonded to the surface of the second wiring layer 130.

[0135] Specifically, a second temporary substrate 300 is provided. The second temporary substrate 300 may be a glass substrate, a silicon substrate or other rigid carrier plate, and its surface is pre-coated with the second temporary bonding layer for temporary bonding with the surface of the second wiring layer 130.

[0136] Next, refer to Figure 2 and Figure 8 Then, perform steps S1-9 to remove the first temporary substrate 210 and expose the light-transmitting protective layer 122.

[0137] Specifically, based on the material properties of the first temporary bonding layer, a suitable debonding method is selected to remove the first temporary substrate 210 from the surface of the light-transmitting protective layer 122. After debonding, the surface of the light-transmitting protective layer 122 is exposed, and the surface is flat, clean, and free of residues, which can serve as a light-emitting window for subsequent dicing and corresponding chips, with minimal impact on light emission efficiency. Thus, in this example, the first temporary substrate 210 is formed on the surface of the light-transmitting protective layer 122 after the front-side process, and the first temporary substrate 210 on the surface of the light-transmitting protective layer 122 is removed based on the second temporary substrate 300 formed on the surface of the second wiring layer 130 after the back-side process, which is beneficial to the stability of the light-transmitting protective layer 122 and the stability of the process implementation.

[0138] Next, refer to Figure 2 and Figure 8 Then, perform steps S1-10 to remove the second temporary substrate 300 and expose the second wiring layer 130.

[0139] Specifically, based on the material properties of the second temporary bonding layer, an appropriate debonding method is selected to remove the second temporary substrate 300 from the back side of the second wiring layer 130. After removing the second temporary substrate 300, the lower surface of the second wiring layer 130 is fully exposed. The surface of the second wiring layer 130 has undergone planarization treatment, resulting in a smooth, clean surface free of residue. At this point, the first wafer 100 no longer has any temporary carrier support, and the back side of the second wiring layer 130 exposed after removing the temporary substrate can be directly attached to the dicing tape. The dicing tape provides sufficient mechanical support for subsequent dicing processes, ensuring the stability and accuracy of the subsequent dicing processes.

[0140] Next, refer to Figure 2 and Figure 17 Steps S1-11 are executed to cut the current structure to form multiple emitting elements 11, wherein the emitting elements 11 integrate the Micro-LED array 120 and the driving circuit.

[0141] Specifically, under the mechanical support of the cutting tape, the first wafer 100 is fully or partially cut along the dicing lines using blade cutting or laser stealth cutting methods, dividing the first wafer 100 into multiple independent emitting elements 11. After cutting, the emitting elements 11 are picked up one by one from the dicing film by ultraviolet light irradiation or mechanical pins. Each emitting element 11 fully integrates the Micro-LED array 120 and the driving circuit, and its front side is covered with a flat light-transmitting protective layer 122, while the back side exposes the second wiring layer 130 (which can be further fabricated with microbumps). At this point, the emitting element 11 can be used for high-precision bonding with the subsequent interposer layer 400. This cutting method ensures that the edges of the emitting element 11 are smooth and free of delamination, and maintains the cleanliness of the front and back sides of the emitting element 11, providing a reliable independent device for subsequent packaging.

[0142] As an example, the method for fabricating the optical communication transmitting component further includes:

[0143] See Figure 18 In step S1-12, an intermediary layer 400 is provided. The transmitting element 11 is bonded to the intermediary layer 400 through the second wiring layer 130, and the second wiring layer 130 is electrically connected to the intermediary layer 400.

[0144] As an example, the interposer 400 may include a silicon interposer, an RDL interposer, or an interposer that includes a silicon substrate and a redistribution layer located on the silicon substrate, wherein through-silicon vias are formed in the silicon substrate.

[0145] Specifically, the interposer 400 is preferably a silicon interposer with through-silicon vias (TSVs). Its front side has a second lead structure 131 that matches the second wiring layer 130 of the emitter element 11; this can be a second pad, microbump, or redistribution layer. The back side can have solder balls for external connections. The emitter element 11, as described above, is picked up and flipped (or placed directly) so that the surface of the second wiring layer 130 is aligned with the corresponding pad on the front side of the interposer 400. A flip-chip bonding process, such as thermoforming, reflow soldering, or hybrid bonding, is used to form a robust electrical connection between the metal bumps or planarization pads of the second wiring layer 130 and the second lead 131 of the interposer 400. In some embodiments, the gap between the emitter element 11 and the interposer 400 can be filled with an underfill layer (not shown) to buffer thermal stress and improve reliability.

[0146] This embodiment employs double-sided bonding and a specific debonding sequence (first bonding the first temporary substrate 210, then bonding the second temporary substrate, and finally removing the first temporary substrate 210), ensuring that the first wafer 100 is always supported by at least one temporary substrate before thinning and back-side processing, effectively preventing warping and breakage. The second temporary substrate 300 is then removed before dicing. The driving circuit of the emitter element 11 is connected to an external system via the internal circuitry of the second wiring layer 130 and the interposer layer 400, achieving high-density packaging and system integration of the emitter element 11. The interposer layer 400 can serve as a common platform for multi-chip integration, facilitating subsequent assembly with other chips. Thus, the fabrication steps of the emitter unit in the semiconductor structure are completed.

[0147] See Figure 19 In step S1-13, a receiving element 12 is provided, which has a receiving circuit and a third wiring layer 230 located on the surface of the receiving element 12, and is bonded to the transmitting element 11 in parallel to the intermediary layer 400 through the third wiring layer 230.

[0148] As an example, the receiving element 12 may include a photodetector (such as a single-photon avalanche diode (SPAD), an APD (avalanche photodiode), or a PIN photodiode) and a matching readout circuit, the specific structure of which may employ techniques known in the art.

[0149] In one specific embodiment, the receiving element 12 may employ a stacked wafer structure, details of which are not illustrated. The receiving element 12 includes a third wafer located on top and a second wafer located below. The front side of the third wafer includes a photodiode array (such as SPAD, APD, or PIN photodiodes) and a fifth wiring layer, while its back side has a microlens array for receiving incident light. The front side of the second wafer includes a receiving circuit and a fourth wiring layer. The fifth wiring layer of the third wafer and the fourth wiring layer of the second wafer are directly connected by hybrid bonding to achieve electrical interconnection. Of course, the specific structure and fabrication steps of the receiving element 12 are not limited to this.

[0150] See Figure 19 Steps S1-14 are executed to form a molding compound 520 on the surface of the intermediate layer 400, the molding compound 520 covering the transmitting element 11 and the receiving element 12.

[0151] Specifically, the molding compound 520 covers the transmitting element 11 and the receiving element 12, providing physical protection and environmental isolation for the heterogeneous integrated structure, preventing damage from moisture, particles, and mechanical forces. Simultaneously, the molding compound 520 can fill gaps between devices and flatten surfaces, facilitating subsequent heat dissipation or the fabrication of electromagnetic shielding layers, thereby improving module reliability.

[0152] See Figure 19 In step S1-15, a second TSV post 510 is formed from the surface of the intermediary layer 400 away from the molding layer 520 inward, penetrating the intermediary layer 400. One end of the second TSV post 510 is electrically connected to the second wiring layer 130 and the third wiring layer 230, respectively, and the other end of the second TSV post 510 is exposed on the side of the intermediary layer 400 away from the molding layer 520.

[0153] Specifically, the structure of the second TSV pillar 510 can fan out the high-density interconnect signals of the transmitting element 11 and the receiving element 12 downwards, so that the bottom of the interposer layer 400 can be directly integrated onto the surface of the subsequent packaging substrate 500 to form a complete three-dimensional packaging module.

[0154] See Figure 19 In step S1-16, a packaging substrate 500 is provided, the side of the interposer 400 facing away from the molding layer 520 is bonded to the packaging substrate 500, and the second TSV post 510 is electrically connected to the packaging substrate 500.

[0155] Specifically, by bonding the second TSV pillar 510 on the bottom surface of the interposer 400 to the packaging substrate 500 as described above, vertical electrical connection between the transmitting element 11 and the receiving element 12 and the external system is achieved. The packaging substrate 500 provides mechanical support and signal fan-out for the interposer 400, thereby completing three-dimensional system integration from the chip level to the board level. In an optional embodiment, an isolation structure, such as a trench isolation structure penetrating the interposer 400, can be formed in the interposer 400. This can isolate the signal transmission of each independent chip disposed on the interposer 400, which is beneficial for the independent fabrication of different chips and stable packaging, improving the performance of each independent chip while improving packaging stability.

[0156] See Figure 19 In step S1-17, a metal bump 540 is formed on the side of the packaging substrate 500 away from the interposer layer 400, and the metal bump 540 is electrically connected to the packaging substrate 500.

[0157] Specifically, the metal bump 540 is electrically connected to the wiring layer and pads inside the packaging substrate 500, serving as an interface for electrical interconnection of the package to the outside world, and is used for subsequent flip-chip soldering with printed circuit boards or other external circuit boards.

[0158] See Figure 19After the integration of the packaging substrate 500 is completed, a third TSV pillar 530 is formed inward from the side of the packaging substrate 500 away from the interposer layer 400. One end of the third TSV pillar 530 is electrically connected to the internal circuitry of the packaging substrate 500. Subsequently, a PCB board 600 or other circuit board is provided, and the packaging substrate 500 is bonded to the PCB board 600 or other circuit board through metal bumps 540, thereby realizing the final fan-out and interconnection of the signals of the transmitting element 11 and the receiving element 12 to external systems (such as motherboard, power supply, data interface).

[0159] As an example, the receiving circuit integrates a deserializer circuit.

[0160] Specifically, the deserializer circuit is integrated within the receiving circuit, and can deserialize the received serial data into parallel data. This integration eliminates the need for an external, separate SerDes chip 13, reducing the package area and lowering signal transmission delay and power consumption.

[0161] As an example, see Figures 20-22 When the serializer and / or the receiver circuit does not integrate a serializer and a deserializer circuit, the method further includes: providing at least one SerDes chip 13, and bonding the SerDes chip 13 to the interposer layer 400, which is arranged side by side with the transmitting element 11 and the receiving element 12, and the SerDes chip 13 is electrically connected to the interposer layer 400; the SerDes chip 13 is electrically connected to the transmitting element 11 and the receiving element 12 respectively through interconnection traces inside the interposer layer 400.

[0162] Specifically, see Figure 22 The SerDes chip 13 includes a SerDes wafer 700 and a sixth wiring layer 710 formed on the surface of the SerDes wafer 700. The sixth wiring layer 710 is electrically connected to corresponding functional components through the second TSV pillars 510 in the interposer layer 400, providing them with serialization / deserialization functions. This solution can flexibly adapt to the high-speed data interface requirements of different application scenarios without changing the existing driver circuit design or receiver circuit design, reducing process flow and cost.

[0163] This embodiment first integrates the Micro-LED array and then performs back-side interconnection. Specifically: First, the Micro-LED array is integrated on the first wiring layer on the front side of the first wafer. Then, a light-transmitting protective layer is formed on the surface of the Micro-LED array, covering all light-emitting units and filling their gaps, with the surface of the light-transmitting protective layer higher than the top surface of the Micro-LED array. A first temporary substrate is bonded to the surface of the light-transmitting protective layer, and back-side thinning, TSV, and back-side second wiring layer fabrication are performed. Subsequently, a second temporary substrate is bonded and the first temporary substrate is removed, followed by the removal of the second temporary substrate. This path utilizes the light-transmitting protective layer as a bonding interface, ensuring uniform distribution of support pressure during back-side thinning and avoiding stress concentration caused by the protruding structure of the Micro-LED array. After fulfilling its temporary support function, the protective layer is permanently retained on the device surface, preventing warping, breakage, or deformation of the thinned first wafer during back-side processing and temporary substrate removal. Simultaneously, the light-transmitting protective layer also functions as a light-emitting window, avoiding contamination of the light-emitting surface by traditional temporary bonding adhesive residue, and improving light extraction efficiency through refractive index matching design.

[0164] It should be noted that the specific structural dimensions, materials, and number of layers described in this embodiment are merely examples and not intended to limit the invention. Those skilled in the art can reasonably adjust the above parameters without departing from the core structural features of this invention, and these adjusted solutions still fall within the protection scope of this invention.

[0165] Example 2

[0166] This embodiment provides a method for fabricating an optical communication transmitting component. Unlike Embodiment 1, the steps of forming the Micro-LED array and the light-transmitting protective layer are performed after removing the first temporary substrate. Please refer to [link to previous document]. Figure 9 The diagram shows the fabrication process of an optical communication transmitting component, including:

[0167] First, refer to Figure 9 and Figure 3 Step S2-1 is executed, providing a first wafer 100, the first wafer 100 including a driving circuit near the front side of the first wafer 100.

[0168] Next, refer to Figure 9 and Figure 3 In step S2-2, a first wiring layer 110 is formed on the front side of the first wafer 100, and the first wiring layer 110 is electrically connected to the driving circuit.

[0169] The processes of steps S2-1 and S2-2 are the same as those in Example 1. For the specific process, please refer to Example 1. They will not be repeated here.

[0170] Next, refer to Figure 9 and Figure 11 Step S2-3 is executed, a first temporary substrate 210 is provided, and the first temporary substrate 210 is bonded to the first wiring layer 110.

[0171] Specifically, the first temporary substrate 210 is made of a rigid material such as silicon or glass and is dimensionally matched. A tight connection is formed by applying pressure and temperature using hot-pressing or adhesive bonding techniques. The bonded structure provides a mechanical foundation, prevents warping and displacement during processing, and ensures thermal conduction and electrical isolation. This allows subsequent operations such as grinding, etching, or multilayer integration to be performed on the back side of the first wiring layer 110, reducing defects and improving device performance and yield.

[0172] Next, refer to Figure 9 and Figure 12 Steps S2-4 are executed to thin the back side of the first wafer 100; a first TSV hole is formed downward from the back side of the first wafer 100 and filled to form a first TSV pillar 140, wherein the first TSV pillar 140 is electrically connected to the first wiring layer 110.

[0173] Specifically, the back side of the first wafer 100 is thinned using mechanical grinding and chemical mechanical polishing. After thinning, the first wafer 100 is supported by the first temporary substrate 210 to suppress warping. The first TSV via is formed on the back side by photolithography and etching, penetrating vertically until the first wiring layer 110 is exposed. After cleaning, an insulating layer and a seed layer are deposited, and the first TSV pillar 140 is formed by electroplating and filling with conductive material, achieving electrical connection with the first wiring layer 110.

[0174] Next, refer to Figure 9 and Figure 13 In step S2-5, a second wiring layer 130 is formed on the back side of the first wafer 100. The second wiring layer 130 is electrically connected to the first wiring layer 110 through the first TSV pillar 140.

[0175] Specifically, the process includes depositing an insulating layer on the back side of the thinned first wafer 100, patterning wiring paths through photolithography and etching, and then filling with conductive material to form metal interconnects. The second wiring layer 130 is in direct contact with the top of the first TSV pillar 140, thereby establishing a vertical electrical connection, supporting three-dimensional integration and improving circuit performance. Specific processes and materials can be found in Embodiment 1.

[0176] Next, refer to Figure 9 and 13 Steps S2-6 are executed, a second temporary substrate 300 is provided, and the second temporary substrate 300 is bonded to the surface of the second wiring layer 130.

[0177] Specifically, a second temporary substrate 300 is provided. The second temporary substrate 300 may be a glass substrate, a silicon substrate or other rigid carrier plate, and its surface is pre-coated with the second temporary bonding layer for temporary bonding with the surface of the second wiring layer 130.

[0178] Next, refer to Figure 9 and 14 Then, perform steps S2-7 to remove the first temporary substrate 210 and expose the first wiring layer 110.

[0179] Specifically, this step can be achieved through methods such as laser dissociation or thermal release, depending on the properties of the temporary bonding material, such as using a soluble adhesive or a thermally sensitive adhesive layer. After removing the first temporary substrate 210, the first wiring layer 110 is fully exposed, providing a foundation for the subsequent integration of the Micro-LED array 120. The first temporary substrate 210 serves as mechanical support and prevents warping in the early stages of the process. Exposing the first wiring layer 110 ensures the integrity of the vertical interconnects, supporting the final formation of the three-dimensional packaging structure.

[0180] Next, refer to Figure 9 and Figure 15 Steps S2-8 are executed to form a Micro-LED array 120 on the surface of the first wiring layer 110, and the Micro-LED array 120 is electrically connected to the first wiring layer 110.

[0181] In some embodiments, prior to integrating the Micro-LED array 120, the surface of the first wiring layer 110 is pretreated, for example, by plasma cleaning to remove surface oxides and organic contaminants and activate the metal surface. Flux or anisotropic conductive adhesive is selectively coated onto the activated surface of the first wiring layer 110 to enhance the bonding strength and conductivity reliability of the subsequent electrical connection between the Micro-LED array 120 and the first wiring layer 110.

[0182] As an example, the Micro-LED array 120 is electrically connected to the first wiring layer 110 via flip-chip bonding, metal-to-metal bonding, or hybrid bonding. Specifically, during the integration of the Micro-LED array 120, a flexible mold or electrostatic adsorption head is used to massively transfer the Micro-LED array 120 to the driving substrate, and then, after alignment, pressure and heating are applied to bring the first bump 121 into contact with the pad. See Embodiment 1 for details.

[0183] Next, refer to Figure 9 and Figure 15Step S2-9 is executed, in which a light-transmitting protective layer 122 is formed on the surface of the Micro-LED array 120. The light-transmitting protective layer 122 covers the Micro-LED array 120 and fills its gaps, and the surface of the light-transmitting protective layer 122 is higher than the surface of the Micro-LED array 120.

[0184] As an example, the material of the light-transmitting protective layer 122 includes at least one of silicon oxide, silicon nitride, spin-coated glass, or transparent organic resin. Specifically, the material selection for the light-transmitting protective layer 122 needs to consider the refractive index to reduce total internal reflection and improve light extraction efficiency. In optical communication systems, spin-coated glass or benzocyclobutene are preferred due to their good filling properties and light transmittance.

[0185] As an example, after forming the light-transmitting protective layer 122, the method further includes a step of chemically and mechanically polishing the upper surface of the light-transmitting protective layer 122 to flatten it, so as to eliminate local unevenness and thickness fluctuations on the surface, thereby providing a highly flat surface for the light-transmitting protective layer 122 as a light-emitting window, and avoiding contamination that may occur during the cutting and packaging process.

[0186] As an example, a microstructure 123 is formed based on the light-transmitting protective layer 122. This microstructure acts as an optical coupler, coupling the light emitted from the Micro-LED array 120 to an optical transmission element and then to an optical receiving element. For instance, the microstructure 123 couples the light emitted from the Micro-LED array 120 to an optical fiber, which then transmits the light to the optical receiving device. This simplifies the overall interconnect architecture during the optimization of the optical emitting component fabrication process. Specifically, the formation of the microstructure 123 can be performed after the formation of the light-transmitting protective layer 122 to achieve optical path micro-shaping, such as by additionally configuring the microstructure or processing the light-transmitting protective layer 122 to obtain the microstructure 123. Alternatively, the light-transmitting protective layer 122 with the microstructure 123 can be formed directly during the formation of the light-transmitting protective layer 122, thereby achieving the formation of the optical path shaping component in this process and simplifying the process.

[0187] As an example, see Figure 16 The microstructure 123 has a trapezoidal cross-sectional profile corresponding to the Micro-LED array 120, and the top corner of the trapezoid is chamfered or rounded.

[0188] Specifically, the microstructure 123 is disposed on the light-emitting side of the Micro-LED array 120, and the outer contour of the longitudinal section of the microstructure 110 along its height direction (i.e., the direction perpendicular to the plane where the Micro-LED array 120 is located) is trapezoidal. Specifically, when the outer contour of the longitudinal section of the microstructure 123 is trapezoidal, the apex of the trapezoid is chamfered or rounded to avoid stress concentration caused by sharp edges and to facilitate uniform coverage of subsequent film layers. The microstructure 123 can effectively change the focusing of the emitted light from the Micro-LED array 120 at the interface, effectively reducing the emission angle of the beam and matching the emission angle of the light with the subsequent optical waveguide, thereby significantly improving the coupling effect; at the same time, its design without sharp edges at the top helps to eliminate stress concentration, improving device reliability and process yield.

[0189] Next, refer to Figure 9 and Figure 17 Then, perform step S2-10 to remove the second temporary substrate 300 and expose the second wiring layer 130.

[0190] Next, refer to Figure 9 and Figure 17 Step S2-11 is executed to cut the current structure to form multiple emitting elements 11, wherein the emitting elements 11 integrate the Micro-LED array 120 and the driving circuit.

[0191] The structure and process of steps S2-10 to S2-11 are the same as those of S1-10 to S1-11 in Example 1. For details, please refer to Example 1, which will not be described in detail here.

[0192] As an example, the method for fabricating the optical communication transmitting component further includes:

[0193] See Figure 9 and Figure 18 In step S2-12, an intermediary layer 400 is provided, the transmitting element 11 is bonded to the intermediary layer 400 through the second wiring layer 130, and the second wiring layer 130 is electrically connected to the intermediary layer 400.

[0194] See Figure 19 In step S2-13, a receiving element 12 is provided, which has a receiving circuit and a third wiring layer 230 located on the surface of the receiving element 12, and is bonded to the transmitting element 11 in parallel to the intermediary layer 400 through the third wiring layer 230.

[0195] See Figure 19In step S2-14, a molding compound 520 is formed on the surface of the intermediate layer 400, the molding compound 520 covering the transmitting element 11 and the receiving element 12.

[0196] See Figure 19 In step S2-15, a second TSV post 510 is formed from the surface of the intermediary layer 400 away from the molding layer 520 inward, penetrating the intermediary layer 400. One end of the second TSV post 510 is electrically connected to the second wiring layer 130 and the third wiring layer 230, respectively, and the other end of the second TSV post 510 is exposed on the side of the intermediary layer 400 away from the molding layer 520.

[0197] See Figure 19 In step S2-16, a packaging substrate 500 is provided, the side of the interposer 400 facing away from the molding layer 520 is bonded to the packaging substrate 500, and the second TSV post 510 is electrically connected to the packaging substrate 500.

[0198] See Figure 19 In step S2-17, a metal bump 540 is formed on the side of the packaging substrate 500 away from the interposer layer 400, and the metal bump 540 is electrically connected to the packaging substrate 500.

[0199] As an example, the receiving circuit integrates a deserializer circuit.

[0200] As an example, see Figures 20-22 When the serializer and deserializer circuits are not integrated in the driving circuit and / or the receiving circuit, the method further includes: providing at least one of the SerDes chips 13, and bonding the SerDes chip 13 to the interposer layer 400, which is arranged side by side with the transmitting element 11 and the receiving element 12, and the SerDes chip 13 is electrically connected to the interposer layer 400.

[0201] The structure of steps S2-12 to S2-17 is an optional step in Example 2, and the materials and processes are the same as in Example 1. For details, please refer to Example 1, which will not be described in detail here.

[0202] As can be seen from the above, the core difference between Embodiment 2 and Embodiment 1 lies in the process sequence of Micro-LED array integration and the formation of the light-transmitting protective layer. Embodiment 1 completes the Micro-LED array integration and the formation of the light-transmitting protective layer before the back-side thinning and TSV processes, while Embodiment 2 postpones these two steps to after the back-side processes. Specifically: First, a first wiring layer is formed on the front side of the first wafer, and a first temporary substrate is bonded to the surface of the first wiring layer. Then, back-side thinning, the first TSV via, and the fabrication of the second wiring layer on the back side are performed. Subsequently, a second temporary substrate is bonded to the surface of the second wiring layer, and the first temporary substrate is removed. Next, the Micro-LED array is integrated on the exposed surface of the first wiring layer on the front side of the first wafer 100, and a light-transmitting protective layer is formed on the surface of the Micro-LED array. Finally, the second temporary substrate is removed.

[0203] This approach moves the high-temperature processes, such as first TSV hole etching, insulating layer deposition, metal deposition, and metal annealing, to the front end, completing them before the Micro-LED array integration. This eliminates the need for the III-V group luminescent material in the Micro-LED array to undergo any harsh process conditions, fundamentally avoiding the risk of photoelectric performance degradation and improving device reliability and yield. Although this embodiment differs from Embodiment 1 in the timing of the formation of the Micro-LED array and protective layer, both revolve around the same core objective: ensuring effective mechanical protection of the structure throughout the back-side interconnect process, ultimately achieving the same emitting component product structure: a Micro-LED array integrated on the front side and covered with a light-transmitting protective layer, and a first TSV pillar and a second wiring layer fabricated on the back side, with electrical connection achieved through the first TSV pillar.

[0204] Example 3

[0205] See Figure 23 In this embodiment, the preparation method of Embodiment 1 or Embodiment 2 is extended. In this embodiment, the first wafer 100 is further provided with a receiving circuit 133, and the electrical signals of the driving circuit 132 and the receiving circuit 133 are independent of each other; the first wiring layer 110 includes a driving wiring area 112 and a receiving wiring area 113 that are electrically isolated from each other.

[0206] Furthermore, the method for fabricating the emitting component includes the following steps before forming the Micro-LED array 120:

[0207] A PD layer (photodetector layer) 800 is formed above the first wiring layer 110, and the PD layer 800 is patterned to form a photosensitive area and a non-photosensitive area; the photosensitive area is electrically connected to the receiving wiring area 113.

[0208] A conductive via is formed in the non-photosensitive area, penetrating the PD layer 800, and a conductive material is filled in the conductive via to form a fourth TSV pillar 810;

[0209] The Micro-LED array 120 is fabricated on the patterned PD layer 800, and the Micro-LED array 120 is electrically connected to the driving wiring area 112 through the fourth TSV pillar 810.

[0210] In this embodiment, a second wiring layer 130 is formed on the back side of the first wafer 100 for bonding a packaging substrate 400; wherein the second wiring layer 130 includes a first bonding wiring region 132 connected to the driving wiring region 112 via a first TSV pillar 140, and a second bonding wiring region 133 electrically connected to the receiving wiring region 113 via a TSV pillar in the receiving element. The two parts are electrically isolated, respectively bonded to the driving substrate 400, and grounded through a portion of the wiring on the driving substrate.

[0211] In one implementation, a photodetector is formed in the PD layer 800. This photodetector can be formed on the front side of the PD layer 800 (the side closest to the first wiring layer 110) and receive light from the back side of the PD layer 800. That is, the light-emitting side of the Micro-LED array 120 is the same as the light-receiving side of the photodetector in the PD layer, and the photodetector receives light from the back side, which is beneficial for improving light emission and reception efficiency. Alternatively, the conductive via and the fourth TSV pillar 810 can be formed during the back-side fabrication of the photodetector after at least some of the photodetector fabrication processes in the PD layer 800 have been completed, such as after PIN element ion implantation. This simplifies the process steps.

[0212] In one example, a first microstructure corresponding to the emitting element and a second microstructure corresponding to the photodetector are simultaneously formed based on the light-transmitting protective layer 122. The first microstructure is used for emitting light shaping, and the second microstructure is used for receiving light focusing. The first microstructure and the second microstructure can be lens assemblies to achieve the above-mentioned functions in this example.

[0213] As an example, the cross-sectional profiles of the first and second microstructures are trapezoidal; wherein the apex of the trapezoid is chamfered or rounded. In a specific embodiment, the first microstructure presents a regular trapezoidal structure, which can effectively change the focusing of the emitted light from the Micro-LED array 120 at the interface, effectively reduce the emission angle of the beam, and match the emission angle of the light with the subsequent optical waveguide, thereby significantly improving the coupling effect; the second microstructure presents an inverted trapezoidal structure, which can collect the light in the optical waveguide or light beam into the receiving element at the receiving end, realize the mode conversion of the light spot size, and thus significantly improve the coupling efficiency.

[0214] This embodiment inherits the technical effects of Embodiments 1 and 2. By pre-forming the receiving circuit 133 on the front side of the first wafer 100 and directly corresponding it in the vertical direction to the subsequently deposited PD layer 800, the photosensitive area and the receiving circuit 133 can be connected through a shorter vertical conductive path. This avoids the complex process and additional mechanical stress caused by interconnecting the independent photodetector chip and the receiving chip through wire bonding or flip-chip bonding in the traditional solution. Combined with the vertical interconnection design of the first wiring layer 110, the PD layer 800 and the Micro-LED array 120, the risk of warping and deformation caused by multiple wafer transfers, alignments and external bonding processes is reduced. This reduces the probability of device damage and electrical connection failure caused by thermal expansion mismatch and mechanical stress, and comprehensively improves process yield and device reliability.

[0215] Example 4

[0216] See Figure 17 This embodiment provides an optical communication transmitting component, which can be fabricated using the preparation method described in Embodiment 1 or Embodiment 2, or a similar method. The optical communication transmitting component includes a transmitting element 11, which comprises:

[0217] A first wafer 100 includes a driving circuitry located near the front side of the first wafer 100.

[0218] As an example, the first wafer 100 serves as a substrate, with its front side planarized. The internal driving circuitry is fabricated using a CMOS process to provide the pixel-level driving signals required by the Micro-LED array 120.

[0219] The first wiring layer 110 is located on the front side of the first wafer 100 and is electrically connected to the driving circuit.

[0220] As an example, the first wiring layer 110 is formed by a metal interconnect process and includes multiple dielectric layers and metal traces, leading the output of the driving circuit to the bonding position of the Micro-LED array 120.

[0221] Micro-LED array 120 is integrated on the surface of the first wiring layer 110 and is electrically connected to the first wiring layer 110.

[0222] As an example, the Micro-LED array 120 is electrically connected to the pads of the first wiring layer 110 one-to-one through flip-chip bonding or hybrid bonding, thereby realizing independent control of the light-emitting pixels.

[0223] A light-transmitting protective layer 122 covers the surface of the Micro-LED array 120 and fills the gaps between the Micro-LED arrays 120, and the surface of the light-transmitting protective layer 122 is higher than the surface of the Micro-LED array 120.

[0224] As an example, the material of the light-transmitting protective layer 122 includes at least one of silicon oxide, silicon nitride, spin-coated glass, or transparent organic resin.

[0225] The light-transmitting protective layer 122 is planarized by CMP to form a flat surface, and also serves as a support interface for subsequent temporary bonding. The light-transmitting protective layer 122 is permanently retained as a light-emitting window, eliminating the risk of contamination from residual temporary bonding material.

[0226] The first TSV pillar 140 extends from the back side of the first wafer 100 through the first wafer 100 to the first wiring layer 110 and is electrically connected to the first wiring layer 110.

[0227] Specifically, the first TSV pillar 140 vertically penetrates the thinned first wafer 100, with its top end contacting the bottom pad of the first wiring layer 110 and its bottom end connecting to the subsequent second wiring layer 130, thereby achieving low-resistance transmission of front-side signals to the back-side.

[0228] The second wiring layer 130 is located on the back side of the first wafer 100 and is electrically connected to the first wiring layer 110 through the first TSV pillar 140.

[0229] Specifically, the second wiring layer 130 is located on the back side of the first wafer 100, and is composed of multiple redistribution layers and dielectric layers. It receives drive signals through the first TSV pillar 140 and provides high-density fan-out pads for external interconnection.

[0230] Thus, the electrical signal of the driving circuit is transmitted from the front side of the first wafer 100 through the first TSV pillar 140 to the second wiring layer 130 on the back side, realizing high-density interconnection on the back side without the need for front-side leads.

[0231] As an example, see Figure 18 The semiconductor structure further includes an interposer 400, to which the second wiring layer 130 is bonded and electrically connected.

[0232] Specifically, the interposer layer 400 serves as a multi-chip integration platform. Its front side has bonding pads and internal interconnects that match the second wiring layer 130, while its back side can be provided with second TSV pillars 510 and solder balls for connecting to the next-level substrate. In one embodiment, the second wiring layer 130 and the interposer layer 400 form a stable electrical connection and mechanical fixation through flip-chip bonding (thermo-press, reflow, or hybrid bonding), thereby achieving the packaging and system integration of the transmitter element 11. This solution guides signals to the back side through the first TSV pillars 140 and the second wiring layer 130, and directly bonds them to the interposer layer 400, providing permanent mechanical support to the thinner wafer and avoiding the risk of breakage in a free state.

[0233] As an example, see Figure 19 The semiconductor structure further includes a receiving element 12, which has a third wiring layer 230 on its surface and is bonded to the interposer layer 400 in parallel with the transmitting element 11 through the third wiring layer 230.

[0234] In this embodiment, the receiving element 12 is a light receiving chip used to convert the received optical signal into an electrical signal. The transmitting element 11 and the receiving element 12 are disposed side by side on the same interposer layer 400, and their upper surfaces are substantially coplanar to optimize optical path alignment and integration density. In another embodiment not shown, the receiving element 12 may employ a stacked wafer structure, for example, comprising two wafers interconnected by hybrid bonding, and a microlens array may be fabricated on the back side of one of the wafers. However, this is merely an alternative and not a limitation of the present invention.

[0235] A molding compound 520 is located on the surface of the interposer 400, and the molding compound 520 covers the transmitting element 11 and the receiving element 12; see also Figures 20-22 In some embodiments, the semiconductor structure further includes a SerDes chip 13 for providing serialization and / or deserialization functions for the semiconductor structure.

[0236] The packaging substrate 500 is disposed on the side of the interposer 400 opposite to the first wafer 100, providing mechanical support and external electrical interface for the entire semiconductor structure. The packaging substrate 500 is typically an organic substrate or a ceramic substrate, and its surface is provided with bonding pads corresponding to the second TSV pillar 510.

[0237] The second TSV pillar 510 penetrates the interposer layer 400. One end of the second TSV pillar 510 is electrically connected to the second wiring layer 130 and the third wiring layer 230, respectively, and the other end of the second TSV pillar 510 is electrically connected to the packaging substrate 500, so as to realize the vertical fan-out of chip signals to the board-level system.

[0238] Metal bump 540, the metal bump 540 is located on the side of the packaging substrate 500 away from the interposer layer 400, and is electrically connected to the packaging substrate 500.

[0239] Unless otherwise specified, the materials, structures and preparation methods of each component in this embodiment are the same as those in Embodiment 1, and will not be described again here.

[0240] In another specific embodiment, see [reference] Figure 23 The transmitting component further includes:

[0241] A receiving circuit 133 is disposed in the first wafer 100, and the electrical signals of the driving circuit 132 and the receiving circuit 133 are independent of each other;

[0242] A PD layer 800 is disposed between the Micro-LED array 120 and the first wiring layer 110;

[0243] The PD layer 800 includes a non-photosensitive area and a photosensitive area. Along a first direction perpendicular to the surface of the first wafer 100, the non-photosensitive area overlaps with the projection of the Micro-LED array 120, and the photosensitive area overlaps with the projection of the receiving circuit 133. The first wiring layer 110 includes a driving wiring area 112 and a receiving wiring area 113 that are electrically isolated from each other. The Micro-LED array 120 is electrically connected to the driving wiring area 112 through a fourth TSV pillar 810 penetrating the non-photosensitive area, and the photosensitive area is electrically connected to the receiving wiring area 113. Specific processes in this embodiment can be found in Embodiment 3, and will not be detailed here.

[0244] In summary, this invention provides an optical communication transmitting component and its fabrication method, aiming to solve technical problems such as reduced back-side process quality due to uneven support, easy warping and breakage after wafer thinning, and the impact of residual temporary bonding material on light extraction efficiency during the back-side interconnection process after heterogeneous integration of the Micro-LED array and driving circuit on the first wafer. This invention, based on the same core inventive concept, provides two fabrication paths: temporary substrates are set on both sides of the first wafer for alternating bonding and removal, combined with the fabrication of the back-side TSV and the second wiring layer, ensuring that the wafer receives mechanical support throughout the thinning and back-side processes, preventing warping or breakage.

[0245] The first fabrication path involves first integrating the Micro-LED array and then performing back-side interconnection: A Micro-LED array is integrated on the front side of a first wafer, forming a transparent protective layer that covers the light-emitting units and fills the gaps; a first temporary substrate is bonded to the surface of the protective layer, followed by back-side thinning, TSV (Transparent Transparent Valves), and the fabrication of the second wiring layer; subsequently, a second temporary substrate is bonded and removed sequentially. In this path, the transparent protective layer acts as a bonding interface, ensuring uniform distribution of support pressure and preventing stress concentration; this protective layer is permanently retained, also functioning as a light-emitting window, avoiding contamination from temporary bonding adhesive residue, and improving light extraction efficiency through refractive index matching. The second fabrication path involves first performing back-side interconnection and then integrating the Micro-LED array: A first temporary substrate is bonded to the front side of a first wafer, followed by back-side thinning, TSV (Transparent Transparent Valves), and the fabrication of the second wiring layer; a second temporary substrate is bonded and the first temporary substrate is removed; a Micro-LED array is integrated on the front side of the first wafer, forming a transparent protective layer; finally, the second temporary substrate is removed. This path places the high-temperature TSV and the second wiring layer entirely in front, protecting the Micro-LED array material from the effects of high-temperature processes and preventing degradation of photoelectric performance. Both approaches ultimately yield the same emitting component structure: a Micro-LED array is integrated on the front side and covered with a light-transmitting protective layer, while a TSV and a second wiring layer are fabricated on the back side, with the two electrically connected via the TSV. The resulting emitting element is bonded to an interposer layer via the second wiring layer on the back side, achieving side-by-side integration and three-dimensional system-in-package with the receiving element. This invention is based on standard wafer-level processes and is compatible with existing CMOS production lines and advanced packaging equipment. Therefore, this invention effectively overcomes various shortcomings of existing technologies and has high industrial applicability.

[0246] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating an optical communication transmitting component, characterized in that, include: A first wafer is provided, the first wafer including driving circuitry near the front side of the first wafer; A first wiring layer is formed on the front side of the first wafer, and the first wiring layer is electrically connected to the driving circuit. A structure to be cut is formed based on a first temporary substrate, a second temporary substrate, and a light-transmitting protective layer; wherein: The structure to be cut includes a first TSV pillar formed from the back side of the first wafer and electrically connected to the first wiring layer; an array of light-emitting elements on the surface of the first wiring layer; and a second wiring layer on the back side of the first wafer that is electrically connected to the first wiring layer through the first TSV pillar. The light-transmitting protective layer is formed on the surface of the light-emitting element array. The first temporary substrate is bonded to the side of the first wiring layer away from the second wiring layer. The second temporary substrate is bonded to the surface of the second wiring layer. The first temporary substrate is removed based on the second temporary substrate to form the structure to be cut, which includes the light-transmitting protective layer. The structure to be cut is cut to form multiple emitting elements, each emitting element integrating the light-emitting element array and the driving circuit.

2. The method for preparing the optical communication transmitting component according to claim 1, characterized in that, The steps following providing the first wafer and forming the first wiring layer specifically include: The light-emitting element array is formed above the first wiring layer, and the light-emitting element array is electrically connected to the first wiring layer; A light-transmitting protective layer is formed on the surface of the light-emitting element array, the light-transmitting protective layer covers the light-emitting element array and fills its gaps, and the surface of the light-transmitting protective layer is higher than the surface of the light-emitting element array; Provide the first temporary substrate and bond the first temporary substrate to the surface of the light-transmitting protective layer; Thin the back side of the first wafer; form a first TSV via downward from the back side of the first wafer, and fill it to form the first TSV pillar, the first TSV pillar being electrically connected to the first wiring layer; A second wiring layer is formed on the back side of the first wafer, and the second wiring layer is electrically connected to the first wiring layer through the first TSV pillar; Provide the second temporary substrate and bond the second temporary substrate to the surface of the second wiring layer; Remove the first temporary substrate to expose the light-transmitting protective layer; Remove the second temporary substrate to expose the second wiring layer, thereby forming the structure to be cut; The structure to be cut is cut to form multiple emitting elements, each emitting element integrating the Micro-LED array and the driving circuit.

3. The method for preparing the optical communication transmitting component according to claim 1, characterized in that, The steps following providing the first wafer and forming the first wiring layer specifically include: Provide the first temporary substrate and bond the first temporary substrate to the surface of the first wiring layer; Thin the back side of the first wafer; form a first TSV via downward from the back side of the first wafer, and fill it to form the first TSV pillar, the first TSV pillar being electrically connected to the first wiring layer; A second wiring layer is formed on the back side of the first wafer, and the second wiring layer is electrically connected to the first wiring layer through the first TSV pillar; Provide the second temporary substrate and bond the second temporary substrate to the surface of the second wiring layer; Remove the first temporary substrate to expose the first wiring layer; The light-emitting element array is formed above the first wiring layer, and the light-emitting element array is electrically connected to the first wiring layer; A light-transmitting protective layer is formed on the surface of the light-emitting element array, the light-transmitting protective layer covers the light-emitting element array and fills its gaps, and the surface of the light-transmitting protective layer is higher than the surface of the light-emitting element array; Remove the second temporary substrate to expose the second wiring layer, thereby forming the structure to be cut; The structure to be cut is cut to form multiple emitting elements, each emitting element integrating the light-emitting element array and the driving circuit.

4. The method for preparing the optical communication transmitting component according to claim 3, characterized in that: The light-emitting element array is a Micro-LED array, and a microstructure is formed based on the light-transmitting protective layer. The microstructure acts as an optical coupler to couple the light emitted by the Micro-LED array to the optical communication receiving element.

5. The method for preparing the optical communication transmitting component according to claim 2 or 3, characterized in that: The material of the light-transmitting protective layer includes at least one of silicon oxide, silicon nitride, spin-coated glass, or transparent organic resin; and / or, the light-emitting element array is a Micro-LED array, which is electrically connected to the first wiring layer by flip-chip bonding, metal-to-metal bonding, or hybrid bonding.

6. The method for preparing an optical communication transmitting component according to claim 2 or 3, characterized in that, Also includes: The first wafer also contains a receiving circuit, and the electrical signals of the driving circuit and the receiving circuit are independent of each other; the first wiring layer includes a driving wiring area and a receiving wiring area that are electrically isolated from each other; A photodiode (PD) layer is formed above the first wiring layer, and the PD layer is patterned to form a photosensitive area and a non-photosensitive area; the photosensitive area is electrically connected to the receiving wiring area. A conductive via is formed in the non-photosensitive area, penetrating the PD layer, and a conductive material is filled into the conductive via to form a fourth TSV pillar; The light-emitting element array is fabricated above the patterned PD layer, and the light-emitting element array is electrically connected to the driving wiring area through the fourth TSV pillar.

7. The method for preparing an optical communication transmitting component according to claim 1, characterized in that, Also includes: An intermediary layer is provided, the transmitting element is bonded to the intermediary layer through the second wiring layer, and the second wiring layer is electrically connected to the intermediary layer; A receiving element is provided, the receiving element having a receiving circuit and a third wiring layer located on the surface of the receiving element, and is bonded in parallel to the transmitting element to the intermediate layer through the third wiring layer, the third wiring layer being electrically connected to the intermediate layer; A molding layer is formed on the surface of the intermediate layer, and the molding layer covers the transmitting element and the receiving element; A second TSV post is formed from the surface of the interposer away from the molding layer inward, penetrating the interposer. One end of the second TSV post is electrically connected to the second wiring layer and the third wiring layer, respectively. The other end of the second TSV post is exposed on the side of the interposer away from the molding layer. A packaging substrate is provided, wherein the side of the interposer opposite to the molding layer is bonded to the packaging substrate, and the second TSV pillar is electrically connected to the packaging substrate; A metal bump is formed on the side of the packaging substrate away from the interlayer, and the metal bump is electrically connected to the packaging substrate.

8. The method for preparing the optical communication transmitting component according to claim 7, characterized in that: The driving circuit integrates a serializer circuit; the receiving circuit integrates a deserializer circuit.

9. The method for preparing an optical communication transmitting component according to claim 7, characterized in that, Also includes: At least one SerDes chip is provided and bonded to the interposer layer, arranged side by side with the transmitting element and the receiving element, and the SerDes chip is electrically connected to the interposer layer; the SerDes chip is electrically connected to the transmitting element and the receiving element respectively through interconnect traces inside the interposer layer.

10. An optical communication transmitting component, characterized in that, The transmitting assembly includes a transmitting element, the transmitting element comprising: A first wafer, the first wafer including a driving circuit near the front side of the first wafer; The first wiring layer is located on the front side of the first wafer and is electrically connected to the driving circuit. An array of light-emitting elements is integrated above the first wiring layer and is electrically connected to the first wiring layer; A light-transmitting protective layer covers the surface of the light-emitting element array and fills the gaps between the light-emitting element arrays, and the surface of the light-transmitting protective layer is higher than the surface of the light-emitting element array; The first TSV pillar extends from the back side of the first wafer through the first wafer to the first wiring layer and is electrically connected to the first wiring layer. The second wiring layer is located on the back side of the first wafer and is electrically connected to the first wiring layer through the first TSV pillar.

11. The optical communication transmitting component according to claim 10, characterized in that: The light-emitting element array is a Micro-LED array, and the light-transmitting protective layer has a microstructure. The microstructure acts as an optical coupler to couple the light emitted by the Micro-LED array to the optical communication receiver.

12. The optical communication transmitting component according to claim 11, characterized in that: The microstructure has a trapezoidal cross-sectional profile corresponding to the Micro-LED array; the apex of the trapezoid is chamfered or rounded.

13. The optical communication transmitting component according to claim 10, characterized in that, Also includes: An interposer layer, wherein the second wiring layer is bonded to and electrically connected to the interposer layer; A receiving element having a receiving circuit and a third wiring layer located on the surface of the receiving element, and being bonded in parallel to the transmitting component to the intermediate layer via the third wiring layer, the third wiring layer being electrically connected to the intermediate layer; A molding compound is located on the surface of the intermediate layer, and the molding compound covers the transmitting element and the receiving element; A packaging substrate is disposed on the side of the interposer layer opposite to the first wafer; The second TSV pillar penetrates the interposer layer. One end of the second TSV pillar is electrically connected to the second wiring layer and the third wiring layer, respectively, and the other end of the second TSV pillar is electrically connected to the packaging substrate. Metal bumps are located on the side of the packaging substrate away from the interposer layer and are electrically connected to the packaging substrate.

14. The optical communication transmitting component according to claim 10, characterized in that: The driving circuit integrates a serializer circuit; the receiving circuit integrates a deserializer circuit.

15. The optical communication transmitting component according to claim 10, characterized in that, Also includes: At least one SerDes chip is bonded to the interposer layer and arranged side by side with the transmitting element and the receiving element, and the SerDes chip is electrically connected to the interposer layer; the SerDes chip is electrically connected to the transmitting element and the receiving element respectively through interconnect traces inside the interposer layer.

16. The optical communication transmitting component according to claim 10, characterized in that: Also includes: A receiving circuit is disposed in the first wafer, and the electrical signals of the driving circuit and the receiving circuit are independent of each other; A PD layer is disposed between the light-emitting element array and the first wiring layer; The PD layer includes a non-photosensitive area and a photosensitive area. Along a first direction perpendicular to the surface of the first wafer, the non-photosensitive area overlaps with the projection of the light-emitting element array, and the photosensitive area overlaps with the projection of the receiving circuit. The first wiring layer includes a driving wiring area and a receiving wiring area that are electrically isolated from each other. The light-emitting element array is electrically connected to the driving wiring area through a fourth TSV pillar passing through the non-photosensitive area, and the photosensitive area is electrically connected to the receiving wiring area.

17. The optical communication transmitting component according to claim 16, characterized in that: The light-transmitting protective layer includes at least one of a silicon oxide layer, a silicon nitride layer, a spin-coated glass layer, or a transparent organic resin layer; and / or, the light-emitting element array is a Micro-LED array, the light-transmitting protective layer covers the PD layer, and has a first microstructure corresponding to the Micro-LED array and a second microstructure corresponding to the photodetector of the photosensitive area.

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