Packaging structure of light quantum chip

Abstract

The utility model discloses a packaging structure of a light quantum chip. The packaging structure of the light quantum chip comprises a first heat dissipation substrate; the semiconductor cooler is located on the first heat dissipation substrate; the first heat dissipation substrate is located on the semiconductor cooler, the second heat dissipation substrate is located on the semiconductor cooler, the PCB is located on the first heat dissipation substrate, and the second heat dissipation substrate is electrically connected with the PCB; the light quantum chip is located on the semiconductor cooler, the at least two optical fiber arrays are located on the semiconductor cooler and the first heat dissipation substrate, and the light quantum chip is located between the two optical fiber arrays and is in optical coupling connection with the two optical fiber arrays; the PCB comprises an FPC (Flexible Printed Circuit) connector; the FPC connector is welded on the reverse side of the PCB, the FPC connector is in line connection with the front side of the PCB, and the FPC connector is used for providing a driving electric signal for the light quantum chip. According to the utility model, the temperature of the light quantum chip can be conducted out to ensure the stability of the chip; the operation frequency of the technological process is reduced, and the product packaging reliability is improved.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor chip technology, and in particular to a packaging structure of a photon chip. Background Art

[0002] Chip packaging is the process of combining an integrated circuit die with packaging materials to connect the die to an external circuit. Packaging not only protects the integrated circuit, but also improves thermal performance, optimizes electromagnetic compatibility, and facilitates production and installation. Photonic quantum chip packaging mainly includes two aspects: electrical packaging and optical packaging.

[0003] Electrical packaging: The normal operation of the photon chip requires a stable working environment to avoid external interference. At the same time, the heat generated by the photon chip during operation affects the signal transmission and chip performance, which causes the chip performance to deteriorate or even fail to work. Normally, the exposed photon chip needs to be packaged before use, and the interference of the environment and its own heat is reduced by using a packaging shell with high thermal conductivity and a semiconductor refrigerator (Thermo Electric Cooler, TEC). In the prior art, the photon chip is generally protected by setting a packaging shell, and the photon chip is pasted to the bottom of the packaging shell, and then the transmission of electrical signals is achieved by connecting the photon chip to the circuit board through wire bonding.

[0004] Optical packaging: The optical packaging of the photonic quantum chip comes after the electrical packaging. The photonic quantum chip converts the received electrical signal into an optical signal and then transmits the optical signal to the outside through the optical fiber array. The coupling process of the photonic quantum chip and the optical fiber array is the key link in realizing the transmission of optical signals. A good photonic quantum chip and optical fiber array coupling packaging process can not only improve the transmission efficiency and reliability of the optical signal, but also reduce the packaging size and reduce the cost.

[0005] The packaging of photonic quantum chips is quite complex, involving mechanical protection, temperature control, electrical connection, optical coupling, electromagnetic shielding and other technologies. They are packaged in the form of traditional tube shells, but the design and processing cycle of tube shells is long, often one month or more, and the processing cost of tube shells is high. At the same time, once the design and processing are completed, they can only be applied to the packaging of specific integrated chips. They are highly targeted and have a single task. They can only be used in scenarios with strict reliability requirements. For application scenarios with low reliability requirements, short task cycles, and applicable to packaging and testing of different chips, traditional tube shells are obviously not the best choice.

[0006] Photonic quantum chips are highly temperature sensitive, and active optical devices such as on-chip integrated lasers and detectors require external electrodes for modulation. During the test process, poor temperature control will cause problems such as temperature drift, thereby reducing the accuracy of the test and product reliability. At present, the existing photonic quantum chip packaging process includes primary electrical packaging, optical coupling testing, secondary electrical packaging, coupling verification and other processes. There are many process flows, which increases the workload of product packaging. At the same time, during the product packaging process, too many process flows also bring problems such as increased packaging costs and reduced reliability. Utility Model Content

[0007] The utility model provides a packaging structure for a photon chip, which can timely conduct the temperature of the photon chip to ensure the temperature stability of the photon chip; reduces the number of process operation times and improves the product packaging reliability.

[0008] According to one aspect of the present invention, a packaging structure of a photon chip is provided, and the packaging structure of the photon chip includes:

[0009] a first heat dissipation substrate;

[0010] A semiconductor refrigerator located on the first heat dissipation substrate;

[0011] At least one second heat dissipation substrate located on the semiconductor refrigerator, and a PCB board located on the first heat dissipation substrate, wherein the second heat dissipation substrate is electrically connected to the PCB board;

[0012] A photon chip located on the semiconductor refrigerator, and at least two optical fiber arrays located on the semiconductor refrigerator and the first heat dissipation substrate, wherein the photon chip is located between the two optical fiber arrays and is optically coupled to the two optical fiber arrays;

[0013] The PCB board includes an FPC connector;

[0014] The FPC connector is welded on the reverse side of the PCB board, the FPC connector is connected to the front line of the PCB board, and the FPC connector is used to provide a driving electrical signal for the photonic quantum chip.

[0015] Optionally, the second heat dissipation substrate and the PCB board are located on the same horizontal plane.

[0016] Optionally, the PCB board further includes a pin header;

[0017] The needle row is connected to the square electrode in the photonic quantum chip, the square electrode is connected to the lead of the semiconductor refrigerator, and the needle row is used to provide a driving electrical signal for the semiconductor refrigerator.

[0018] Optionally, the PCB board further includes at least four screw fixing holes and a plurality of conductive vias, and the FPC connector is connected to the front circuit of the PCB board through the conductive vias.

[0019] Optionally, the shape of the second heat dissipation substrate includes at least one of: I-shaped, rectangular, and U-shaped.

[0020] Optionally, the packaging structure of the optical quantum chip further includes a plurality of heat dissipation fins, and the heat dissipation fins are located at the bottom of the first heat dissipation substrate.

[0021] Optionally, the packaging structure of the optical quantum chip further includes an acrylic shell and at least two bolts. The acrylic shell is located above the optical fiber array and there is a gap between the acrylic shell and the optical fiber array. The bolts are used to connect the acrylic shell and the first heat dissipation substrate.

[0022] Optionally, the optical quantum chip is a silicon-based optical quantum chip.

[0023] Optionally, the first heat dissipation substrate is a heat sink.

[0024] Optionally, the second heat dissipation substrate is an aluminum nitride ceramic substrate.

[0025] The technical solution of the embodiment of the present utility model, compared with the traditional packaging structure of the optical quantum chip, this structure integrates 2-way optical fiber arrays, integrates electrical packaging and optical packaging together, realizes the integration and miniaturization of the packaging structure; at the same time, the packaging structure becomes an open structure, which can adapt to the packaging test of chips of different sizes, can achieve rapid response, and reduces the packaging cost. By improving the structure, the FPC connector is adjusted from the front of the PCB board to the back, which is beneficial to the coupling operation of the optical fiber array, and at the same time reduces the packaging process and improves the reliability of product packaging. By integrating a semiconductor refrigerator, the temperature of the optical quantum chip can be monitored and controlled in real time during the test process. By using a second heat dissipation substrate with a higher thermal conductivity coefficient, the temperature can be conducted out in time to ensure the temperature stability of the optical quantum chip and improve the accuracy of the test and the reliability of the product. By optimizing the structure to reduce the packaging process flow,开槽 on the back of the heat sink, welding the FPC connector on the back of the PCB board, through such an optimized structural design, on the one hand, the two electrical packaging processes can be combined into one electrical packaging process, reducing the number of process operations and improving the reliability of product packaging. On the other hand, it provides convenience for the coupling operation of the optical fiber array and improves the optical coupling operation efficiency. In summary, the present utility model solves the problems of poor temperature control and temperature drift in the existing test process, which reduces the accuracy of the test and the reliability of the product; it also solves the problems of increased cost and reduced reliability in the existing product packaging process due to excessive process flows.

[0026] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present utility model, nor are they intended to limit the scope of the present utility model. Other features of the present utility model will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 This is a front schematic diagram of a packaging structure of a photon chip provided according to an embodiment of the utility model;

[0029] Figure 2 It is a schematic diagram of the reverse side of a packaging structure of a photon quantum chip provided according to an embodiment of the utility model;

[0030] Figure 3 It is a cross-sectional view of a packaging structure of a photon chip provided according to an embodiment of the utility model;

[0031] Figure 4 This is a workflow diagram of a photon chip provided according to an embodiment of the utility model;

[0032] Figure 5 It is a structural schematic diagram of a second heat dissipation substrate provided according to an embodiment of the utility model;

[0033] Figure 6 It is a front schematic diagram of a PCB board provided according to an embodiment of the utility model;

[0034] Figure 7 This is a schematic diagram of the back side of a PCB board provided according to an embodiment of the utility model;

[0035] Figure 8 It is a packaging flow chart of a packaging structure of a photonic quantum chip provided according to an embodiment of the utility model. DETAILED DESCRIPTION

[0036] In order to enable those skilled in the art to better understand the solution of the utility model, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the utility model.

[0037] It should be noted that the terms "first", "second", etc. in the specification and claims of the utility model and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the utility model described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0038] Figure 1 It is a front view schematic diagram of a packaging structure of a photon chip provided according to an embodiment of the utility model. Figure 2 It is a schematic diagram of the reverse side of a packaging structure of a photon chip provided according to an embodiment of the utility model. Figure 3 is a cross-sectional view of a packaging structure of a photon chip provided according to an embodiment of the present utility model, with reference to Figure 1 , Figure 2 and Figure 3 The embodiment of the utility model provides a packaging structure of a photon chip, and the packaging structure of the photon chip includes: a first heat dissipation substrate 10; a semiconductor refrigerator 20 located on the first heat dissipation substrate 10; at least one second heat dissipation substrate 30 located on the semiconductor refrigerator 20, a PCB board 40 located on the first heat dissipation substrate 10, and the second heat dissipation substrate 30 is electrically connected to the PCB board 40; a photon chip 50 located on the semiconductor refrigerator 20, and at least two optical fiber arrays 60 located on the semiconductor refrigerator 20 and the first heat dissipation substrate 10, and the photon chip 50 is located between the two optical fiber arrays 60 and optically coupled with the two optical fiber arrays 60; the PCB board 40 includes an FPC connector 41; the FPC connector 41 is welded on the back side of the PCB board 40, the FPC connector 41 is connected to the front line of the PCB board 40, and the FPC connector 41 is used to provide a driving electrical signal for the photon chip 50.

[0039] Specifically, optionally, the first heat dissipation substrate 10 is a heat sink. The heat sink is the support structure of the entire packaged product, and is made of copper material, which has good thermal conductivity and electrical conductivity. The electrical conductivity and thermal conductivity of copper are second only to silver, and it is widely used to make conductive and thermal conductive equipment. The heat sink mainly provides mechanical support, heat dissipation channels and other functions for the chip in the package structure.

[0040] The semiconductor cooler 20 refers to a device that uses the thermoelectric effect of semiconductors to generate cooling, also known as a thermoelectric cooler. When two different metals are connected by a conductor and a direct current is turned on, the temperature at one junction decreases and the temperature at the other junction increases. The semiconductor cooler in the packaging structure mainly provides a stable temperature environment for the photonic chip 50 to ensure that the photonic chip 50 can work normally. In view of the temperature sensitivity of the photonic chip 50, the semiconductor cooler 20 is added to the packaging structure to achieve precise control of the temperature of the photonic chip 50.

[0041] Optionally, the second heat dissipation substrate 30 is an aluminum nitride ceramic substrate. Aluminum nitride ceramic has excellent electrical and thermal properties and is considered to be the most promising high thermal conductivity ceramic substrate material. Circuit lines are distributed on the surface of the aluminum nitride ceramic substrate, and the circuit lines are etched from pure gold. The aluminum nitride ceramic substrate plays a transfer role in the packaging structure, and interconnects the photon chip 50 and the PCB board 40 through gold wire bonding to achieve electrical connectivity. There are circuits on the second heat dissipation substrate 30, which need to be gold-wire bonded to the PCB pad. When designing, it is best to ensure that the second heat dissipation substrate 30 and the PCB board 40 are on the same horizontal plane.

[0042] The PCB board 40 provides an electrical interface for the chip in the packaging structure. An FPC connector 41 is integrated on the PCB board 40. The FPC connector 41 is welded on the back side of the PCB board 40, and is connected to the front side of the PCB board 40 through a conductive through hole. The FPC connector 41 provides a driving electrical signal for the photonic quantum chip 50.

[0043] The photon chip 50 integrates the luminescence properties of indium phosphide and the optical routing capabilities of silicon into a single chip. The photon chip 50 is made using traditional semiconductor micro-nano processing technology, and a large number of photon devices can be integrated on a single chip. By applying voltage to indium phosphide, a continuous laser beam can be generated, and silicon photonic devices can be driven under the action of the laser beam to realize quantum information processing applications. It has the advantages of high integration, high precision, and high stability. Optionally, the photon chip 50 is a silicon-based photon chip. Silicon-based photon chips based on silicon-based integrated optical technology can be applied to large-scale photon computing and information processing due to their CMOS compatibility, strong nonlinear effects, and ultra-high integration.

[0044] The second heat dissipation substrate 30 serves as an electrical connection bridge between the photonic chip 50 and the PCB board 40 (there is a metal trace on the second heat dissipation substrate 30), the photonic chip 50 is wired to one end of the metal trace on the second heat dissipation substrate 30, and the second heat dissipation substrate 30 (the second end of the metal trace) is wired to the PCB board 40. It is connected to the FPC connector 41 through the conductive through hole inside it, so that the FPC connector 41 can provide a driving electrical signal for the photonic chip 50.

[0045] The second heat dissipation substrate 30 can be a whole piece, and the photon chip 50 is directly attached to the second heat dissipation substrate 30, so that the structure and the manufacturing process are relatively simple. In addition, two second heat dissipation substrates 30 can be arranged on the semiconductor refrigerator 20, and the photon chip 50 is directly located on the semiconductor refrigerator 20 for better effect.

[0046] The fiber array 60 (FA) is an array formed by installing a bundle of optical fibers or an optical fiber ribbon on a substrate at specified intervals using a V-groove substrate. In the packaging structure, the fiber array 60 mainly realizes information exchange between the photonic quantum chip 50 and the outside.

[0047] Figure 4 This is a workflow diagram of a photon chip provided according to an embodiment of the utility model, with reference to Figure 4 The basic structure of a photonic chip includes photonic devices such as optical waveguides, modulators, detectors, lasers, and microelectronic devices such as CMOS transistors. The working principle of a photonic chip is based on the optoelectronic properties of silicon materials and the principles of optical devices. It uses the semiconductor properties of silicon to form a waveguide structure on the chip to guide photons to propagate inside the chip. Optical devices such as optical modulators, lasers, and photodetectors are also integrated on the chip to modulate, transmit, and receive optical signals. Photons and electrons in a photonic chip are converted into each other through the photoelectric effect. After being modulated by an optical modulator, the light intensity, phase, and frequency can be controlled. Through optical transmission media such as optical fibers, light signals can be transmitted over long distances between chips or between the chip and the outside world.

[0048] Combined with semiconductor chip packaging technology, improvements and optimizations are proposed for the existing photonic quantum chip packaging structure, and a packaging structure for a photonic quantum chip with an integrated optical fiber array is provided, which can be used to make quantum computer products. Compared with photonic chip packaging, the price and volume are greatly reduced. Therefore, the use of this solution can ultimately achieve low-cost, high-stability, and high-reliability photonic quantum packaging products, thereby promoting the expansion and development of the application field of quantum chips.

[0049] The technical solution of the embodiment of the present utility model, compared with the traditional optical quantum chip packaging structure, this structure integrates two optical fiber arrays, integrates electrical packaging and optical packaging together, realizes the integration and miniaturization of the packaging structure; at the same time, the packaging structure becomes an open structure, which can adapt to the packaging test of chips of different sizes, can achieve rapid response, and reduces the packaging cost. By improving the structure, the FPC connector is adjusted from the front of the PCB board to the back, which is beneficial to the coupling operation of the optical fiber array, and at the same time reduces the packaging process and improves the reliability of product packaging. By integrating a semiconductor cooler, the temperature of the optical quantum chip can be monitored and controlled in real time during the test process. By using a second heat dissipation substrate with a higher thermal conductivity coefficient, the temperature can be conducted out in time to ensure the temperature stability of the optical quantum chip and improve the accuracy of the test and the reliability of the product. By optimizing the structure to reduce the packaging process flow, a groove is opened on the back of the heat sink, and the FPC connector is welded to the back of the PCB board. Through such a structural optimization design, on the one hand, two electrical packaging processes can be combined into one electrical packaging process, reducing the number of process operations and improving the reliability of product packaging. On the other hand, it provides convenience for the coupling operation of the optical fiber array and improves the optical coupling operation efficiency. In summary, the present utility model solves the problems of temperature drift caused by poor temperature control during the existing test process, thereby reducing the accuracy of the test and the reliability of the product; it also solves the problems of increased cost and reduced reliability caused by excessive process flow during the packaging process of existing products.

[0050] Continue to refer to Figure 3 , optionally, the packaging structure of the optical quantum chip further includes a plurality of heat dissipation fins 70, and the heat dissipation fins 70 are located at the bottom of the first heat dissipation substrate 10.

[0051] Specifically, adding heat dissipation fins 70 on the back of the overall packaging structure is beneficial to conducting the temperature of the packaging structure out in time, thereby improving the heat dissipation efficiency of the packaging structure.

[0052] Continue to refer to Figure 3 , optionally, the packaging structure of the optical quantum chip further includes an acrylic shell 80 and at least two bolts 90. The acrylic shell 80 is located above the optical fiber array 60 and there is a gap between the acrylic shell 80 and the optical fiber array 60. The bolts 90 are used to connect the acrylic shell 80 and the first heat dissipation substrate 10.

[0053] Optionally, the shape of the second heat dissipation substrate includes at least one of:工字 shape, rectangular shape, 冂 shape.

[0054] Figure 5 is a schematic structural diagram of a second heat dissipation substrate provided according to an embodiment of the present utility model. Refer to Figure 5 and Figure 1Optionally, the second heat dissipation substrate 30 and the PCB board 40 are located on the same horizontal plane.

[0055] Specifically, there are circuits on the second heat dissipation substrate 30, which need to be gold-wire bonded to the PCB pads on the PCB board 40. During design, it is best to ensure that the second heat dissipation substrate 30 and the PCB board 40 are on the same horizontal plane.

[0056] Figure 6 is a front view of a PCB board provided according to an embodiment of the utility model, Figure 7 is a schematic diagram of the back side of a PCB board provided according to an embodiment of the utility model, with reference to Figure 6 and Figure 7 Optionally, the PCB board 40 also includes a pin row 42; the pin row 42 is connected to the square electrode in the photonic chip, the square electrode is connected to the lead of the semiconductor refrigerator, and the pin row 42 is used to provide a driving electrical signal for the semiconductor refrigerator.

[0057] Continue to refer Figure 6 and Figure 7 Optionally, the PCB board 40 further includes at least four screw fixing holes 43 and a plurality of conductive through holes 44 , and the FPC connector is connected to the front line of the PCB board 40 through the conductive through holes 44 .

[0058] Specifically, Figure 6 The circular holes at the four corners of the middle PCB board 40 are screw fixing holes 43, and the 1-33 and 1-37 origin arrays are the front faces of the conductive through holes 44; the pin row 42 at the lower right corner connects two square electrodes, and the square electrodes are connected to the leads of the semiconductor refrigerator (by means of lead welding). Figure 7 The origin array in FIG. 4 is the back side of the conductive through hole 44 , the rectangular pad array is the electrode of the FPC connector, and other square electrodes can be ignored.

[0059] Figure 8 This is a packaging flow chart of a packaging structure of a photon chip provided according to an embodiment of the utility model, with reference to Figure 8 , Figure 8 The entire process of packaging the packaging structure of a photonic quantum chip is shown by way of example.

[0060] The above specific implementations do not constitute a limitation on the protection scope of the present utility model. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present utility model shall be included in the protection scope of the present utility model.

Claims

1. A packaging structure for an optical quantum chip, characterized in that, it includes: A first heat dissipation substrate; A semiconductor refrigerator located on the first heat dissipation substrate; At least one second heat dissipation substrate located on the semiconductor refrigerator, a PCB board located on the first heat dissipation substrate, and the second heat dissipation substrate is electrically connected to the PCB board; An optical quantum chip located on the semiconductor refrigerator, at least two optical fiber arrays located on the semiconductor refrigerator and the first heat dissipation substrate, and the optical quantum chip is located between the two optical fiber arrays and is optically coupled to the two optical fiber arrays; The PCB board includes an FPC connector; The FPC connector is soldered on the reverse side of the PCB board, the FPC connector is connected to the front circuit of the PCB board, and the FPC connector is used to provide a driving electrical signal for the optical quantum chip.

2. The packaging structure for an optical quantum chip according to claim 1, characterized in that, The second heat dissipation substrate and the PCB board are on the same horizontal plane.

3. The packaging structure for an optical quantum chip according to claim 1, characterized in that, The PCB board further includes pin headers; The pin headers are connected to the square electrodes in the optical quantum chip, the square electrodes are connected to the leads of the semiconductor refrigerator, and the pin headers are used to provide a driving electrical signal for the semiconductor refrigerator.

4. The packaging structure for an optical quantum chip according to claim 2, characterized in that, The PCB board further includes at least four screw fixing holes and a plurality of conductive vias, and the FPC connector is connected to the front circuit of the PCB board through the conductive vias.

5. The packaging structure for an optical quantum chip according to claim 1, characterized in that, The shape of the second heat dissipation substrate includes at least one of: I-shaped, rectangular, and U-shaped.

6. The packaging structure for an optical quantum chip according to claim 1, characterized in that, It further includes a plurality of heat dissipation fins, and the heat dissipation fins are located at the bottom of the first heat dissipation substrate.

7. The packaging structure for an optical quantum chip according to claim 1, characterized in that, It further includes an acrylic housing and at least two bolts, the acrylic housing is located above the optical fiber array and there is a gap between the acrylic housing and the optical fiber array, and the bolts are used to connect the acrylic housing and the first heat dissipation substrate.

8. The packaging structure for an optical quantum chip according to claim 1, characterized in that, The optical quantum chip is a silicon-based optical quantum chip.

9. The packaging structure for an optical quantum chip according to claim 1, characterized in that, The first heat dissipation substrate is a heat sink.

10. The packaging structure for an optical quantum chip according to claim 1, characterized in that, The second heat dissipation substrate is an aluminum nitride ceramic substrate.

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