High-power parallel power module with symmetrical packaging structure

Abstract

The utility model relates to the technical field of packaging structures, in particular to a high-power parallel power module with a symmetrical packaging structure, which comprises an upper DBC board and a lower DBC board, a source electrode power terminal on the upper DBC board is connected with a source electrode loop copper-clad layer, a grid electrode driving terminal on the upper DBC board is connected with a grid electrode loop copper-clad layer, and a grid electrode power terminal on the lower DBC board is connected with a grid electrode loop copper-clad layer. A drain power terminal on the lower DBC board is connected with a drain loop copper-clad layer, a SiC MOSFET and a diode chip are arranged between the drain loop copper-clad layer and the source loop copper-clad layer, and the SiC MOSFET and the diode chip are connected with the upper DBC board through buffer conducting strips. According to the utility model, electrical connection of all parts in the module is realized by adopting the two DCB boards and the buffer conducting strip, so that the whole packaging structure of the module is simplified, double-sided heat dissipation of the SiC MOSFET and the diode chip is realized through the copper-clad layers arranged on the surfaces of the two DBC boards, the whole temperature of the module and the junction temperature of the chip are effectively reduced, and the service life of the module is effectively prolonged.

Description

Technical Field

[0001] The utility model relates to the technical field of packaging structures, in particular to a high-power parallel power module with a symmetrical packaging structure. Background Art

[0002] In recent years, SiC devices have been widely used in the fields of modular multilevel converters, hybrid high-voltage DC circuit breakers and other renewable energy power generation grid-connected fields due to their excellent characteristics such as high blocking voltage, high switching frequency, high thermal conductivity and low loss. However, due to the limitations of semiconductor processes, costs, thermal and mechanical factors, the current carrying capacity of a single chip is limited. For example, the current carrying capacity of most commercial single SiC MOSFET chips is only tens of amperes. Therefore, in these medium and large power application fields, in order to increase the current level of SiC power modules, multiple devices need to be connected in parallel. However, the traditional multi-module parallel connection method not only introduces large parasitic inductance, but also has a great impact on the switching speed and dynamic balance of the device. Therefore, it is necessary to develop a power module with multi-chip parallel packaging.

[0003] However, there are several challenges in the current multi-chip parallel packaging power module. First, the current imbalance of each branch in the parallel connection of modules, mainly due to the dispersion of loop parasitic parameters, will cause the electrical and thermal stress of each chip in the module to be uneven, which will cause the premature failure of some chips in the module due to excessive stress, seriously reducing the service life of the entire module. Secondly, the traditional packaging module structure uses aluminum bonding as the interconnection method between the chip and the DBC. The aluminum bonding wire will bring great parasitic inductance due to its thinness and length; and the failure mode of bond wire warping and falling off in the bonding package also reduces the reliability of the module for long-term operation. Due to the high-speed switching capability of the SiC module, the SiC power module is easily affected by the parasitic inductance in the module during the switching process and generates a large overvoltage, which reduces the reliability of the module and accelerates the aging of the module. Finally, connecting multiple SiC chips in parallel in a power module puts higher requirements on the heat dissipation capacity of the module. The ordinary single-sided heat dissipation packaging mode will make the overall junction temperature of the module too high, which is very unfavorable to the module. Summary of the invention

[0004] The technical problem to be solved by the utility model is to provide a high-power parallel power module with a symmetrical packaging structure to solve the above-mentioned problem.

[0005] The utility model solves the above technical problem through a technical solution: a high-power parallel power module with a symmetrical packaging structure, comprising an upper DBC board and a lower DBC board, wherein the source power terminal on the upper DBC board is connected to a source loop copper clad layer, the gate drive terminal on the upper DBC board is connected to a gate loop copper clad layer, the drain power terminal on the lower DBC board is connected to a drain loop copper clad layer, a SiC MOSFET and a diode chip are arranged between the drain loop copper clad layer and the source loop copper clad layer, and the SiC MOSFET and the diode chip are respectively connected to the upper DBC board through a buffer conductive sheet.

[0006] As a preferred technical solution of the utility model, the upper DBC board and the lower DBC board are both copper-clad ceramic boards, and the copper-clad ceramic board includes an upper copper layer, and the upper copper layer is connected to the lower copper layer through an insulating layer.

[0007] As a preferred technical solution of the present utility model, the material of the insulating layer is aluminum nitride ceramic or aluminum oxide ceramic.

[0008] As a preferred technical solution of the utility model, the upper DBC plate and the lower DBC plate are both circular structures, and the source power circuit on the lower surface of the upper DBC plate and the drain power circuit on the upper surface of the lower DBC plate are distributed in mirror symmetry.

[0009] As a preferred technical solution of the utility model, the SiC MOSFET and diode chips are provided in several groups and are distributed in a circularly symmetrical manner.

[0010] As a preferred technical solution of the utility model, the buffer conductive sheet comprises a first buffer conductive sheet, a second buffer conductive sheet and a third buffer conductive sheet, one end of the first buffer conductive sheet (3) is connected to the source of the SiC MOSFET, one end of the second buffer conductive sheet is connected to the gate of the SiC MOSFET, and the third buffer conductive sheet is connected to the anode of the diode chip.

[0011] As a preferred technical solution of the present utility model, the first buffer conductive sheet, the second buffer conductive sheet and the third buffer conductive sheet are all made of molybdenum.

[0012] As a preferred technical solution of the utility model, the source power terminal and the drain power terminal are both cylindrical structures, an insulating sheet is installed at the connection between the source power terminal and the upper DBC plate, and an insulating sheet is installed at the connection between the drain power terminal and the lower DBC plate, and the material of the insulating sheet is aluminum nitride ceramic or alumina ceramic.

[0013] As a preferred technical solution of the present utility model, the source power terminal, the drain power terminal and the gate drive terminal are all made of copper.

[0014] Since the utility model adopts such a structure, it has the following beneficial effects:

[0015] 1. By adopting a circular symmetrical structure, multiple groups of SiC MOSFET and diode chips are symmetrically distributed along the circumference with the center of the DBC board as the center, so that the loop area and loop length of the power loop of each group of SiC MOSFET and diode chips are equal, and the parasitic parameters of each parallel branch are basically the same, so that the current distribution of each parallel branch is more even, and the electrical and thermal stress of each group of SiC MOSFET and diode chips is more balanced, thereby improving the overall life of the parallel power module.

[0016] 2. The power circuit in the lower copper layer of the upper DBC board and the power circuit in the upper copper layer of the lower DBC board are distributed in a mirror-symmetrical manner, so that the power circuit in the lower copper layer of the upper DBC board in each parallel branch overlaps with the power circuit in the copper layer of the lower DBC board, and the current directions are opposite. According to the principle of magnetic flux cancellation, the parasitic inductance of the power circuit of the parallel module is effectively reduced. At the same time, the copper cladding design of two DBC boards is used to realize the electrical connection of various parts in the module, and aluminum bonding wires are not used. This not only avoids the failure mode of bonding wire warping and falling off that may occur in the bonding package, but also effectively reduces the parasitic inductance of the circuit, greatly improving the reliability of the parallel module.

[0017] 3. The electrical connection of each part inside the module is realized by using two DCB boards and buffer conductive sheets, which simplifies the overall packaging structure of the module. At the same time, the copper cladding layer set on the surface of the two DBC boards realizes double-sided heat dissipation of SiC MOSFET and diode chips, effectively reducing the overall temperature of the module and the junction temperature of the chip, and effectively extending the life of the module. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is an equivalent circuit topology diagram of a high-power parallel power module with a symmetrical packaging structure of the utility model.

[0019] Figure 2 It is an exploded diagram of a high-power parallel power module with a symmetrical packaging structure of the utility model.

[0020] Figure 3 It is a structural diagram of the upper DBC board.

[0021] Figure 4 It is a cross-sectional view of a high-power parallel power module with a symmetrical packaging structure of the utility model.

[0022] Figure 5 The utility model is a schematic diagram of the power loop current magnetic field distribution of a high-power parallel power module with a symmetrical packaging structure.

[0023] Figure 6 The utility model is a schematic diagram of a parasitic inductance sweep frequency of a power circuit of a high-power parallel power module with a symmetrical packaging structure.

[0024] Figure 7 It is a schematic diagram of temperature distribution of a high-power parallel power module of a symmetrical packaging structure of the utility model.

[0025] In the figure: 1 is the source power terminal, 2 is the insulating sheet, 3 is the first buffer conductive sheet, 4 is the third buffer conductive sheet, 5 is the second buffer conductive sheet, 6 is the drain loop copper clad layer, 7 is the SiC MOSFET, 8 is the diode chip, 9 is the source loop copper clad layer, 10 is the gate loop copper clad layer, 11 is the gate drive terminal, 13 is the upper DBC board, 16 is the lower DBC board, and 17 is the drain power terminal. DETAILED DESCRIPTION

[0026] The utility model is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] like Figure 1-4 As shown, a high-power parallel power module of a symmetrical packaging structure of the utility model includes an upper DBC board 13 and a lower DBC board 16, wherein the source power terminal 1 on the upper DBC board 13 is connected to a source loop copper clad layer 9, the gate drive terminal 11 on the upper DBC board 13 is connected to a gate loop copper clad layer 10, and the drain power terminal 17 on the lower DBC board 16 is connected to a drain loop copper clad layer 6, and SiC MOSFET 7 and a diode chip 8 are provided between the drain loop copper clad layer 6 and the source loop copper clad layer 9, and the SiC MOSFET 7 and the diode chip 8 are respectively connected to the upper DBC board 13 through a buffer conductive sheet. The parallel design of SiC MOSFET 7 can improve the current level of the SiC power module, which is beneficial to reducing the module volume and increasing the module power density. Compared with the method of paralleling modules to increase the current level, the parallel connection between SiC MOSFET 7 greatly reduces the parasitic inductance of the loop.

[0028] The upper DBC board 13 and the lower DBC board 16 are both made of copper-clad ceramic boards. The DBC board includes an upper copper layer and a lower copper layer, and an insulating layer sandwiched between the two copper layers. The middle insulating layer is made of aluminum nitride ceramic or aluminum oxide ceramic.

[0029] The upper DCB board 13 and the lower DBC board 16 are both circular structures, and the source power loop 9 in the lower copper layer of the upper DBC board 13 and the drain power loop 6 in the upper copper layer of the lower DBC board are distributed in a mirror-symmetrical manner, so that in each parallel branch, the source power loop 9 in the lower copper layer of the upper DBC board 13 and the drain power loop 6 in the upper copper layer of the lower DBC board 16 overlap in path, and the current directions are opposite, which helps to reduce the parasitic inductance of the power loop of the parallel module based on the principle of magnetic flux cancellation.

[0030] SiC MOSFET 7 and diode chip 8 are arranged between the upper DCB board 13 and the lower DBC board 16. There are multiple groups of SiC MOSFET 7 and diode chip 9 (6 groups are used as an example in this embodiment), and each group of SiC MOSFET 7 and diode chip 9 is symmetrically distributed along the circumference with the center of the DBC board as the center. By adopting a circular symmetrical structure, it is ensured that the power loop of each group of SiC MOSFET and diode chip has the same area and length, and the parasitic parameters of each parallel branch can be basically consistent, and the current distribution of each parallel branch can be more uniform, which can significantly extend the service life of the entire parallel power module.

[0031] SiC MOSFET 7 and diode chip 8 are connected to one end of the buffer conductive sheet, and the other end of the buffer conductive sheet is connected to the upper DBC board 13. The buffer conductive sheet includes a first buffer conductive sheet 3, a second buffer conductive sheet 5 and a third buffer conductive sheet 4. One end of the first buffer conductive sheet 3 is connected to the source of SiC MOSFET 7, one end of the second buffer conductive sheet 5 is connected to the gate of SiC MOSFET 7, and the third buffer conductive sheet 4 is connected to the anode of diode chip 8. The first conductive sheet 3, the second buffer conductive sheet 5 and the third buffer conductive sheet 4 are all made of molybdenum sheets, which have a good buffering effect. The copper cladding design of two DBC boards is used to realize the electrical connection of various parts in the module. No aluminum bonding wire is used in the entire package, which not only avoids the failure mode of warping and falling of the bonding wire that may occur in the bonding package, but also effectively reduces the parasitic inductance of the loop, greatly improving the reliability of the parallel module. At the same time, the overall packaging structure of the module is simplified, and the double-sided heat dissipation of SiCMOSFET and diode chips is realized by the copper cladding layer set on the surface of the two DBC boards, which helps to reduce the overall temperature of the module and the junction temperature of the chip, thereby extending the life of the module.

[0032] The source power terminal 1 adopts a cylindrical structure and is fixed at the center of the upper DBC board 13. One end of the terminal is connected to the source power loop 9 of the lower copper layer of the upper DBC board, and the other end passes through the middle insulating layer of the upper DBC board 13 and the upper copper layer of the upper DBC board 13. An insulating sheet 2 is provided between the source power terminal 1 and the upper copper layer of the upper DBC board 13 to achieve electrical isolation; the drain power terminal 17 adopts a cylindrical structure and is fixed at the center of the lower DBC board 16. One end of the terminal is connected to the drain power loop 6 of the upper copper layer of the lower DBC board, and the other end passes through the middle insulating layer of the lower DBC board 16 and the lower copper layer of the lower DBC board 16. An insulating sheet 2 is provided between the drain power terminal 17 and the lower copper layer of the lower DBC board 16 to achieve electrical isolation; the gate drive terminal is connected to the lower copper layer of the upper DBC board 13. The source power terminal, the drain power terminal, and the gate drive terminal are made of copper metal, and the insulating sheet is made of aluminum nitride ceramic or aluminum oxide ceramic.

[0033] according to Figure 5 The current magnetic field of each parallel branch of the power circuit of the utility model is evenly distributed, which means that the problem of current sharing in each branch in the parallel module is effectively solved.

[0034] according to Figure 6 The utility model extracts that the parasitic inductance of the power circuit (including the power terminal) is only 6.58nH.

[0035] according to Figure 7 ,The heat source of the six chips is set to 50W, the heat dissipation boundary conditions are located on the upper and lower surfaces of the power module, the heat convection coefficient is set to 100W / (m2·℃), and the maximum temperature is 53.395℃.

[0036] The description and application of the utility model here are illustrative and are not intended to limit the scope of the utility model to the above-described embodiments. Variations and changes of the embodiments disclosed here are possible, and the actual replacement of the embodiments and the various components equivalent to those of ordinary skill in the art are well known. It should be clear to those skilled in the art that the utility model can be implemented in other forms, structures, arrangements, proportions, and with other elements, materials, and components without departing from the spirit or essential features of the utility model. Other variations and changes can be made to the embodiments disclosed here without departing from the spirit or essential features of the utility model.

Claims

1. A high-power parallel power module with a symmetrical packaging structure, characterized by: The invention comprises an upper DBC plate (13) and a lower DBC plate (16), wherein the source power terminal (1) on the upper DBC plate (13) is connected to a source loop copper clad layer (9), the gate drive terminal (11) on the upper DBC plate (13) is connected to a gate loop copper clad layer (10), the drain power terminal (17) on the lower DBC plate (16) is connected to a drain loop copper clad layer (6), a SiC MOSFET (7) and a diode chip (8) are provided between the drain loop copper clad layer (6) and the source loop copper clad layer (9), and the SiC MOSFET (7) and the diode chip (8) are respectively connected to the upper DBC plate (13) via a buffer conductive sheet.

2. The high-power parallel power module with a symmetrical packaging structure according to claim 1, characterized in that: The upper DBC plate (13) and the lower DBC plate (16) are both copper-clad ceramic plates, and the copper-clad ceramic plates include an upper copper layer, and the upper copper layer is connected to the lower copper layer via an insulating layer.

3. The high-power parallel power module with a symmetrical packaging structure according to claim 2, characterized in that: The insulating layer is made of aluminum nitride ceramic or aluminum oxide ceramic.

4. The high-power parallel power module with a symmetrical packaging structure according to claim 1, characterized in that: The upper DBC plate (13) and the lower DBC plate (16) are both circular structures, and the source power loop on the lower surface of the upper DBC plate (13) and the drain power loop on the upper surface of the lower DBC plate (16) are distributed in a mirror-symmetrical manner.

5. The high-power parallel power module with a symmetrical packaging structure according to claim 1, characterized in that: The SiC MOSFET (7) and diode chips (8) are arranged in several groups and are distributed symmetrically around the circumference.

6. The high-power parallel power module with a symmetrical packaging structure according to claim 1, characterized in that: The buffer conductive sheet comprises a first buffer conductive sheet (3), a second buffer conductive sheet (5) and a third buffer conductive sheet (4); one end of the first buffer conductive sheet (3) is connected to the source of the SiC MOSFET (7); one end of the second buffer conductive sheet (5) is connected to the gate of the SiC MOSFET (7); and the third buffer conductive sheet (4) is connected to the anode of the diode chip (8).

7. The high-power parallel power module with a symmetrical packaging structure according to claim 6, characterized in that: The first buffer conductive sheet (3), the second buffer conductive sheet (5) and the third buffer conductive sheet (4) are all made of molybdenum.

8. The high-power parallel power module with a symmetrical packaging structure according to claim 1, characterized in that: The source power terminal (1) and the drain power terminal (17) are both cylindrical structures; an insulating sheet (2) is installed at the connection between the source power terminal (1) and the upper DBC plate (13); an insulating sheet (2) is installed at the connection between the drain power terminal (17) and the lower DBC plate (16); and the insulating sheet (2) is made of aluminum nitride ceramic or aluminum oxide ceramic.

9. The high-power parallel power module with a symmetrical packaging structure according to claim 1, characterized in that: The source power terminal (1), the drain power terminal (17) and the gate drive terminal (11) are all made of copper.

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