Embedded Ethernet switching device

Abstract

The utility model discloses an embedded Ethernet switching device, which relates to the technical field of computer interconnection and comprises an Ethernet switching module, and the Ethernet switching module comprises a micro-processing unit, a Switch unit and a PHY unit, and the Switch unit and the PHY unit interact with the micro-processing unit. Each of the micro-processing unit and the Switch unit comprises an SMI (System Management Interface); and the SMI interface of the Switch unit is connected with the SMI interface of the micro-processing unit. The power supply module comprises a power supply end group, the power supply end group comprises a first power supply end and a second power supply end which are connected with the Switch unit, and working voltage and working current required by the Switch unit are provided for the Switch unit through the first power supply end and the second power supply end based on a power supply time sequence; the detection module is connected with the first power supply end and the second power supply end of the power supply module, the power supply state of the power supply module is detected through the first power supply end and the second power supply end, and the embedded Ethernet switching device has high power supply stability, facilitates troubleshooting and maintenance of the power supply module and is high in applicability.

Description

Technical Field

[0001] The utility model relates to the technical field of computer interconnection, in particular to an embedded Ethernet switching device. Background Art

[0002] With the rapid development of computers and their interconnection technology, Ethernet has become the most popular short-distance Layer 2 computer network to date, and the core component of Ethernet is the Ethernet switch.

[0003] Usually, Ethernet switches use switching chips and CPUs of foreign brands. Switching chips are mainly represented by foreign manufacturers such as Broadcom and Marvell. They adopt an open structure and mainly consider non-security factors such as switching performance, reliability and power consumption. This leads to many security vulnerabilities, making it easy for criminals to implant monitoring and surveillance devices to steal state secrets. There are a series of security threats such as computer technology defects, viruses, information spam, hackers and information extortion.

[0004] With the further development of informatization in my country, information security issues have attracted increasing attention, and the demand for domestic switch solutions has become more and more urgent. At the same time, how to design a power supply solution for domestic Ethernet switches, improve the reliability of switch power supply and troubleshooting, and meet the power supply needs of domestic switches is also an urgent problem to be solved. In addition, existing Ethernet switches still have problems such as single function, large size and complex installation methods, and poor applicability, which cannot meet actual application needs. Utility Model Content

[0005] In view of the above problems and technical requirements, the inventors have proposed an embedded Ethernet switching device.

[0006] The technical solution of the utility model is as follows:

[0007] An embedded Ethernet switching device, comprising:

[0008] An Ethernet switching module, including a microprocessing unit and a Switch unit and a PHY unit interacting with the microprocessing unit;

[0009] The microprocessing unit and the Switch unit each include an SMI interface;

[0010] The SMI interface of the Switch unit is connected to the SMI interface of the microprocessor unit;

[0011] The PHY unit includes a PHY-SMI interface and an RGMII interface;

[0012] The PHY-SMI interface of the PHY unit is connected to the SMI interface of the microprocessing unit, and the RGMII interface of the PHY unit is connected to the Switch unit;

[0013] A power supply module, comprising a power supply terminal group, wherein the power supply terminal group comprises a first power supply terminal and a second power supply terminal connected to the Switch unit, and provides the Switch unit with a working voltage and a working current required by the Switch unit through the first power supply terminal and the second power supply terminal based on a power supply timing;

[0014] The detection module is connected to the microprocessing unit, the Switch unit, and the first power supply end and the second power supply end of the power supply module, and detects the power supply status of the power supply module through the first power supply end and the second power supply end.

[0015] A further technical solution is that the detection module includes a current detection unit group, and the current detection unit group includes a plurality of current detection units;

[0016] For any current detection unit, it includes a detection resistor Rsense, a switch S1, a switch S2, a switch S3, a switch S4, a capacitor C1, a capacitor C2, a differential amplifier U1, an operational amplifier U2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a sampling resistor Rref1 and a sampling resistor Rref2, wherein:

[0017] One end of the detection resistor Rsense is connected to one end of the capacitor C1 through the switch S1, and one end of the detection resistor Rsense is also connected to one end of the capacitor C2 through the switch S3;

[0018] The other end of the detection resistor Rsense is connected to one end of the capacitor C1 through the switch S2, and the other end of the detection resistor Rsense is also connected to one end of the capacitor C2 through the switch S4;

[0019] The other end of the capacitor C1 is connected to the non-inverting input end of the subtractor U1, and the other end of the capacitor C2 is connected to the inverting input end of the subtractor U1;

[0020] The first output terminal of the subtractor U1 is connected to the non-inverting input terminal of the operational amplifier U2 through the resistor R2, and the second output terminal of the subtractor U1 is connected to the inverting input terminal of the operational amplifier U2 through the resistor R1;

[0021] The inverting input terminal of the operational amplifier U2 is connected to the output terminal of the operational amplifier U2 through the resistor R3, and the non-inverting input terminal of the operational amplifier U2 is connected to one end of the sampling resistor Rref1 and one end of the sampling resistor Rref2 through the resistor R4;

[0022] The other end of the sampling resistor Rref1 is connected to the reference voltage source VCC, and the other end of the sampling resistor Rref2 is grounded.

[0023] A further technical solution is that the voltage detection unit includes a first detection terminal Sense1, a second detection terminal Sense2, a latch A1, a latch A2, an OR gate C1, a switch S9 and a differential amplifier unit, wherein the latch A1 and the latch A2 are both of the model RS1G373XC6;

[0024] For any latch, including a first pin, a second pin, a third pin, a fourth pin and a fifth pin;

[0025] The first pin and the second pin of the latch A1 are connected to the first detection terminal Sense1, and the first pin and the second pin of the latch A2 are connected to the second detection terminal Sense2;

[0026] The fifth pins of the latch A1 and the latch A2 are both connected to the input end of the differential amplifier unit, and the second pins of the latch A1 and the latch A2 are both connected to the output end of the differential amplifier unit;

[0027] The switch S9 includes a static end, a dynamic end, a first contact end and a second contact end, wherein the static end of the switch S9 is connected to the first input end of the OR gate C1, the first contact end of the switch S9 is connected to the third pin of the latch A1, and the second contact end of the switch S9 is connected to the third pin of the latch A2;

[0028] The fourth pin of latch A1 is connected to the third output terminal of OR gate C1, the fourth pin of latch A2 is connected to the second pin of OR gate C1, and the output terminal of OR gate C1 is connected to the microprocessing unit.

[0029] A further technical solution is that the voltage detection unit further includes a buffer subunit, and the buffer subunit includes a buffer B1, a buffer B2, a buffer B3 and a buffer B4, wherein:

[0030] The first detection terminal Sense1 is connected to the input terminal of the buffer B1 and the output terminal of the buffer B2, the output terminal of the buffer B1 is connected to the first pin of the latch A1, and the input terminal of the buffer B2 is connected to the second pin of the latch A1;

[0031] The second detection terminal Sense2 is connected to the input terminal of the buffer B3 and the output terminal of the buffer B4. The output terminal of the buffer B3 is connected to the first pin of the latch A2. The input terminal of the buffer B4 is connected to the second pin of the latch A2.

[0032] A further technical solution is that the power supply module includes a voltage conversion unit and a load switch unit;

[0033] The voltage conversion unit includes a voltage conversion chip and an inductor L1;

[0034] The voltage conversion chip model is SGM61020P, including VIN pin, EN pin, SW pin and PG pin, among which,

[0035] The VIN pin and the EN pin are connected to a voltage source VDD;

[0036] The SW pin is connected to a second power supply terminal through an inductor L1, and the second power supply terminal is connected to a Switch unit;

[0037] The PG pin is connected to a load switch unit, and the load switch unit is connected to a first power supply end;

[0038] The first power supply end is connected to a first detection end Sense1 of a voltage detection unit, and the second power supply end is connected to a second detection end Sense2 of the voltage detection unit.

[0039] A further technical solution is that the voltage conversion unit further includes a capacitance-resistance protection subunit, and the capacitance-resistance protection subunit includes a capacitor C24, a capacitor C122, a capacitor C18, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C118 and a resistor R312, wherein:

[0040] One end of the capacitor C24, one end of the capacitor C122 and one end of the capacitor C18 are connected to each other and to the VIN pin, and the other ends of the capacitor C24, the capacitor C122 and the capacitor C18 are grounded;

[0041] One end of the resistor R312 is connected to the second power supply end, and the other end of the resistor R312 is grounded;

[0042] One ends of the capacitor C11, the capacitor C12, the capacitor C13 and the capacitor C118 are all connected to the second power supply end, and the other ends of the capacitor C11, the capacitor C12, the capacitor C13 and the capacitor C118 are all grounded.

[0043] A further technical solution is that the load switch unit includes a load switch chip, a capacitor C206 and a capacitor C207;

[0044] The load switch chip model is SGM2575, including a VIN pin, a VOUT pin, an ON pin and a GND pin, wherein:

[0045] The ON pin is connected to the PG pin of the voltage conversion chip;

[0046] The VIN pin is connected to a first driving voltage, and the GND pin is grounded;

[0047] The VOUT pin is connected to the Switch unit;

[0048] One end of the capacitor C206 is connected to the VIN pin, and the other end of the capacitor C206 is grounded;

[0049] One end of the capacitor C207 is connected to the VOUT pin, and the other end of the capacitor C207 is grounded.

[0050] Its further technical solution is that the microprocessor unit includes an MCU chip of the GD32F4 series, and the MCU chip of the GD32F4 series includes an ETH_MAC pin and a GMAC0 pin;

[0051] The ETH_MAC pin is configured as RMII MAC mode and connected to the Switch unit to form an RMII data path between the MCU chip and the Switch unit;

[0052] The GMAC0 pin is connected to the RGMII interface of the PHY unit.

[0053] A further technical solution is that it also includes a connection module, the connection module includes a connector and a connection panel, the Ethernet switching module is connected to the connection panel via the connector, wherein:

[0054] The connection panel includes a plurality of signal transformers and a plurality of RJ45 plugs corresponding to the signal transformers one by one;

[0055] The Switch unit also includes a network interface subunit, and the network interface subunit includes a plurality of Switch network interfaces;

[0056] For any Switch network interface, the Switch network interface is connected to a signal transformer in the connection panel through a connector, and the signal transformer is connected to the corresponding RJ45 plug.

[0057] A further technical solution is that the connection panel further includes a level conversion chip, and the MCU chip further includes a UART pin;

[0058] The UART pin of the MCU chip is connected to the level conversion chip.

[0059] The beneficial technical effects of the utility model are:

[0060] The utility model provides an embedded Ethernet switching device, comprising an Ethernet switching module, a power supply module and a detection module. The power supply module provides the Switch unit with the required working voltage and working current according to the power supply timing of the Switch unit in the Ethernet switching module. The detection module is used to detect the power supply status of the power supply module, and the microprocessor module displays the abnormal detection result, thereby improving the power supply stability of the switching device and facilitating the troubleshooting and maintenance of the power supply module.

[0061] At the same time, through the interaction and cooperation of the microprocessor unit, the Switch unit and the PHY unit in the Ethernet switching module, the information security of the Ethernet switching device is effectively improved. In addition, the Ethernet switching device constructs a data path between the microprocessor unit and the Switch unit, realizes the switching function based on the protocol stack based on the data path, and realizes the functional diversification of the Ethernet switching device. In addition, the Ethernet switching module completes the setting of the physical interface through the connection module, reduces the volume of the Ethernet switching device, makes it easy to install and use, and improves the applicability of the Ethernet switching device. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 It is a schematic diagram of an embodiment of the embedded Ethernet switching device provided by the utility model.

[0063] Figure 2 It is a signal transmission schematic diagram of an embodiment provided by the utility model.

[0064] Figure 3 It is a schematic diagram of an embodiment of a power-on power supply module provided by the utility model.

[0065] Figure 4 It is a schematic diagram of an embodiment of a load switch unit provided by the utility model.

[0066] Figure 5 It is a schematic diagram of an embodiment of a power-on sequence provided by the utility model.

[0067] Figure 6 It is a schematic diagram of an embodiment of a current detection unit provided by the utility model.

[0068] Figure 7 It is a schematic diagram of an embodiment of a voltage detection unit provided by the utility model.

[0069] Figure 8 It is a schematic diagram of an embodiment of the differential amplifier unit provided by the utility model.

[0070] Fig. 9 It is a schematic diagram of an embodiment of the connection module provided by the utility model.

[0071] Fig.10 It is a schematic diagram of an embodiment of a voltage conversion module provided by the utility model.

[0072] Reference numerals: 100 - Ethernet switching module, 101 - MCU chip, 102 - Switch chip, 103 - PHY chip, 200 - connection module, 201 - connector, 202 - connection panel. DETAILED DESCRIPTION

[0073] The specific implementation of the utility model is further described below in conjunction with the accompanying drawings.

[0074] The utility model proposes an embedded Ethernet switching device, comprising:

[0075] The Ethernet switching module 100 includes a microprocessing unit and a Switch unit and a PHY unit interacting with the microprocessing unit;

[0076] The microprocessing unit and the Switch unit each include an SMI interface;

[0077] The SMI interface of the Switch unit is connected to the SMI interface of the microprocessor unit;

[0078] The PHY unit includes a PHY-SMI interface and an RGMII interface;

[0079] The PHY-SMI interface of the PHY unit is connected to the SMI interface of the microprocessing unit, and the RGMII interface of the PHY unit is connected to the Switch unit;

[0080] A power supply module, comprising a power supply terminal group, wherein the power supply terminal group comprises a first power supply terminal and a second power supply terminal connected to the Switch unit, and provides the Switch unit with a working voltage and a working current required by the Switch unit through the first power supply terminal and the second power supply terminal based on a power supply timing;

[0081] The detection module is connected to the microprocessing unit, the Switch unit, and the first power supply end and the second power supply end of the power supply module, and detects the power supply status of the power supply module through the first power supply end and the second power supply end.

[0082] Specifically, the SMI interface of the Switch unit is connected to the SMI interface of the microprocessor unit through an SMI bus, and the microprocessor unit interacts with the Switch unit, that is, the microprocessor unit controls the Switch unit through an SMI (Serial Management Interface) to implement the basic switching function of Ethernet. The basic switching functions include VLAN (Virtual LAN), QoS (Quality of Service), ACL (Access Control List), IGMP Snooping (Internet Group Management Protocol Snooping), static multicast, port speed limit, port aggregation, port flow control, port statistics, port mirroring, and storm suppression.

[0083] The SMI interface of the microprocessor unit is also connected to the PHY-SMI interface of the PHY (Physical Layer) unit through the SMI bus, and the PHY unit is managed through the PHY-SMI interface. The PHY unit is used to expand the number of interfaces of the Ethernet switch module 100 to improve the applicability of the Ethernet switch device. The PHY-SMI interface of the PHY unit, the SMI interface of the Switch unit, and the SMI interface of the microprocessor unit are of the same form.

[0084] The power supply module is also connected to the microprocessor unit. Under the control of the microprocessor unit, the power supply module provides the Switch unit with the operating voltage and operating current required by the Switch unit through the first power supply end and the second power supply end based on the power supply sequence. Generally, the Switch unit requires two different power supplies to power the Switch unit according to a preset power supply sequence, and the above power supply sequence is the preset power supply sequence of the Switch unit. In the Ethernet switching device, the Switch unit requires the power supply module to provide the first operating voltage and the first operating current through the first power supply end according to the preset power supply sequence, and to provide the second operating voltage and the second operating current through the second power supply end. The specific power supply method of the power supply module can refer to the following description.

[0085] The detection module detects the power supply status of the power supply module through the first power supply terminal and the second power supply terminal, specifically, detecting the first power supply voltage and the first power supply current output by the power supply module through the first power supply terminal, and the second power supply voltage and the second power supply current output by the power supply module through the second power supply terminal. The detection module feeds back the detection results of the first power supply terminal and the detection results of the second power supply terminal to the microprocessing unit. The specific connection method of the detection module, the microprocessing unit and the Switch unit can refer to the following description.

[0086] The microprocessing unit compares the first power supply voltage with the first voltage threshold, and compares the first power supply current with the first current threshold. When the difference between the first power supply voltage and the first voltage threshold and / or the difference between the first power supply current and the first current threshold exceeds a preset range, the microprocessing module outputs power supply abnormality information to facilitate troubleshooting and maintenance of the power supply module. Similarly, the microprocessing unit also compares the second power supply voltage with the second voltage threshold, and compares the second power supply current with the second current threshold. When the difference between the second power supply voltage and the second voltage threshold and / or the difference between the second power supply current and the second current threshold exceeds a preset range, the microprocessing module outputs power supply abnormality information.

[0087] In a specific implementation, the first voltage threshold is set according to the first operating voltage of the Switch unit, the first current threshold is set according to the first operating current of the Switch unit, the second voltage threshold is set according to the second operating voltage of the Switch unit, and the second current threshold is set according to the second operating current of the Switch unit.

[0088] The embedded Ethernet switching device uses a power supply module to power the Switch unit according to the power supply timing of the Switch unit in the Ethernet switching module, and uses a detection module to detect the power supply status of the power supply module, thereby meeting the power supply demand of the Ethernet switching device, improving the power supply reliability of the switch, and making the power supply module easier to troubleshoot and repair.

[0089] Further, the microprocessing unit includes an MCU chip 101 of the GD32F4 series, and the MCU chip 101 of the GD32F4 series includes an ETH_MAC pin and a GMAC0 pin;

[0090] The ETH_MAC pin is configured as RMII MAC mode and connected to the Switch unit to form an RMII data path between the MCU and the Switch unit;

[0091] The GMAC0 pin is connected to the RGMII interface of the PHY unit.

[0092] Specifically, in order to improve the information security of the Ethernet switching device, the microprocessor unit, the Switch unit and the PHY unit all use domestic components. In one embodiment of the utility model, the microprocessor unit uses an MCU chip 101 of the GD32F4 series, the Switch unit uses a Switch chip 102 of the SF2507 series, and the PHY unit uses a PHY chip 103 of the YT8521SH-CA series.

[0093] In order to realize the functional diversification of the Ethernet switching device, in one embodiment of the utility model, the ETH_MAC pin of the MCU chip 101 is configured as the RMII MAC mode, and is connected to the GMAC1 interface of the Switch chip 102 through the RMII bus to build a data path between the MCU chip 101 and the Switch chip 102. Based on the data path, the MCU chip 101 is able to process message information to realize functions based on the protocol stack, such as STP (Spanning Tree Protocol), LACP (Link Aggregation Control Protocol), GVRP (GARP VLAN Registration Protocol), etc.

[0094] like Figure 1 As shown, the RGMII interface of the PHY chip 103 is connected to the GMAC0 interface of the Switch chip 102 via the RGMII bus, and the PHY chip includes a GPHY5 interface. In one embodiment of the utility model, the GPHY5 interface is used as a 10 / 100 / 1000Base-T network interface and / or a 1000Base-X optical fiber interface to expand the number of interfaces of the Ethernet switch module 100.

[0095] like Figure 2 As shown, the SMI bus connected between the MCU chip 101, the Switch chip 102 and the PHY chip 103 is used to transmit two signals, MDC and MDIO. The RMII bus connected between the MCU chip 101 and the Switch chip 102 is used to transmit RMII_TXCLK, RMII_TXEN, RMII_TXD[1:0], RMII_RXDV, RMII_RXCLK, and RMII_RXD[1:0] 6 signals, the bit width, transmission direction and signal description of the above 6 signals are shown in Table 1. The RMII bus also needs to access an external clock as a reference clock. In one embodiment of the utility model, the external clock selects a 50MHz active clock.

[0096] Table 1 RMII bus signal description table

[0097] name Bit width Transmission direction describe RMII_TXCLK 1 output Transmit signal reference clock RMII_TXEN 1 output Send enable signal RMII_TXD[1:0] 2 output Sending Data RMII_RXDV 1 input Receive data valid signal RMII_RXCLK 1 input Receive signal reference clock RMII_RXD[1:0] 2 input Receiving Data

[0098] In Table 1, the transmission direction output indicates that the signal is transmitted from the MCU chip 101 to the Switch chip 102 , and the transmission direction input indicates that the signal is transmitted from the Switch chip 102 to the MCU chip 101 .

[0099] like Figure 2 As shown, the RGMII bus connected between the Switch chip 102 and the PHY chip 103 is used to transmit six signals, namely RGMII_TXCLK, RGMII_TXCTL, RGMII_TXD[3:0], RGMII_RXCTL, RGMII_RXCLK and RGMII_RXD[3:0]. The bit width, transmission direction and signal description of the above six signals are shown in Table 2.

[0100] Table 2 RGMII bus signal description table

[0101] name Bit width Transmission direction describe RGMII_TXCLK 1 output Transmit signal reference clock RGMII_TXCTL 1 output Send data control signal RGMII_TXD[3:0] 4 output Sending Data RGMII_RXCTL 1 input Receive data control signal RGMII_RXCLK 1 input Receive signal reference clock RGMII_RXD[3:0] 4 input Receiving Data

[0102] In Table 2, the transmission direction output indicates that the signal is transmitted from the Switch chip 102 to the PHY chip 103 , and the transmission direction input indicates that the signal is transmitted from the PHY chip 103 to the Switch chip 102 .

[0103] Further, the power supply module includes a voltage conversion unit and a load switch unit;

[0104] The voltage conversion unit includes a voltage conversion chip and an inductor L1;

[0105] The voltage conversion chip model is SGM61020P, including VIN pin, EN pin, SW pin and PG pin, among which,

[0106] The VIN pin and the EN pin are connected to a voltage source VDD;

[0107] The SW pin is connected to a second power supply terminal through an inductor L1, and the second power supply terminal is connected to a Switch unit;

[0108] The PG pin is connected to a load switch unit, and the load switch unit is connected to a first power supply end;

[0109] The first power supply end is connected to a first detection end Sense1 of a voltage detection unit, and the second power supply end is connected to a second detection end Sense2 of the voltage detection unit.

[0110] In one embodiment of the utility model, the first working voltage of the Switch unit is 3.3V, the first working current is 805mA, the second working voltage is 1.1V, and the second working current is 405mA. The preset power supply timing of the Switch unit is that the second working voltage is supplied before the first working voltage or is supplied at the same time. To supply power to the Switch unit according to the preset power supply timing, Figure 3 As shown, a 3.3V voltage source VDD equal to the first working voltage of the Switch unit is provided, and a 3.3V first driving voltage provided by the voltage source VDD is converted into a 1.1V second driving voltage equal to the second working voltage of the Switch unit by a voltage conversion unit. Figure 3 In the figure, DCDC stands for voltage conversion chip. The second driving voltage is loaded to the Switch unit and provides a working current of 805 mA to the Switch unit.

[0111] After the second driving voltage is loaded to the Switch unit, the MCU chip 101 sends a control signal to the EN pin of the voltage conversion chip through a preset power-on interval, and the control signal is transmitted to the load switch unit through the PG pin of the voltage conversion chip, and the load switch unit is controlled to load the 3.3V first driving voltage connected to the load switch unit to the Switch unit, and provide a 405mA working current to the Switch unit to complete the power supply of the Switch unit according to the preset power supply timing. The voltage source VDD also directly powers the microprocessor unit and the PHY unit. The working principle and pin configuration of the voltage conversion chip are consistent with the prior art and will not be repeated here.

[0112] The load switch unit includes a load switch chip, a capacitor C206 and a capacitor C207;

[0113] In one embodiment of the utility model, the load switch chip model is SGM2575, including a VIN pin, a VOUT pin, an ON pin and a GND pin, wherein:

[0114] The ON pin is connected to the PG pin of the voltage conversion chip;

[0115] The VIN pin is connected to a first driving voltage, and the GND pin is grounded;

[0116] The VOUT pin is connected to the Switch unit;

[0117] One end of the capacitor C206 is connected to the VIN pin, and the other end of the capacitor C206 is grounded;

[0118] One end of the capacitor C207 is connected to the VOUT pin, and the other end of the capacitor C207 is grounded.

[0119] In the load switch chip, the VOUT pin is connected to the second power supply terminal, the control signal is transmitted to the load switch chip through the ON pin, and under the control of the control signal, the load switch chip supplies power to the Switch unit through the VOUT pin and the second power supply terminal. The working principle and pin configuration of the load switch chip are consistent with the prior art and will not be repeated here.

[0120] Furthermore, the voltage conversion unit further includes a capacitance-resistance protection subunit, and the capacitance-resistance protection subunit includes a capacitor C24, a capacitor C122, a capacitor C18, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C118 and a resistor R312, wherein:

[0121] One end of the capacitor C24, one end of the capacitor C122 and one end of the capacitor C18 are connected to each other and to the VIN pin, and the other ends of the capacitor C24, the capacitor C122 and the capacitor C18 are grounded;

[0122] One end of the resistor R312 is connected to the second power supply end, and the other end of the resistor R312 is grounded;

[0123] One ends of the capacitor C11, the capacitor C12, the capacitor C13 and the capacitor C118 are all connected to the second power supply end, and the other ends of the capacitor C11, the capacitor C12, the capacitor C13 and the capacitor C118 are all grounded.

[0124] Specifically, the capacitance and resistance protection unit is used to filter out noise. In order to filter out high-frequency noise and low-frequency noise at the same time and achieve the decoupling effect of high-frequency noise and low-frequency noise, a capacitor with a larger capacitance and a capacitor with a smaller capacitance need to be comprehensively adopted in the capacitance and resistance protection unit. In one embodiment of the utility model, the capacitance of capacitor C11 and capacitor C12 are both 22μF, the capacitance of capacitor C24 is 4.7μF, the capacitance of capacitor C13 and capacitor C122 is 0.1μF, and the capacitance of capacitor C118 and capacitor C18 is 1000pF, wherein the capacitance of capacitor C11, capacitor C12 and capacitor C24 is relatively large, and is used to filter out high-frequency noise. The capacitance of capacitor C13, capacitor C122, capacitor 18, and capacitor C118 is relatively small, and is used to filter out low-frequency noise. The capacitance and resistance protection unit also includes a resistor R1287, one end of which is connected to one end of inductor L1, and the other end of which is connected to PG pin.

[0125] Further, the detection module includes a current detection unit group, and the current detection unit group includes a plurality of current detection units;

[0126] For any current detection unit, it includes a detection resistor Rsense, a switch S1, a switch S2, a switch S3, a switch S4, a capacitor C1, a capacitor C2, a differential amplifier U1, an operational amplifier U2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a sampling resistor Rref1 and a sampling resistor Rref2, wherein:

[0127] One end of the detection resistor Rsense is connected to one end of the capacitor C1 through the switch S1, and one end of the detection resistor Rsense is also connected to one end of the capacitor C2 through the switch S3;

[0128] The other end of the detection resistor Rsense is connected to one end of the capacitor C1 through the switch S2, and the other end of the detection resistor Rsense is also connected to one end of the capacitor C2 through the switch S4;

[0129] The other end of the capacitor C1 is connected to the non-inverting input end of the subtractor U1, and the other end of the capacitor C2 is connected to the inverting input end of the subtractor U1;

[0130] The first output terminal of the subtractor U1 is connected to the non-inverting input terminal of the operational amplifier U2 through the resistor R2, and the second output terminal of the subtractor U1 is connected to the inverting input terminal of the operational amplifier U2 through the resistor R1;

[0131] The inverting input terminal of the operational amplifier U2 is connected to the output terminal of the operational amplifier U2 through the resistor R3, and the non-inverting input terminal of the operational amplifier U2 is connected to one end of the sampling resistor Rref1 and one end of the sampling resistor Rref2 through the resistor R4;

[0132] The other end of the sampling resistor Rref1 is connected to the reference voltage source VCC, and the other end of the sampling resistor Rref2 is grounded.

[0133] like Figure 6 As shown, the current detection unit also includes a switch S5, a switch S6, a switch S7 and a switch S8, the switch S5 is connected in parallel with the capacitor C3, the switch S6 is connected in parallel with the capacitor C4, the first output end of the subtractor U1 is connected to one end of the resistor R2 through the switch S7, and the second output end of the subtractor U1 is connected to one end of the resistor R1 through the switch S8. The detection module also includes an ADC chip, the output end of the operational amplifier U2 is connected to the ADC chip, and the ADC chip is connected to the MCU chip.

[0134] The first power supply end and the second power supply end are both connected to a current detection unit, and the first power supply current and the second power supply current are detected by the current detection unit connected to the first power supply end and the second power supply end. The current detection unit is connected in the same manner as the first power supply end and the second power supply end, and the principle of detecting the first power supply current and the second power supply current is also the same.

[0135] The following takes the detection principle of the first power supply end and the first power supply current as an example to explain the connection method and detection principle of the current detection unit and the power supply end. The detection resistor Rsense in the current detection unit is connected in series between the first power supply end and the Switch unit. The subtractor U1 measures the voltage difference between the two ends of the detection resistor Rsense and outputs it to the operational amplifier U2. The voltage difference between the two ends of the detection resistor Rsense is differentially amplified and output to the ADC chip in the form of an analog signal. The ADC chip converts the analog signal into a digital signal and outputs it to the MCU chip. Finally, based on Ohm's law, the current of the circuit where the detection resistor Rsense is located is obtained, that is, the first power supply current output by the first power supply end.

[0136] In order to ensure the accuracy of current detection without affecting the power supply circuit, it is necessary to select a high-precision, low-resistance resistor as the detection resistor Rsense. In one embodiment of the utility model, the accuracy of the detection resistor Rsense is at least 0.1%, and the resistance is 0.01Ω. In specific implementation, the accuracy and resistance of the detection resistor Rsense can be selected according to actual needs.

[0137] Further, the detection unit further includes a voltage detection unit, which includes a first detection terminal Sense1, a second detection terminal Sense2, a latch A1, a latch A2, an OR gate C1, a switch S9 and a differential amplifier unit, wherein the latch A1 and the latch A2 are both of the model RS1G373XC6;

[0138] For any latch, including a first pin, a second pin, a third pin, a fourth pin and a fifth pin;

[0139] The first pin and the second pin of the latch A1 are connected to the first detection terminal Sense1, and the first pin and the second pin of the latch A2 are connected to the second detection terminal Sense2;

[0140] The fifth pins of the latch A1 and the latch A2 are both connected to the input end of the differential amplifier unit, and the second pins of the latch A1 and the latch A2 are both connected to the output end of the differential amplifier unit;

[0141] The switch S9 includes a static end, a dynamic end, a first contact end and a second contact end, wherein the static end of the switch S9 is connected to the first input end of the OR gate C1, the first contact end of the switch S9 is connected to the third pin of the latch A1, and the second contact end of the switch S9 is connected to the third pin of the latch A2;

[0142] The fourth pin of latch A1 is connected to the third output terminal of OR gate C1, the fourth pin of latch A2 is connected to the second pin of OR gate C1, and the output terminal of OR gate C1 is connected to the microprocessing unit.

[0143] like Figure 7 As shown, the voltage detection unit further includes a buffer subunit, and the buffer subunit includes a buffer B1, a buffer B2, a buffer B3, a buffer B4, a buffer B5, a buffer B6 and a buffer B7, wherein:

[0144] The first detection terminal Sense1 is connected to the input terminal of the buffer B1 and the output terminal of the buffer B2, the output terminal of the buffer B1 is connected to the first pin of the latch A1, and the input terminal of the buffer B2 is connected to the second pin of the latch A1;

[0145] The second detection terminal Sense2 is connected to the input terminal of the buffer B3 and the output terminal of the buffer B4. The output terminal of the buffer B3 is connected to the first pin of the latch A2. The input terminal of the buffer B4 is connected to the second pin of the latch A2.

[0146] The input end of the buffer B5 is connected to the output end of the OR gate C1 and the third end of the buffer B7, the output end of the buffer B5 is connected to the input end of the buffer B6 and the MCU chip 101, the output end of the buffer B6 is connected to the input end of the buffer B7 and the first input end of the OR gate C1. The input end of the buffer B7 is connected to the static end of the switch S9, and the output end of the buffer B7 is connected to the ADC chip.

[0147] The first power supply end is connected to a first detection end Sense1 of a voltage detection unit, and the second power supply end is connected to a second detection end Sense2 of the voltage detection unit.

[0148] When performing voltage detection, the first power supply voltage is input into latch A1, and the second power supply voltage is input into latch A2. The MCU chip controls switch S9 by outputting a Select signal, and uses switch S9 to select a detection channel, that is, when the moving end of switch S9 is connected to the first contact end, the first power supply voltage stored in latch A1 is input into the differential amplifier unit via the fifth pin of latch A1, and after being amplified by the differential amplifier unit, it is fed back to latch A1 in the form of an analog signal through the second pin of latch A1, and then input into the ADC chip via the third pin of latch A1 through buffer B7. The ADC chip converts the analog signal into a digital signal and inputs it into the MCU, thereby obtaining the first power supply voltage output by the first power supply end.

[0149] When the moving end of the switch S9 is connected to the second contact section, the second power supply voltage stored in the latch A2 is input to the differential amplifier unit via the fifth pin of the latch A2, and is fed back to the latch A2 in the form of an analog signal after being amplified by the differential amplifier unit, and is then input to the ADC chip via the third pin of the latch A2 via the buffer B7. The ADC chip converts the analog signal into a digital signal and inputs it into the MCU, thereby obtaining the second power supply voltage output by the second power supply end.

[0150] Figure 7 The Pulse Generator module in FIG. 1 represents a differential amplifier subunit, and the differential amplifier subunit includes an operational amplifier U3, a resistor R5, a resistor R6, a resistor Rref3, and a resistor Rref4. Figure 8 As shown, the inverting input terminal of the operational amplifier U3 is connected to the output terminal of the operational amplifier U3 through the resistor R6. The fifth pin of the latch A1 and the fifth pin of the latch A2 are connected to the non-inverting input terminal of the operational amplifier U3 through the resistor Rref3, and the output terminal of the operational amplifier U3 is connected to the second pin of the latch A1 and the second pin of the latch A2.

[0151] Furthermore, the embedded Ethernet switching device further comprises a connection module 200, wherein the connection module 200 comprises a connector 201 and a connection panel 202, and the Ethernet switching module is connected to the connection panel 202 via the connector 201, wherein:

[0152] The connection panel 202 includes a plurality of signal transformers and a plurality of RJ45 plugs corresponding to the signal transformers one by one;

[0153] The Switch unit also includes a network interface subunit, and the network interface subunit includes a plurality of Switch network interfaces;

[0154] For any Switch network interface, the Switch network interface is connected to a signal transformer in the connection panel through a connector, and the signal transformer is connected to the corresponding RJ45 plug.

[0155] Specifically, the connector 201 may be a pin header and a female header, that is, the Ethernet switch module 100 is connected to the connection panel via a pin header and a female header, so as to facilitate installation and removal of the Ethernet switch module 100. In specific implementation, the form of the connector 201 can be flexibly selected according to actual needs.

[0156] The Switch chip includes five network interfaces, namely Figure 1 The GPHY0 interface, GPHY1 interface, GPHY2 interface, GPHY3 interface and GPHY4 interface shown in the figure. The five network interfaces of the Switch chip are respectively connected to an RJ45 plug through a signal transformer to transmit an MDI signal. When the GPHY5 interface in the PHY chip is used as a network interface, the GPHY5 interface is connected to the corresponding RJ45 plug through a signal transformer to transmit an MDI signal. The connection panel 202 is also provided with port indicator lights corresponding to the RJ45 plugs, namely LED_0-4 and LED5 to indicate the connection status of the corresponding ports.

[0157] The connection panel 202 is also provided with an SFP optical module, and the MCU chip is connected to the SFP optical module via an IIC bus. The GPHY5 port of the PHY chip is also connected to the SFP optical module as an optical fiber interface to transmit SCMII signals.

[0158] Furthermore, the connection panel 202 further includes a level conversion chip, and the MCU chip further includes a UART pin;

[0159] The UART pin is connected to a level conversion chip.

[0160] Specifically, the level conversion chip may be a MAX232 chip, and a Console interface is formed on the connection panel based on the level conversion chip to control the MCU chip through the Console interface.

[0161] Furthermore, a voltage source VCC is provided to supply power to the connection panel, the voltage source VCC may be 12V, and the voltage source VCC is supplied before the voltage source VDD. Figure 5 FIG. 2 shows a power-on timing sequence of an Ethernet switching device in an embodiment of the utility model. Figure 5As shown, the 12V voltage source VCC powers the connection panel, the 3.3V voltage source VDD powers the MCU chip and the PHY chip, and the voltage conversion module converts the 3.3V voltage into a 1.1V voltage to provide a first working voltage for the Switch chip, and after the 1.1V voltage is loaded into the Switch chip, the 3.3V voltage is loaded into the Switch chip to complete the power supply of the Ethernet switching device.

[0162] The embedded Ethernet switching device provided by the utility model utilizes the connector 201 and the connection panel 202 in the above-mentioned connection module to complete the setting of the physical interface, thereby reducing the volume of the Ethernet switching device, making it easier to install and use, and improving the applicability of the Ethernet switching device.

[0163] Furthermore, the Ethernet switching module also includes a reset unit, and the reset unit is connected to the MCU chip 101.

[0164] Specifically, the reset unit includes at least one reset chip. When the reset unit includes only one reset chip, the reset chip is only connected to the MCU chip 101. After the Ethernet switching device is powered on, the reset chip provides a reset signal to the MCU chip 101 to initialize the MCU chip 101. After the MCU chip 101 is initialized, the reset signal is output to the Switch chip 102 and the PHY chip 103 to initialize the Switch chip 102 and the PHY chip 103. The reset chip may be a reset chip of model CN809S.

[0165] When the reset unit includes more than one reset chip, the Switch chip 102 and / or the PHY chip 103 is connected to a reset chip, and the Switch chip 102 and / or the PHY chip 103 can be initialized by the connected reset chip to enrich the reset scheme of the Ethernet switch module.

[0166] Optionally, the MCU chip 101 is provided with a SPI Flash chip for expanding the Flash capacity of the MCU chip 101, and the SPI Flash chip is connected to the MCU chip 101 via a SPI bus.

[0167] Furthermore, the MCU chip 101 , the Switch chip 102 and the PHY chip 103 are all connected to a clock unit for providing a clock reference.

[0168] like Figure 1As shown, the MCU chip 101, the Switch chip 102 and the PHY chip 103 all have XTAL pins, and the clock unit is connected to the MCU chip 101, the Switch chip 102 and the PHY chip 103 through the corresponding XTAL pins. The clock unit can use a 25MHz passive crystal oscillator.

[0169] The above is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the protection scope of the present invention.

Claims

1. An embedded Ethernet switching device, characterized in that: include: An Ethernet switching module, including a microprocessing unit and a Switch unit and a PHY unit interacting with the microprocessing unit; The microprocessing unit and the Switch unit each include an SMI interface; The SMI interface of the Switch unit is connected to the SMI interface of the microprocessor unit; The PHY unit includes a PHY-SMI interface and an RGMII interface; The PHY-SMI interface of the PHY unit is connected to the SMI interface of the microprocessing unit, and the RGMII interface of the PHY unit is connected to the Switch unit; A power supply module, comprising a power supply terminal group, wherein the power supply terminal group comprises a first power supply terminal and a second power supply terminal connected to the Switch unit, and provides the Switch unit with a working voltage and a working current required by the Switch unit through the first power supply terminal and the second power supply terminal based on a power supply timing; The detection module is connected to the microprocessing unit, the Switch unit, and the first power supply end and the second power supply end of the power supply module, and detects the power supply status of the power supply module through the first power supply end and the second power supply end.

2. The embedded Ethernet switching device according to claim 1, characterized in that: The detection module includes a current detection unit group, and the current detection unit group includes a plurality of current detection units; For any current detection unit, including a detection resistor Rsense, a switch S1, a switch S2, a switch S3, a switch S4, a capacitor C1, a capacitor C2, a differential amplifier U1, an operational amplifier U2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a sampling resistor Rref1 and a sampling resistor Rref2, wherein one end of the detection resistor Rsense is connected to one end of the capacitor C1 through the switch S1, and one end of the detection resistor Rsense is also connected to one end of the capacitor C2 through the switch S3; The other end of the detection resistor Rsense is connected to one end of the capacitor C1 through the switch S2, and the other end of the detection resistor Rsense is also connected to one end of the capacitor C2 through the switch S4; The other end of the capacitor C1 is connected to the non-inverting input end of the subtractor U1, and the other end of the capacitor C2 is connected to the inverting input end of the subtractor U1; The first output terminal of the subtractor U1 is connected to the non-inverting input terminal of the operational amplifier U2 through the resistor R2, and the second output terminal of the subtractor U1 is connected to the inverting input terminal of the operational amplifier U2 through the resistor R1; The inverting input terminal of the operational amplifier U2 is connected to the output terminal of the operational amplifier U2 through the resistor R3, and the non-inverting input terminal of the operational amplifier U2 is connected to one end of the sampling resistor Rref1 and one end of the sampling resistor Rref2 through the resistor R4; The other end of the sampling resistor Rref1 is connected to the reference voltage source VCC, and the other end of the sampling resistor Rref2 is grounded.

3. The embedded Ethernet switching device according to claim 2, characterized in that: The detection unit further includes a voltage detection unit, which includes a first detection terminal Sense1, a second detection terminal Sense2, a latch A1, a latch A2, an OR gate C1, a switch S9 and a differential amplifier unit, wherein the latch A1 and the latch A2 are both of the model RS1G373XC6; For any latch, including a first pin, a second pin, a third pin, a fourth pin and a fifth pin; The first pin and the second pin of the latch A1 are connected to the first detection terminal Sense1, and the first pin and the second pin of the latch A2 are connected to the second detection terminal Sense2; The fifth pins of the latch A1 and the latch A2 are both connected to the input end of the differential amplifier unit, and the second pins of the latch A1 and the latch A2 are both connected to the output end of the differential amplifier unit; The switch S9 includes a static end, a dynamic end, a first contact end and a second contact end, wherein the static end of the switch S9 is connected to the first input end of the OR gate C1, the first contact end of the switch S9 is connected to the third pin of the latch A1, and the second contact end of the switch S9 is connected to the third pin of the latch A2; The fourth pin of latch A1 is connected to the third output terminal of OR gate C1, the fourth pin of latch A2 is connected to the second pin of OR gate C1, and the output terminal of OR gate C1 is connected to the microprocessing unit.

4. The embedded Ethernet switching device according to claim 3, characterized in that: The voltage detection unit further includes a buffer subunit, and the buffer subunit includes a buffer B1, a buffer B2, a buffer B3 and a buffer B4, wherein: The first detection terminal Sense1 is connected to the input terminal of the buffer B1 and the output terminal of the buffer B2, the output terminal of the buffer B1 is connected to the first pin of the latch A1, and the input terminal of the buffer B2 is connected to the second pin of the latch A1; The second detection terminal Sense2 is connected to the input terminal of the buffer B3 and the output terminal of the buffer B4. The output terminal of the buffer B3 is connected to the first pin of the latch A2. The input terminal of the buffer B4 is connected to the second pin of the latch A2.

5. The embedded Ethernet switching device according to claim 3, characterized in that: The power supply module includes a voltage conversion unit and a load switch unit; The voltage conversion unit includes a voltage conversion chip and an inductor L1; The voltage conversion chip model is SGM61020P, including VIN pin, EN pin, SW pin and PG pin, among which, The VIN pin and the EN pin are connected to a voltage source VDD; The SW pin is connected to a second power supply terminal through an inductor L1, and the second power supply terminal is connected to a Switch unit; The PG pin is connected to a load switch unit, and the load switch unit is connected to a first power supply end; The first power supply end is connected to a first detection end Sense1 of a voltage detection unit, and the second power supply end is connected to a second detection end Sense2 of the voltage detection unit.

6. The embedded Ethernet switching device according to claim 5, characterized in that: The voltage conversion unit further includes a capacitance-resistance protection subunit, which includes a capacitor C24, a capacitor C122, a capacitor C18, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C118 and a resistor R312, wherein: One end of the capacitor C24, one end of the capacitor C122 and one end of the capacitor C18 are connected to each other and to the VIN pin, and the other ends of the capacitor C24, the capacitor C122 and the capacitor C18 are grounded; One end of the resistor R312 is connected to the second power supply end, and the other end of the resistor R312 is grounded; One ends of the capacitor C11, the capacitor C12, the capacitor C13 and the capacitor C118 are all connected to the second power supply end, and the other ends of the capacitor C11, the capacitor C12, the capacitor C13 and the capacitor C118 are all grounded.

7. The embedded Ethernet switching device according to claim 5, characterized in that: The load switch unit includes a load switch chip, a capacitor C206 and a capacitor C207; The load switch chip model is SGM2575, including a VIN pin, a VOUT pin, an ON pin and a GND pin, wherein: The ON pin is connected to the PG pin of the voltage conversion chip; The VIN pin is connected to a first driving voltage, and the GND pin is grounded; The VOUT pin is connected to the Switch unit; One end of the capacitor C206 is connected to the VIN pin, and the other end of the capacitor C206 is grounded; One end of the capacitor C207 is connected to the VOUT pin, and the other end of the capacitor C207 is grounded.

8. The embedded Ethernet switching device according to claim 7, characterized in that: The microprocessor unit includes an MCU chip of the GD32F4 series, and the MCU chip of the GD32F4 series includes an ETH_MAC pin and a GMAC0 pin; The ETH_MAC pin is configured as RMII MAC mode and connected to the Switch unit to form an RMII data path between the MCU chip and the Switch unit; The GMAC0 pin is connected to the RGMII interface of the PHY unit.

9. The embedded Ethernet switching device according to claim 8, characterized in that: It also includes a connection module, which includes a connector and a connection panel, and the Ethernet switching module is connected to the connection panel via the connector, wherein: The connection panel includes a plurality of signal transformers and a plurality of RJ45 plugs corresponding to the signal transformers one by one; The Switch unit also includes a network interface subunit, and the network interface subunit includes a plurality of Switch network interfaces; For any Switch network interface, the Switch network interface is connected to a signal transformer in the connection panel through a connector, and the signal transformer is connected to the corresponding RJ45 plug.

10. The embedded Ethernet switching device according to claim 9, characterized in that: The connection panel also includes a level conversion chip, and the MCU chip also includes a UART pin; The UART pin of the MCU chip is connected to the level conversion chip.

Images