Printed circuit board structure and method for its manufacture

Abstract

A printed circuit board structure (100) and a method for manufacturing the same are provided. The printed circuit board structure (100) comprises a ceramic plate (13), a thick circuit layer (111) formed on the ceramic plate (13), and a thin circuit layer (C1) formed on the ceramic plate (13). The thick circuit layer (111) has a thickness greater than or equal to 200 µm, and the thin circuit layer (C1) has a thickness in the range of 1 µm to 150 µm. The thin circuit layer (C1) comprises a sputtering layout segment (21) bonded to the ceramic plate (13) and an electroplating layer (6) bonded to the sputtering layout segment (21). The material of the electroplating layer (6) is different from that of the sputtering layout segment (21).

Description

Some references, which may include patents, patent applications, and various publications, may be cited and discussed in the specification of this disclosure. The citation and / or discussion of such references is merely for the purpose of illustrating the description of the present disclosure and does not constitute an admission of the fact that such reference is "prior art" for the disclosure described herein. All references cited and discussed in this specification are incorporated into the present specification in their entirety and to the same extent as if each reference was individually incorporated by reference.The present disclosure relates to a printed circuit board, and more particularly to a printed circuit board structure and method of manufacturing the same.A conventional ceramic circuit board is provided with metal circuits by a chemical etching method. However, since the widths of the metal circuits are influenced by the lateral etching in the chemical etching method, the metal circuits cannot have high pattern accuracy, whereby an electrical short circuit may easily occur. Moreover, the conventional ceramic circuit board must have metal circuits of different thicknesses in order to meet various practical requirements.In view of the above-mentioned technical deficiencies, the present disclosure provides a printed circuit board structure and method for manufacturing the same to effectively eliminate the problems associated with conventional ceramic printed circuit boards.In order to solve the above-mentioned problems, one of the technical aspects of the present disclosure is to provide a method of manufacturing a circuit board structure, including a preparation step, a patterning step, a sputtering step, a shielding step, an electroplating step, and a chemical etching step. The preparing step is implemented by providing a metallized ceramic substrate. The metallized ceramic substrate includes a ceramic plate, a first metal layer, and a second metal layer. The ceramic plate has a first surface and a second surface opposite the first surface. The first metal layer and the second metal layer are formed on the first and second surfaces of the ceramic plate, respectively. The patterning step is implemented by patterning the first metal layer to remove a portion of the first metal layer and thereby form a first thick circuit layer. Moreover, the thickness of the first thick circuit layer is equal to or greater than 200 μm, and a part of the first surface is exposed from the first thick circuit layer and defined as a first processing region. The sputtering step is implemented by sputtering the first processing region of the ceramic plate to form a first sputtering conductor layer. The shielding step is implemented by forming a first shielding layer on the first sputtering conductor layer. The first shield layer has a first patterned trench, and a part of the first sputtering conductor layer is exposed from the first shield layer through the first patterned trench and is defined as a first sputtering layout segment. The electroplating step is implemented by electroplating the first sputter layout segment of the first sputter conductor layer to form a first electroplating layer connected to the first sputter layout segment. The chemical etching step is implemented by removing the first shield layer and another part of the first sputtering conductor layer connected to the first shield layer, so that the first plating layer and the first sputtering layout segment, which are collectively defined as a first thin circuit layer, are maintained. Moreover, the thickness of the first thin circuit layer is in a range of 1 μm to 150 μm.In order to solve the above-mentioned problems, another of the technical aspects of the present disclosure is to provide a circuit board structure including a ceramic plate, a thick circuit layer, and a thin circuit layer. The ceramic plate has a first surface and a second surface opposite the first surface. The thick circuit layer is formed on the first surface of the ceramic plate and has a thickness of 200 μm or more. Moreover, a part of the first surface is exposed from the first thick circuit layer and is defined as a first processing region. The thin circuit layer is formed on the first processing region of the first surface and has a thickness in a range of 1 μm to 150 μm. The thin circuit layer includes a sputtering layout segment connected to the first surface and a first plating layer connected to the sputtering layout segment, and the first plating layer and the first sputtering layout segment are each made of different materials.In order to solve the above-mentioned problems, another of the technical aspects of the present disclosure is to provide a printed circuit board structure including a ceramic plate, a thick circuit layer, and a sputtering circuit layer. The ceramic plate has a first surface and a second surface opposite the first surface. The thick circuit layer is formed on the first surface of the ceramic plate and has a thickness of 200 μm or more. Moreover, a part of the first surface is exposed from the first thick circuit layer and is defined as a first processing region. The sputtering circuit layer is formed on the first processing region of the first surface and has a thickness in a range of 0.1 μm to 1 μm.Therefore, each of the manufacturing methods and each of the circuit board structures provided by the present disclosure has only easy side etching on the first sputtering layout segment (or the sputtering circuit layer) through the steps and the configuration thereof, so that the pattern accuracy of the first thin circuit layer (or the sputtering circuit layer) is not impaired to prevent an electrical short from occurring at the first thin circuit layer (or the sputtering circuit layer). Accordingly, the first thick circuit layer and the first thin circuit layer (or the sputtering circuit layer) can be accurately formed by implementing the above steps to meet various practical requirements.These and other aspects of the present disclosure will become apparent from the following description of the embodiment taken in conjunction with the following drawings and their labels, although variations and modifications may be made therein without departing from the spirit and scope of the novel concepts of the disclosure.The described preferred embodiments can be better understood with reference to the following description and the accompanying drawings. The following are shown: FIG. 1 is a flow chart of a method for manufacturing a printed circuit board structure according to a first embodiment of the present disclosure, FIG. 2 shows a schematic view of a preparation step from FIG. 1, FIG. 3 shows a schematic view of a structuring step from FIG. 1, FIG. 4 shows a schematic view of a sputtering step from FIG. 1 , FIG. 5 is a schematic view of a shielding step of FIG. 1 , FIG. 6 shows a schematic view of a electroplating step from FIG. 1 , FIG. 7 is a schematic view of a chemical etching step of FIG. 1 , FIG. 8 is a schematic view of a first variation of the circuit board structure according to the first embodiment of the present disclosure, FIG. 9 is a schematic view of a second variation of the circuit board structure according to the first embodiment of the present disclosure, FIG. 10 is a schematic view of a third variation of the circuit board structure according to the first embodiment of the present disclosure, FIG. 11 is a schematic view of the circuit board structure according to a second embodiment of the present disclosure, FIG. 12 is a schematic view of the shielding step of the manufacturing method according to a third embodiment of the present disclosure, FIG. 13 is a schematic view of the electroplating step of the manufacturing method according to the third embodiment of the present disclosure, FIG. 14 is a schematic view of the chemical etching step of the manufacturing method according to the third embodiment of the present disclosure; and FIG. 15 is a schematic view of the circuit board structure according to a fourth embodiment of the present disclosure.The present disclosure will be described in more detail in the following examples, which are for illustrative purposes only, as numerous modifications and variations therein will be apparent to those skilled in the art. Like numerals in the drawings indicate like components throughout the views. As used herein in the specification and in the following claims, unless the context clearly dictates otherwise, the meaning of "a / an" and "the / s" includes plural, and includes the meaning of "in" "in" and "on". For convenience of the reader, titles or subtitles may be used herein, but do not affect the scope of the present disclosure.The terms used herein generally have their common meaning in the art. In the event of conflict, the present document, including all definitions contained herein, takes precedence. The same can be expressed in several ways. Alternative terms and synonyms may be used for all terms discussed herein, and it is not particularly important whether a term is discussed or explained in more detail herein. The denomination of one or more synonyms does not exclude the use of other synonyms. The use of examples in any places in this specification, including examples of any terms, is merely illustrative and does not in any way limit the scope and meaning of the present disclosure or any exemplary term. Likewise, the present disclosure is not limited to the various embodiments set forth herein. Numerical words such as "first / first / first", "second / second / second" or "third / third / third" may be used to describe various components, signals or the like that are used merely to distinguish one component / signal from one / another, and these numerical words are neither intended nor intended to impose substantial restrictions on the components, signals or the like.[First Embodiment]Referring to FIGS. 1 to 10, a first embodiment of the present disclosure is provided. As illustrated in FIGS. 1 to 7, the present embodiment provides a method S 100 for manufacturing a circuit board structure, which sequentially includes (or implements) a preparation step S 110, a patterning step S 120, a sputtering step S 130, a shielding step S 140, a plating step S 150, and a chemical etching step S 160.Hereinafter, steps S 110-S 160 of the manufacturing method S 100 implemented to manufacture a circuit board structure 100 will be sequentially described, but the present disclosure is not limited thereto. For example, in other embodiments of the present disclosure not illustrated in the drawings, steps S 110-S 160 of the manufacturing method S 100 may be adjusted (e.g., rearranged, added, or removed) according to design requirements.As shown in FIGS. 1 and 2, the preparation step S 110 is implemented by providing a metallized ceramic substrate 1 including a ceramic plate 13, a first metal layer 11 and a second metal layer 12, the latter two being formed on two opposite sides of the ceramic plate 13. In other words, the ceramic plate 13 has a first surface 131 and a second surface 132 opposite to the first surface 131, and the first metal layer 11 and the second metal layer 12 are formed on the first surface 131 and the second surface 132, respectively.Note that in the preparation step S 110, the metallized ceramic substrate 1 may be a direct bonded copper ceramic (DBC) substrate, and the first metal layer 11 and the second metal layer 12 may be sintered on the first surface 131 and the second surface 132 of the ceramic plate 13, respectively. In other words, each of the first metal layer 11 and the second metal layer 12 according to the present embodiment is sintered and fixed to the ceramic plate 13 via a bonding layer 14 (e.g., a sintering layer).Alternatively, in preparation step S 110, the metallized ceramic substrate 1 may be an active solder (AMB) ceramic substrate, and the first metal layer 11 and the second metal layer 12 are soldered to the first surface 131 and the second surface 132 of the ceramic plate 13, respectively. In other words, according to the present embodiment, each of the first metal layer 11 and the second metal layer 12 is soldered and fixed on the ceramic plate 13 via a connection layer 14 (e.g., a solder layer).As illustrated in FIGS. 1 to 3, the patterning step S 120 is implemented by patterning the first metal layer 11 and the second metal layer 12 to remove a part of the first metal layer 11 and a part of the second metal layer 12 to form a first thick circuit layer 111 and a second thick circuit layer 121, respectively, and the first thick circuit layer 111 and the second thick circuit layer 121 may have different patterns or thicknesses, but the present disclosure is not limited thereto. For example, according to other embodiments of the present disclosure not illustrated in the drawings, the manufacturing method S 100 may be implemented without patterning the second metal layer 12 according to design requirements (for example, an original structure of the second metal layer 12 may be maintained, and the second thick circuit layer 121 is not formed).Specifically, the patterning of the first metal layer 11 and the second metal layer 12 may be implemented in a film mounting manner, an exposure manner, and a development manner, respectively, but the present disclosure is not limited thereto. Moreover, each of the thickness of the first thick circuit layer 111 and the thickness of the second thick circuit layer 121 is equal to or greater than 200 μm, a part of the first surface 131 is exposed from the first thick circuit layer 111 and is defined as a first processing region 1311, and a part of the second surface 132 is exposed from the second thick circuit layer 121 and is defined as a second processing region 1321.As illustrated in FIGS. 1, 3, and 4, the sputtering step S 130 is implemented by sputtering the first processing region 1311 of the ceramic plate 13 to form a first sputtering conductor layer 2 and sputtering the second processing region 1321 of the ceramic plate 13 to form a second sputtering conductor layer 3, but the present disclosure is not limited thereto. For example, in other embodiments of the present disclosure not illustrated in the drawings, when the second metal layer 12 is not patterned at the patterning step S 120, the manufacturing method S 100 is implemented without the formation of the second processing region 1321 and the second sputtering conductor layer 3.Specifically, the first sputtering conductor layer 2 and the second sputtering conductor layer 3 are made of the same material, and the thickness of the first sputtering conductor layer 2 and the thickness of the second sputtering conductor layer 3 are each in a range of 0.1 μm to 1 μm.As illustrated in FIGS. 1, 4, and 5, the shielding step S 140 is implemented by forming a first shielding layer 4 on the first sputtering conductor layer 2 and forming a second shielding layer 5 on the second sputtering conductor layer 3. Specifically, the first shield layer 4 has a first patterned trench 41, and a part of the first sputtering conductor layer 2 is exposed from the first shield layer 4 through the first patterned trench 41 and is defined as a first sputtering layout segment 21, but the present disclosure is not limited thereto.For example, in other embodiments of the present disclosure not illustrated in the drawings, when the second metal layer 12 is not patterned, the manufacturing method S 100 is implemented without forming the second shield layer 5 to cover the second sputtering conductor layer 3 according to the design requirements.As illustrated in FIGS. 1, 5, and 6, the electroplating step S 150 is implemented by electroplating the first sputtering layout segment 21 of the first sputtering conductor layer 2 to form a first electroplating layer 6 connected to the first sputtering layout segment 21. According to the present embodiment, the first plating layer 6 and the first sputtering layout segment 21 are each made of different materials, so that the first plating layer 6 does not have lateral etching in the following chemical etching step S 160, but the present disclosure is not limited thereto.As illustrated in FIGS. 1, 6, and 7, the chemical etching step S 160 is implemented by removing the first shield layer 4 and another part of the first sputtering conductor layer 2 connected to (or shielded by) the first shield layer 2 so that the first plating layer 6 and the first sputtering layout segment 21 collectively defined as a first thin circuit layer C 1 are maintained. Moreover, the thickness of the first thin circuit layer C 1 is in a range of 1 μm to 150 μm, and the thickness of the first sputtering layout segment 21 is in a range of 0.1 μm to 1 μm. Further, the chemical etching step S 160 according to the present embodiment is also implemented to remove the second shield layer 5 and the second sputtering conductor layer 3 so as to expose the second processing region 1321 in an external space.In summary, the manufacturing method S 100 provided by the present embodiment includes only a slight lateral etching on the first sputtering layout segment 21 at the chemical etching step S 160 so that the pattern accuracy of the first thin circuit layer C 1 is not impaired to prevent an electrical short circuit from occurring at the first thin circuit layer C 1. Accordingly, the first thick circuit layer 111 and the first thin circuit layer C 1 can be accurately formed to meet various requirements by implementing the above steps S 110-S 160.Specifically, the first thin circuit layer C 1 according to the present embodiment includes a plurality of circuits C 11. After the shielding step S 140 (illustrated in FIG. 5 ), the electroplating step S 150 (illustrated in FIG. 6 ), and the chemical etching step S 160 (illustrated in FIG. 7 ) are implemented, a distance G between any two circuits C 11 adjacent to each other or a width W of any one circuit C 11 has the lowest critical value (or a minimum value) that is within a range of 30 μm to 60 μm. In other words, the lowest critical value of the pitch G or the width W in the first thin circuit layer C 1 can be accurately kept in a range of 30 μm to 60 μm according to the design requirements, but the present disclosure is not limited thereto.In the above, the manufacturing method S 100 provided by the present embodiment has been described, and below, the circuit board structure 100 manufactured by implementing the manufacturing method S 100 will be substantially described. Accordingly, for brevity, in some features of the circuit board structure 100, reference may be made to the above description of the manufacturing method S 100, but the present disclosure is not limited thereto.The circuit board structure 100 according to the present embodiment includes the ceramic board 13, the first thick circuit layer 111 formed on the first surface 131 of the ceramic board 13, the first thin circuit layer C 1 formed on the first surface 131 of the ceramic board 13, and the second thick circuit layer 121 formed on the second surface 132 of the ceramic board 13. The thickness of the first thick circuit layer 111 and the thickness of the second thick circuit layer 121 are the same and may be each greater than or equal to 200 μm, but the present disclosure is not limited thereto.According to the present embodiment, the first thick circuit layer 111 and the second thick circuit layer 121 are sintered and fixed to the first surface 131 and the second surface 132 of the ceramic plate 13, respectively (via the two connection layers 14). Alternatively, the first thick circuit layer 111 and the second thick circuit layer 121 are soldered and fixed to the first surface 131 and the second surface 132 of the ceramic plate 13, respectively (via the two connection layers 14).In particular, the first processing region 1311 of the first surface 131 is not covered by the first thick circuit layer 111 and is not connected to the corresponding connection layer 14, and the second processing region 1321 of the second surface 132 is not covered by the second thick circuit layer 121 and is not connected to the corresponding connection layer 14.Moreover, the first thin circuit layer C 1 is formed on the first processing region 1311 of the first surface 131 and spaced apart from the first thick circuit layer 111, and the second processing region 1321 of the second surface 132 according to the present embodiment is provided without any circuit formed thereon. The first thin circuit layer C 1 includes a plurality of circuits C 11, and the distance G between any two adjacent circuits C 11 or the width W of any circuit C 11 may be formed such that the lowest critical value is within a range of 30 μm to 60 μm.Specifically, the first thin circuit layer C 1 according to the present embodiment includes the first sputtering layout segment 21 connected to the first surface 131 and the first plating layer 6 connected to the first sputtering layout segment 21, and the first plating layer 6 and the first sputtering layout segment 21 are each made of different materials. The thickness of the first thin circuit layer C 1 is in a range of 1 μm to 150 μm, and the thickness of the first sputtering layout segment 21 is in a range of 0.1 μm to 1 μm.Moreover, the circuit board structure 100 has been described above with reference to FIG. 7, but the circuit board structure 100 may be adjusted or changed according to design requirements. For example, as illustrated in FIGS. 8 to 10, the second thick circuit layer 121 may be a structure having no pattern, and the first thin circuit layer C 1 is disposed on a projection region defined by orthogonally projecting the second thick circuit layer 121 onto the first surface 131.Moreover, as illustrated in FIG. 9, the circuit board structure 100 includes a lateral connection portion C 4 formed on the first surface 131. The lateral connection portion C 4 is connected between the first thick circuit layer 111 and the first thin circuit layer C 1. Moreover, the thickness of the side connection portion C 4 gradually decreases in the direction from the thick circuit layer 111 to the thin circuit layer C 1. In other words, the cross section of the lateral connection portion C 4 is substantially in the shape of a triangle.Alternatively, as illustrated in FIG. 10, the circuit board structure 100 includes two lateral connection portions C 4 formed on the first surface 131. Each of the two lateral connection portions C 4 is connected between the first thick circuit layer 111 and the first thin circuit layer C 1. In other words, the two lateral connection portions C 4 are respectively connected to two opposite sides of the first thick circuit layer 111 and respectively connected to two of the circuits C 11 of the first thin circuit layer C 1 disposed adjacent to the first thick circuit layer 111.Moreover, the thickness of each of the two lateral connection portions C 4 gradually decreases in the direction from the thick circuit layer 111 to the thin circuit layer C 1. In other words, the cross section of each of the two side connection portions C 4 is substantially in the shape of a triangle, and a corresponding one of the two connection layers 14 is embedded in the two side connection portions C 4 and the first thick circuit layer 111.[Second Embodiment]In FIG. 11, a second embodiment of the present disclosure similar to the first embodiment of the present disclosure is provided. For brevity, the description of the same components in the first and second embodiments of the present disclosure will be omitted here, and the following description only discloses the features different from the first and second embodiments.According to the present embodiment, the circuit board structure 100 is not provided with the first plating layer, and the first sputtering layout segment 21 is defined as the sputtering circuit layer C 3. In other words, the sputtering circuit layer C 3 of the circuit board structure 100 according to the present embodiment is formed on the first processing region 1311 of the first surface 131, and the thickness of the sputtering circuit layer C 3 is in a range of 0.1 μm to 1 μm.[Third Embodiment]Referring to FIGS. 12 to 14, a third embodiment of the present disclosure similar to the first embodiment of the present disclosure is provided. For brevity, the description of the same components in the first and third embodiments of the present disclosure (e.g., the preparation step, the patterning step, and the sputtering step) is omitted here, and the following description discloses only the features different between the first and third embodiments.As illustrated in FIG. 12, the shielding step S 140 according to the present disclosure is implemented by forming a first shielding layer 4 on the first sputtering conductor layer 2 and forming a second shielding layer 5 on the second sputtering conductor layer 3. The first shield layer 4 has a first patterned trench 41, and a part of the first sputtering conductor layer 2 is exposed from the first shield layer 4 through the first patterned trench 41 and is defined as a first sputtering layout segment 21. Moreover, the second shield layer 5 has a second patterned trench 51, and a part of the second sputtering conductor layer 3 is exposed from the second shield layer 5 through the second patterned trench 51 and is defined as the second sputtering layout segment 31, but the present disclosure is not limited thereto.As illustrated in FIGS. 12 and 13, the electroplating step S 150 is implemented by electroplating the first sputter layout segment 21 of the first sputter conductor layer 2 and the second sputter layout segment 31 of the second sputter conductor layer 3 to form a first electroplating layer 6 connected to the first sputter layout segment 21 and a second electroplating layer 7 connected to the second sputter layout segment 31, respectively. According to the present embodiment, the first plating layer 6 and the second plating layer 7 are made of the same material different from the material of the first sputtering layout segment 21, but the present disclosure is not limited thereto.As illustrated in FIGS. 13 and 14, the chemical etching step S 160 is implemented by removing the first shielding layer 4 and another part of the first sputtering conductor layer 2 connected (or shielded) to the first shielding layer 2 so that the first plating layer 6 and the first sputtering layout segment 21 collectively defined as a first thin circuit layer C 1 are maintained, and is further implemented by removing the second shielding layer 5 and another part of the second sputtering conductor layer 3 connected (or shielded) to the second shielding layer 3 so that the second plating layer 7 and the second sputtering layout segment 31 collectively defined as a second thin circuit layer C 2 are maintained.[Fourth Embodiment]Referring to FIG. 15, a fourth embodiment of the present disclosure similar to the third embodiment of the present disclosure is provided. For brevity, the description of the same components in the third and fourth embodiments of the present disclosure will be omitted here, and the following description only discloses the features different from the third and fourth embodiments.According to the present embodiment, the circuit board structure 100 is formed without the second plating layer, and the second sputtering layout segment 31 is defined as the sputtering circuit layer C 3. In other words, the sputtering circuit layer C 3 of the circuit board structure 100 according to the present embodiment is formed on the second processing region 1321 of the second surface 132, and the thickness of the sputtering circuit layer C 3 is in a range of 0.1 μm to 1 μm.Accordingly, the circuit board structure 100 according to the present embodiment can be provided with three kinds of metal circuits (for example, the first thick circuit layer 111 formed by sintering or soldering, the first thin circuit layer C 1 formed by sputtering or electroplating, and the sputtering circuit layer C 3 formed by sputtering), thereby satisfying various practical requirements.[Advantageous Effects of Embodiments]Finally, it should be noted that each of the manufacturing methods and each of the circuit board structures provided by the present disclosure only have a slight side etching on the first sputtering layout segment (or the sputtering circuit layer) through the steps and the configuration thereof, so that the pattern accuracy of the first thin circuit layer (or the sputtering circuit layer) is not impaired to prevent the first thin circuit layer (or the sputtering circuit layer) from generating an electrical short circuit. Accordingly, the first thick circuit layer and the first thin circuit layer (or the sputtering circuit layer) can be accurately formed by implementing the above steps to meet various requirements.The foregoing description of the exemplary embodiments of the disclosure has been presented for purposes of illustration and description only and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings.The embodiments were chosen and described in order to explain the principles of the disclosure and its practical application, to thereby enable others skilled in the art to utilize the disclosure and various embodiments with various modifications as are suited to the particular use contemplated. Alternative embodiments will be apparent to those skilled in the art to which the present disclosure pertains without departing from its spirit and scope.List of reference characters100 Circuit board structure 1 metallized ceramic substrate 11 first metal layer 111 first thick circuit layer 12 second metal layer 121 second thick circuit layer 13 ceramic plate 131 first surface 1311 first processing region 132 second surface 1321 second processing region 14 connection layer 2 first sputtering conductor layer 21 first sputtering layout segment 3 second sputtering conductor layer 31 second sputtering layout segment 4 first shielding layer 41 first patterned trench 5 second shielding layer 51 second patterned trench 6 first plating layer 7 second plating layer C 1 first thin circuit layer C 11 circuit C 1 second thin circuit layer C 3 sputtering circuit layer C 4 lateral connection portion G distance W width S 100 manufacturing method S 110 preparation step S 120 patterning step S 130 sputtering step S 140 shielding step s 150 Plating step S 160 Chemical etching step

Claims

A method for manufacturing a printed circuit board structure (100), comprising: • a preparation step implemented by providing a metallized ceramic substrate (1), the metallized ceramic substrate (1) comprising: ▪ a ceramic plate (13) having a first surface (131) and a second surface (132) opposite to the first surface (131), and ▪ a first metal layer (11) and a second metal layer (12) formed on the first surface (131) and the second surface (132) of the ceramic plate (13), respectively; • a patterning step implemented by patterning the first metal layer (11) to remove a part of the first metal layer (11) to form a first thick circuit layer (111), wherein the thickness of the first thick circuit layer (111) is greater than or equal to 200 μm, and wherein a part of the first surface (131) is exposed from the first thick circuit layer (111) and defined as a first processing region (1311), • a sputtering step implemented by sputtering the first processing region (1311) of the ceramic plate (13) to form a first sputtering conductor layer (2), • a shielding step implemented by forming a first shielding layer (4) on the first sputtering conductor layer (2), wherein the first shielding layer (4) has a first patterned trench (41) and a part of the first sputtering conductor layer (2) is exposed from the first shielding layer (4) through the first patterned trench (41) and defined as a first sputtering layout segment (21), • a plating step, the chemical etching implemented by electroplating the first sputter layout segment (21) of the first sputter conductor layer (2) to form a first electroplating layer (6) connected to the first sputter layout segment (21), and • a chemical etching step implemented by removing the first shield layer (4) and another part of the first sputter conductor layer (2) connected to the first shield layer (4) so that the first electroplating layer (6) and the first sputter layout segment (21) collectively defined as a first thin circuit layer (C1) are maintained, wherein the thickness of the first thin circuit layer (C1) is in a range of 1 μm to 150 μm.The manufacturing method according to claim 1, wherein the first thin circuit layer (C1) includes a plurality of circuits (C11), and after the shielding step, the electroplating step, and the chemical etching step are performed, the distance (G) between any two circuits (C11) adjacent to each other or the width (W) of any one circuit (C11) has the lowest critical value within a range of 30 μm to 60 μm.The manufacturing method according to claim 1 or 2, wherein the thickness of the first sputter layout segment (21) is in a range of 0.1 μm to 1 μm, and wherein the material of the first electroplating layer (6) is different from the material of the first sputter layout segment (21), so that the first electroplating layer (6) does not have a side etching in the chemical etching step.The manufacturing method according to any one of claims 1 to 3, wherein in the patterning step, the second metal layer (12) is patterned by removing a part thereof to form a second thick circuit layer (121) having a thickness of greater than or equal to 200 μm.The manufacturing method according to claim 4, wherein in the patterning step, a part of the second surface (132) is exposed from the second thick circuit layer (121) and is defined as a second processing region (1321), wherein in the sputtering step, the second processing region (1321) is sputtered to form a second sputtering conductor layer (3), and wherein in the shielding step, a second shielding layer (5) is formed on the second sputtering conductor layer (3).The manufacturing method according to claim 4 or 5, wherein in the chemical etching step, the second shield layer (5) and the second sputtering conductor layer (3) are removed, and the second processing region (1321) is exposed in an external space.The manufacturing method according to any one of claims 4 to 6, wherein in the shielding step, the second shielding layer (5) has a second patterned trench (51), and a part of the second sputtering conductor layer (3) is exposed from the second shielding layer (5) through the second patterned trench (51) and is defined as a second sputtering layout segment (31), wherein in the electroplating step, the second sputtering layout segment (31) is electroplated to form a second electroplating layer (7) connected thereto, and wherein in the chemical etching step, the second shielding layer (5) and another part of the second sputtering conductor layer (3) connected to the second shielding layer (5) are removed so that the second electroplating layer (7) and the second sputtering layout segment (31) are removed, which are collectively defined as a second thin circuit layer (C2) are retained.The manufacturing method according to any one of claims 1 to 7, wherein in the preparing step, the metallized ceramic substrate (1) is a directly bonded copper ceramic substrate (DBC), and the first metal layer (11) and the second metal layer (12) are sintered on the first surface (131) and the second surface (132) of the ceramic plate (13), respectively.The manufacturing method according to any one of claims 1 to 8, wherein in the preparing step, the metallized ceramic substrate (1) is an active solder (AMB) ceramic substrate, and the first metal layer (11) and the second metal layer (12) are soldered to the first surface (131) and the second surface (132) of the ceramic plate (13), respectively.A printed circuit board structure (100) comprising: • a ceramic board (13) having a first surface (131) and a second surface (132) opposite to the first surface (131), • a first thick circuit layer (111) formed on the first surface (131) of the ceramic board (13) and having a thickness of greater than or equal to 200 μm, wherein a part of the first surface (131) is exposed from the first thick circuit layer (111) and is defined as a first processing region (1311); • a first thin circuit layer (C1) formed on the first processing region (1311) of the first surface (131) and having a thickness in a range from 1 μm to 150 μm, • wherein the first thin circuit layer (C1) comprises a first sputtering layout segment (21) connected to the first surface (131) and a first electroplating layer (6) connected to the first sputtering layout segment (21), wherein the first electroplating layer (6) and the first sputtering layout segment (21) are each made of different materials.The printed circuit board structure (100) of claim 10, wherein the first thick circuit layer (111) and the first thin circuit layer (C1) are spaced apart from each other.The circuit board structure (100) according to claim 10 or 11, further comprising at least one lateral connection portion (C4) formed on the first surface (131), wherein the at least one lateral connection portion (C4) is connected between the first thick circuit layer (111) and the first thin circuit layer (C1).The printed circuit board structure (100) according to claim 12, wherein the thickness of the at least one lateral connection portion (C4) gradually decreases in the direction from the thick circuit layer (111) to the thin circuit layer (C1).The circuit board structure (100) according to any one of claims 10 to 13, further comprising a second thick circuit layer (121) formed on the second surface (132) of the ceramic board (13), wherein the thickness of the second thick circuit layer (121) is equal to or greater than 200 μm.The printed circuit board structure (100) of claim 14, wherein a portion of the second surface (132) is exposed from the second thick circuit layer (121) and is defined as a second processing region (1321), and wherein the printed circuit board structure (100) further comprises a sputtering circuit layer (C3) formed on the second processing region (1321) and having a thickness in a range of 0.1 μm to 1 μm.The circuit board structure (100) according to claim 14 or 15, wherein the first thick circuit layer (111) and the second thick circuit layer (121) are sintered on the first surface (131) and the second surface (132) of the ceramic board (13), respectively.The circuit board structure (100) according to any one of claims 14 to 16, wherein the first thick circuit layer (111) and the second thick circuit layer (121) are soldered to the first surface (131) and the second surface (132) of the ceramic board (13), respectively.The circuit board structure (100) according to any one of claims 14 to 17, wherein the first thin circuit layer (C1) is disposed on a projection area defined by orthogonally projecting the second thick circuit layer (121) onto the first surface (131).The circuit board structure according to any one of claims 10 to 18, wherein the first thin circuit layer (C1) includes a plurality of circuits (C11), and the distance (G) between any two circuits (C11) adjacent to each other or the width (W) of any circuit (C11) has the lowest critical value within a range of 30 μm to 60 μm.A printed circuit board structure (100) comprising: • a ceramic board (13) having a first surface (131) and a second surface (132) opposite to the first surface (131), • a first thick circuit layer (111) formed on the first surface (131) of the ceramic board (13) and having a thickness of greater than or equal to 200 μm, wherein a part of the first surface (131) is exposed from the first thick circuit layer (111) and defined as a first processing region (1311); and • a sputtering circuit layer (C3) formed on the first processing region (1311) of the first surface (131) and having a thickness in a range of 0.1 μm to 1 μm.

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