SiC epitaxy wafer and method for its production

Abstract

SiC epitaxy wafer, with: a SiC single-crystal substrate whose main surface has an offset angle of 0.4° to 5° with respect to a (0001) plane; and an epitaxial layer provided on the SiC single crystal substrate, wherein in the epitaxial layer a basal plane dislocation density of basal plane dislocations extending from the SiC single crystal substrate to an outer surface, 0.1 dislocations / cm² 2 or less, and a defect density caused by Si droplets of 0.1 defects / cm² 2 or less wherein the defects caused by the Si droplets are scattered depressions and / or cluster defects in which depressions are arranged in a direction perpendicular to an offset direction in an in-plane direction of the SiC single crystal substrate.

Description

TECHNICAL AREA

[0001] The present invention relates to a SiC epitaxial wafer and a method for producing the same. BACKGROUND TECHNOLOGY

[0002] Silicon carbide (SiC) exhibits properties such as an order of magnitude higher dielectric breakdown field strength, a three times larger band gap, and approximately three times higher thermal conductivity than silicon (Si). Therefore, silicon carbide (SiC) is expected to be used in power supplies, high-frequency devices, high-temperature operating devices, and the like.

[0003] To promote the practical application of SiC devices, techniques for high-quality epitaxial growth and high-quality SiC epitaxial wafers must be established.

[0004] A SiC device is manufactured using a SiC epitaxial wafer, wherein an epitaxial layer (film), which is an active region of the device, is grown by a chemical vapor deposition (CVD) method or the like on a SiC single crystal substrate obtained by processing a SiC bulk single crystal grown by a sublimation recrystallization method.

[0005] More specifically, a 4H epitaxial layer is grown by performing step flow growth (lateral growth from one atomic step) on the SiC single crystal substrate, using a plane thereof having an offset angle in the <11-20> direction from the (0001) plane as the growth surface.

[0006] In SiC epitaxial wafers, a basal plane dislocation (BPD) is referred to as a device killer defect, which causes a fatal defect in the SiC device.

[0007] Most basal plane dislocations in the SiC single-crystal substrate are transformed into threading edge dislocations (TED) during the formation of the epitaxial layer. On the other hand, a portion of the basal plane dislocations extending from the SiC single-crystal substrate to the epitaxial layer leads to a device killer defect.

[0008] Therefore, studies are being conducted to reduce the ratio of basal plane dislocations extending from the SiC single crystal substrate to the epitaxial layer and to reduce device killer defects.

[0009] For example, Patent Document 1 discloses that a basal plane dislocation density of 10 dislocations / cm 2or less can be achieved in a 7.62 cm (3-inch) SiC epitaxial wafer when a thermal stress is applied to change the migration of atoms adhering to a SiC single crystal substrate by controlling the temperature in a crystal growth process.

[0010] Furthermore, for example, Patent Document 2 discloses that a basal plane dislocation density of 10 dislocations / cm 2 or less in a SiC epitaxial wafer by controlling parameters such as reactant concentration, pressure, temperature, gas flow and the like of CVD in a crystal growth process.

[0011] Furthermore, for example, Non-Patent Document 1 discloses that by setting the growth rate of an epitaxial layer to 50 µm / h, it is possible to reduce the proportion of BPDs transferred from the SiC single-crystal substrate to the epitaxial layer to 1%. According to the current state of the art, the density of basal plane dislocations on the surface of a 15.24 cm (6-inch) SiC single-crystal substrate is about 100 to 5000 dislocations / cm 2 For this reason, setting the proportion to 1% means that 10 to 50 basal plane dislocations / cm 2 generated on the surface of the SiC epitaxial wafer.

[0012] In step-flow growth, it is known that when an impurity such as a two-dimensional nucleus is formed on a terrace, the lateral growth of atomic steps is disrupted and crystal defects are generated. Patent Document 3 proposes a method for promoting the decomposition and reevaporation of a two-dimensional nucleus by including a step of changing the conditions to decompose and reevaporate SiC. Furthermore, Patent Document 3 discloses that the adhesion of Si droplets (silicon droplets) is considered to be the cause of an abnormal high-density growth nucleus. Non-Patent Document 2 investigates conditions under which epitaxial growth with a mirror surface at a high growth rate is obtained, and it is described that there is a narrow range of conditions of the C / Si ratio at the high growth rate at which the mirror surface is obtained.

[0013] DE 11 2017 006 777 T5 is state of the art with regard to novelty according to Section 3(2) of the Patent Act and discloses SiC substrates provided with an epitaxial layer of SiC, which have an offset angle of 0.4°-5° with respect to the (0001) plane, as well as SiC wafers which have a basal plane dislocation density of 0.1 cm -2 or less and a density of intrinsic 3C triangular defects of 0.1 cm or less -2 have.

[0014] WO 2013 / 115711 A2 and US 2015 / 0380243 A1 disclose methods for producing SiC wafers with epitaxially deposited SiC layer. Citation listPatent literature Patent Document 1: Japanese Unexamined Patent Application, First Publication JP 2011-219299 A Patent Document 2: Japanese translation JP 2015-521378 A of PCT International Publication WO 2014 / 043 104 A1 Patent Document 3: Japanese Unexamined Patent Application, First Publication JP 2011-219298 A Non-patent literature

[0015] Non-Patent Document 1: T. Hori, K. Dannno, and T. Kimoto. Journal of Crystal Growth, 306 (2007), 297-302.

[0016] Non-Patent Document 2: Y. Ishida, T. Takahashi, K. Kojima et. al. Materials Science Forum Vol. 457-460 (2004) pp. 213-216. DISCLOSURE OF THE INVENTIONTechnical Problem

[0017] In recent years, efforts have been made to increase the number of SiC devices obtained from an epitaxial wafer and reduce manufacturing costs by increasing the size of epitaxial SiC wafers to 15.24 cm (6 inches) or larger. Accordingly, there is a demand for low basal plane dislocation density even in large SiC epitaxial wafers of 15.24 cm (6 inches) or larger.

[0018] However, each of the SiC epitaxial wafers disclosed in the above patent documents has a SiC epitaxial wafer size of 15.24 cm (6 inches) or less. If the above-described conditions are simply applied to the 15.24 cm (6 inches) size, the film formation conditions in one plane of the SiC single-crystal substrate vary due to the large substrate area. Therefore, the same result as with 10.16 cm (4 inches) is not achieved.

[0019] To further increase the growth rate, it is necessary to supply a large amount of silicon raw material, which easily generates Si droplets. Therefore, at a high growth rate, a localized silicon-excess region may be formed even if the abnormal high-density growth nuclei disclosed in Patent Document 3 are not formed. This causes Si droplets to be generated on a growth surface, and defects caused by Si droplets are formed. In recent years, there has been a demand for high-quality epitaxial wafers. Therefore, such defects must be reduced, even though the defects are caused by local Si droplets, which are micro-defects. Furthermore, basal plane dislocations, which are device-killer defects, must be removed as much as possible from the epitaxial layer.

[0020] The present invention was made in view of the above-mentioned problems. An object of the present invention is to obtain a SiC epitaxial wafer having fewer basal plane dislocations that lead to device killer defects and fewer defects caused by Si droplets, and a method for producing the same. Solution to the problem

[0021] As a result of intensive studies, the inventors of the present invention found that under epitaxial growth conditions at high growth rate, a SiC epitaxial wafer can be obtained having a small number of basal plane dislocations and a small number of defects caused by Si droplets by maintaining a constant C / Si ratio and increasing the Cl / Si ratio.

[0022] Accordingly, the present invention provides the following means to solve the above-mentioned problems.

[0023] (1) A SiC epitaxial wafer according to a first aspect includes a SiC single crystal substrate whose main surface has an off-angle of 0.4° to 5° with respect to the (0001) plane; and an epitaxial layer provided on the SiC single crystal substrate, wherein, in the epitaxial layer, a basal plane dislocation density of basal plane dislocations extending from the SiC single crystal substrate to an outer surface is 0.1 dislocations / cm 2 or less and a defect density caused by Si droplets of 0.1 defects / cm 2or less, wherein the defects caused by the Si droplets are scattered pits and / or collective defects in which pits are arranged in a direction perpendicular to an offset direction in an in-plane direction of the SiC single crystal substrate.

[0024] (2) In the SiC epitaxial wafer according to the above aspect, the defect density caused by Si droplets can be zero defects / cm 2 be.

[0025] (3) In the SiC epitaxial wafer according to the above aspects, the total basal plane dislocation density of the basal plane dislocations extending from the SiC single crystal substrate to the outer surface and of basal plane dislocations converted into threading edge dislocations in the epitaxial layer can be 0.1 dislocations / cm 2 or less.

[0026] (4) In the SiC epitaxial wafer according to the above aspects, the diameter of the SiC single crystal substrate may be 150 mm or more.

[0027] (5) A method for producing a SiC epitaxial wafer according to the present invention, in which crystal growth of an epitaxial layer is performed on a SiC single crystal substrate whose main surface has an offset angle of 0.4 to 5° with respect to the (0001) plane, includes an epitaxial growth step of growing the epitaxial layer on the SiC single crystal substrate by supplying a Si-based raw material gas, a C-based raw material gas, and a gas containing a Cl element to a surface of the SiC single crystal substrate, the epitaxial growth step being performed under growth conditions in which the film deposition pressure is 4000 Pa (30 Torr) or less, the Cl / Si ratio is in a range of 8 to 12, the C / Si ratio is in a range of 0.8 to 1.2, and the growth rate from the initial stage of growth is 50 µm / h or more.

[0028] The method for producing a SiC epitaxial wafer according to the second aspect of the present invention preferably includes the following features. It is further preferable that the following features be combined. (6) In the method for producing a SiC epitaxial wafer according to the present invention, the method may further include a cleaning step of cleaning the surface of the SiC single-crystal substrate before the epitaxial growth step by heating the surface to 1550°C to 1650°C in a hydrogen atmosphere under a pressure of 4000 Pa (30 Torr) or less.

[0029] (7) In the method for producing a SiC epitaxial wafer according to the present invention, the gas containing the Cl element may also serve as the Si-based raw material gas. Advantageous effects of the invention

[0030] The SiC epitaxial wafer of the present invention can achieve a low defect density in the basal plane dislocation, which has a significant influence on the device operation of the SiC device, as well as a high yield and quality of the devices. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a schematic cross-sectional view of a SiC epitaxial wafer illustrating a basal plane dislocation and a threading edge dislocation. Fig. Figure 2A is a schematic representation of the behavior of dislocations at the interface between a SiC single crystal substrate and an epitaxial layer and within the epitaxial layer. Fig. Figure 2B is a schematic representation of the behavior of dislocations at the interface between the SiC single crystal substrate and the epitaxial layer and within the epitaxial layer. Fig.Figure 2C is a schematic representation of the behavior of dislocations at the interface between the SiC single crystal substrate and the epitaxial layer and within the epitaxial layer. Fig. Figure 3A is a confocal differential interference contrast microscopy image of an epitaxial wafer surface when the growth pressure is changed in an epitaxial SiC growth step. Fig. Figure 3B is a confocal differential interference contrast microscopy image of the epitaxial wafer surface when the growth pressure is changed in the epitaxial SiC growth step. Fig. Figure 3C is a confocal differential interference contrast microscopy image of the epitaxial wafer surface when the growth pressure is changed in the epitaxial SiC growth step. Fig.3D is a confocal differential interference contrast microscopy image of the epitaxial wafer surface when the growth pressure is changed in the epitaxial SiC growth step. Fig. Figure 4A is a confocal differential interference contrast microscopy image of the epitaxial wafer surface when the growth rate is changed in the epitaxial SiC growth step. Fig. Figure 4B is a confocal differential interference contrast microscopy image of the epitaxial wafer surface when the growth rate is changed in the epitaxial SiC growth step. Fig. Figure 5A is a confocal differential interference contrast microscopy image of the epitaxial wafer surface when the Cl / Si ratio is changed in the SiC epitaxial growth step. Fig.Figure 5B is a confocal differential interference contrast microscopy image of the epitaxial wafer surface when the Cl / Si ratio is changed in the SiC epitaxial growth step. Fig. Figure 5C is a confocal differential interference contrast microscopy image of the epitaxial wafer surface when the Cl / Si ratio is changed in the SiC epitaxial growth step. BEST MODE FOR CARRYING OUT THE INVENTION

[0031] Hereinafter, a SiC epitaxial wafer and a method for manufacturing the SiC epitaxial wafer according to the present embodiment will be described in detail, with reference to the drawings where necessary. In the drawings used in the following description, in order to better understand the features of the present invention, portions containing the features may be enlarged for clarity. The dimensions and proportions of each component may be the same as or different from the actual dimensions. The materials, dimensions, positions, and the like illustrated in the following description are examples. The present invention is not limited to this and can be practiced with appropriate modifications within a range that does not change the spirit of the invention. (Basal plane dislocation (BPD) and edge dislocation or threading edge dislocation (TED))

[0032] Fig.Figure 1 is a schematic cross-sectional view of a SiC epitaxial wafer for explaining a basal plane dislocation and an edge dislocation.

[0033] One in Fig. The SiC epitaxial wafer 10 shown in Figure 1 has an epitaxial layer 2 arranged on a SiC single crystal substrate 1.

[0034] A basal plane dislocation (BPD) 1A exists in the SiC single crystal substrate 1. The basal plane dislocation literally means a dislocation that exists in the (0001) plane (c-plane), which is a basal plane of a SiC single crystal. Generally, the SiC single crystal substrate 1 has a surface with an offset angle in the <11-20> direction of (0001) as the growth surface 1a. Therefore, the basal plane dislocation 1A is in Fig. 1 inclined with respect to the growth surface 1a.

[0035] The basal plane dislocation 1A in the SiC single crystal substrate 1 affects the epitaxial layer 2 when the layer is epitaxially grown, and the dislocation in the epitaxial layer 2 exhibits the following three behaviors. Fig. 2A to 2C are views schematically showing the behavior of dislocations at an interface between the SiC single crystal substrate 1 and the epitaxial layer 2 and within the epitaxial layer 2.

[0036] A first behavior, as in Fig. 2A is a behavior in which the basal plane dislocation 1A is converted into an edge dislocation (TED) 2B at the interface between the basal plane dislocation 1A and the epitaxial layer 2.

[0037] A second behavior, as in Fig.2B is a behavior in which the basal plane dislocation 1A continues unchanged to the epitaxial layer 2. The dislocation that continues into the epitaxial layer 2 becomes a basal plane dislocation 2A.

[0038] A third behavior, as in Fig. 2C is a behavior in which the basal plane dislocation 2A is transformed into the edge dislocation 2B within the epitaxial layer 2.

[0039] The basal plane dislocation and the edge dislocation share the same Burgers vector and are interconvertible. An edge dislocation is a crystal defect in which the Burgers vector, which indicates the direction of displacement of the crystal, is orthogonal to a dislocation line. The shape of the crystal defect is one in which an additional atomic plane is inserted into a perfect crystal surface in the shape of a blade.

[0040] The basal plane dislocation in the epitaxial layer has a negative impact on the SiC device. For example, when a forward current flows in a bipolar device with a basal plane dislocation, defects expand to form Shockley stacking faults, thus degrading the device's forward-biased properties.

[0041] Therefore, the first behavior of three in Fig. 2A has the least influence on the SiC component. On the other hand, the second behavior of three in Fig. 2B has the greatest influence on the SiC component.

[0042] In the case of the third, in Fig. 2C, the effect on the component is compared to the case in Fig.2B is limited, but it is better that the effect be as small as possible, and even better if there is no effect. If the epitaxial growth layer is sufficiently thick, recombination will not occur at a portion where the basal plane dislocation 2A exists in the epitaxial layer 2. This reduces the possibility of the basal plane dislocation being converted into a stacking fault. However, if the epitaxial layer 2 is thick, the on-resistance of the device will become high. Therefore, the epitaxial layer 2 is designed to have a thickness required for designing the withstand voltage and to be as thin as possible.Therefore, in order to avoid deterioration of the device characteristics at high current conduction caused by the stacking faults resulting from the basal plane dislocations 2A remaining in the epitaxial layer 2, it is preferable that there are few basal plane dislocations 2A during epitaxial growth, and better still, that there are no basal plane dislocations.

[0043] As described above, in order to avoid effects on the SiC device, it is necessary to perform a process for forming the epitaxial layer 2 to convert the basal plane dislocations 1A in the SiC single crystal substrate 1 into the edge dislocations 2B with high efficiency. As the timing for converting the basal plane dislocation into the edge dislocation, it is preferable to perform the following steps: Fig.2A, the basal plane dislocation at the interface between the SiC single crystal substrate 1 and the epitaxial layer 2 is converted into the edge dislocation 2B. It is necessary to prevent the basal plane dislocation from being converted into the edge dislocation 2B within the epitaxial layer 2, as shown in Fig. 2C.

[0044] The basal plane dislocations 2A and the edge dislocations 2B can be identified from the shape of pits created by selectively etching a surface and from dislocation images obtained by X-ray topography. Furthermore, detection can be performed using a photoluminescence image obtained based on the photoluminescence light generated by defects when the defects are irradiated with ultraviolet light. The basal plane dislocation 2A emits light with a wavelength of 700 nm or more when irradiated with ultraviolet light.

[0045] A position where the basal plane dislocation is converted into the edge dislocation can be confirmed by cutting the epitaxial layer in the thickness direction and determining the basal plane dislocation by selective etching or the like on the cut surface. (Defect caused by Si droplets)

[0046] For SiC growth, a Si source and a C source are added simultaneously. When Si is present in excess, Si droplets are generated because Si, which does not contribute to the growth, forms an aggregate. Furthermore, the Si droplets adhere to the growth surface, and the Si droplets aggregate on the growth surface. When the Si droplets are present in small quantities, this is not a problem, as the droplets re-evaporate after adhering. However, when the Si droplets are present in large quantities, the droplets hinder the progression of a step during step-flow growth. Before such re-evaporation occurs, the droplets are introduced into the film. As a result, the intercalated Si droplets cause defect formation.

[0047] Defects caused by Si droplets are divided into two types based on their appearance: one is scattered pits, and the other is linear defects. Defects with a linear shape are considered cluster defects, in which pits are arranged in a line. Therefore, the distinction between scattered and clustered pits is confirmed only by their external appearance, and both are formed by Si droplets.

[0048] The defects caused by Si droplets arise from excess Si in the growth atmosphere. Accordingly, defect formation can be suppressed by maintaining a high C / Si ratio in the raw material gas. However, the C / Si ratio also affects other properties. Therefore, to obtain a SiC epitaxial layer that can be used in a device, the C / Si ratio must be adjusted within a specific range for aspects other than Si droplets.

[0049] Therefore, when investigating parameters that can suppress defects caused by Si droplets, apart from the C / Si ratio, one parameter identified was the film formation pressure during epitaxial growth. Qualitatively speaking, at low growth pressures, the Si droplets adhering to the substrate evaporate, making it difficult to form pits. Fig.3A to 3D are views showing examples of defects caused by Si droplets present on the surface of SiC epitaxial wafers produced by changing the film-forming pressure during growth with other conditions kept the same, and observed with a differential interference contrast confocal optical surface inspection device.

[0050] Fig. Figure 3A shows a case where the growth pressure is 26,664 Pa (200 Torr) and the defects (pits) caused by Si droplets are formed. Fig.In Figure 3A, the area surrounding the pits is enclosed by a dashed line due to their difficulty in detecting them. Although threading screw dislocations and threading edge dislocations also cause small pits, the positions of the threading dislocations and edge dislocations can be identified by selective etching, X-ray topography, or the like, so that these small pits can be distinguished from the pits caused by Si droplets. As shown in Fig. As shown in Figure 3A, under high pressure conditions during film formation (Si droplets are likely to be generated), the number of pits caused by Si droplets is large, and the pits are also formed in a central portion of the wafer. Each of the pits caused by Si droplets is isolated.

[0051] Fig.Figure 3B shows a result of the observation of defects caused by Si droplets when the growth pressure is reduced to 13 332 Pa (100 Torr). Fig. 3B, the area surrounding the depressions is enclosed by a dashed line due to the difficulty of detecting the depressions. As in Fig. As shown in Figure 3B, the frequent occurrence of typical isolated pits caused by Si droplets was not observed, but it was confirmed that pits clustered locally, forming a cluster defect in which pits were arranged vertically. The cluster defect was particularly frequently formed at the outer periphery of the substrate.

[0052] Fig. Figure 3C shows a result of the observation of defects caused by Si droplets, where the growth pressure is reduced to 6 666 Pa (50 Torr). In Fig.3C, the area surrounding the depressions is enclosed by a dashed line due to the difficulty of detecting the depressions. As in Fig. As shown in Figure 3C, a collection defect was observed, characterized by the depressions being arranged vertically.

[0053] The density of the pits in the collection defect is reduced when the pressure is lowered.

[0054] Fig. Figure 3D shows the result of observing defects caused by Si droplets when the growth pressure is reduced to 3333 (25 Torr). Neither isolated pits nor a vertically arranged cluster defect are detected. If there is no cluster defect, the surface of the SiC epitaxial wafer is flat and difficult to focus on. Therefore, the part where impurities are located on a lower side of the photo was captured, and the surface was focused.

[0055] The collection defect with the feature that the depressions are arranged vertically can be found for the first time when the defects are focused on their shape and scanned with a high-resolution optical microscope. The reason why the typical depressions caused by the Si droplets are arranged vertically and remain at the end after the Si droplets are reduced can be understood as follows. The Si droplet is likely to form in a depressed portion on the epitaxial growth surface. In step-flow growth, there is an atomic step portion, and the atomic step portion is formed in a step-like manner. Therefore, the Si droplet is likely to move into the portion and adhere there. The atomic step exists in the in-plane direction orthogonal to an offset growth direction.Therefore, it is assumed that the Si droplets are easily dispersed and adhere in this direction, leading to a collection defect where the pits are vertically clustered. The direction in which the Si droplets are vertically arranged is the direction in which the step extends.

[0056] Defects caused by Si droplets include both isolated pits that appear when there are a relatively large number of defects, and cluster defects that appear when the defect formation is small and in which typical pits are arranged vertically. When counting defects, each of the isolated pits is counted as one defect, and the cluster defect in which the pits are arranged vertically is counted as a line of arranged pits, thus quantifying. Although the cluster defect can be counted as scattered pits depending on the measurement magnification, the cluster defects are determined according to whether the defects appear as a line when the defects are confirmed at a magnification of 50 times or more. An upper limit of the measurement magnification is suitably selected in a range of 1000 times or less.

[0057] Among parameters other than the C / Si ratio, one of the parameters that influences the formation of Si droplet-induced pits is the growth rate of the epitaxial layer. To reduce the proportion of BPDs propagating from the substrate to the epitaxial layer, it is better to increase the growth rate to a certain value or more. However, increasing the growth rate requires increasing the flow rate of the Si-based gas, which leads to a state where Si droplet-induced defects are likely to occur.

[0058] Fig. 4A to 4B are differential interference microscopy images of the surface of the SiC epitaxial layer at a growth rate set to 40 µm / h or a growth rate set to 68 µm / h, with other conditions being the same. Fig.4A, defects caused by thread dislocations are observed (in the area of ​​the dashed lines of Fig. 4A), however, defects caused by Si droplets are not observed. It is difficult to determine the defects caused by thread dislocations based on shape alone. Therefore, after taking an image, etching was performed to confirm the defects. On the other hand, when the growth rate is increased to 68 µm / h, as shown in Fig. 4B, the depressions caused by Si droplets are scattered (in the area of ​​the dashed lines in Fig. 4B).

[0059] Increasing the growth rate therefore causes the transformation of basal plane dislocations into threading edge dislocations. However, the growth rate must be reduced to suppress the defects caused by Si droplets. In other words, it is difficult to suppress defects caused by Si droplets under conditions of a high growth rate, which can reduce the basal plane dislocations.

[0060] As continued in Fig.As shown in Figure 2A, for the transformation of the basal plane dislocations 1A into edge dislocations 2B at the interface between the SiC single-crystal substrate 1 and the epitaxial layer 2, it is effective to increase the growth rate immediately after the start of epitaxial growth. However, in this case, a large amount of silicon raw materials is supplied immediately after the start of growth, so Si droplets tend to be easily formed. Therefore, if the transformation from the basal plane dislocations to edge dislocations is controlled, suppression of defects caused by Si droplets becomes more difficult.

[0061] To suppress the formation of defects caused by Si droplets under conditions where the C / Si ratio and growth rate are limited, parameters other than film formation pressure must be controlled during growth. One measure is to introduce a Cl-containing gas to the surface of the SiC single-crystal substrate along with the raw material gas. (Process for producing SiC epitaxial wafers)

[0062] A method for manufacturing a SiC epitaxial wafer 10 according to the present embodiment includes a step of performing crystal growth of an epitaxial layer 2 on a SiC single crystal substrate 1 in which a main surface has an offset angle of 0.4° to 5° with respect to the (0001) plane.

[0063] First, the SiC single-crystal substrate 1 is prepared. The methods for preparing the SiC single-crystal substrate 1 are not particularly limited.

[0064] For example, the SiC single crystal substrate can be obtained by cutting a SiC block obtained by a sublimation method or the like.

[0065] In the SiC single-crystal substrate 1, a basal plane dislocation 1A exists along the (0001) plane (c-plane). The number of basal plane dislocations 1A exposed on a growth surface 1a of the SiC single-crystal substrate 1 is preferably as small as possible, but is not particularly limited. According to the current state of the art, the number of basal plane dislocations 1A present on the surface (growth surface) of a 15.24 cm (6 inch) SiC single-crystal substrate 1 is approximately 1,000 to 5,000 per 1 cm 2 .

[0066] Subsequently, the epitaxial layer 2 is epitaxially grown on the SiC single-crystal substrate 1 to produce the SiC epitaxial wafer 10. The epitaxial layer 2 is obtained, for example, by step flow growth (lateral growth from an atomic step) on the growth surface 1a of the SiC single-crystal substrate 1 by a chemical vapor deposition (CVD) method or the like.

[0067] The epitaxial growth is performed by supplying a raw material gas, a Cl element-containing gas, a carrier gas, and a dopant gas onto the SiC single crystal substrate, which is kept at a high temperature.

[0068] The "raw material gas" is a gas that serves as a raw material for the formation of a SiC epitaxial film. It is generally divided into Si-based raw material gases, which contain Si in the molecule, and C-based raw material gases, which contain C in the molecule.

[0069] As the Si-based raw material gas, a well-known Si-based raw material gas can be used, for example, silane (SiH4). Furthermore, a chlorine-based gas (chloride-based material) containing a Si source and Cl with corrosive activity, such as dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), and tetrachlorosilane (SiCl4), can also be used. The C-based raw material gas can be optionally selected, and for example, propane (C3H8) or the like can be used.

[0070] The "Cl element-containing gas" refers to a gas that contains Cl as a component of the molecules that make up the gas. The Cl-containing gas can be optionally selected, and for example, hydrogen chloride (HCl), SiH2Cl2, SiHCl3, SiCl4, and the like can be mentioned as gases. SiH2Cl2, SiHCl3, and SiCl4 are also the aforementioned Si-based raw material gases. Among these gases, there are cases where the gas is both a "Cl element-containing gas" and a "Si-based raw material gas."

[0071] A "doping gas" is a gas containing an element that acts as a donor or acceptor. Nitrogen is used as a doping gas for the growth of N-type semiconductors, and trimethylaluminum (TMA) or triethylaluminum (TEA) is used for the growth of P-type semiconductors, and the like. The doping gas is usually supplied together with the raw material gas. Since the flow rate of the doping gas is generally low, unless otherwise specified, the doping gas flow is carried out simultaneously with the raw material gas flow, and the amount of the doping gas is appropriately adjusted.

[0072] Another gas that can be used is a carrier gas for transporting the gases into a reaction furnace. Inert hydrogen is the preferred carrier gas. An atmosphere, or film-forming atmosphere, refers to a gaseous state in a growth furnace. For this reason, the atmosphere can refer to a state containing hydrogen gas, but hydrogen does not directly influence an epitaxial growth reaction.

[0073] The C / Si ratio is the ratio of the flow rate of the C element to the flow rate of the Si element in the flowing raw material gas. In epitaxial growth, where normal doping is performed, the C / Si ratio is determined by the ratio of the raw material gases, since the amount of the element used as a dopant is smaller than the amount of Si and C.

[0074] The Cl / Si ratio is a ratio of the flow rate of the Cl element and the flow rate of the Si element contained in all growth gases.

[0075] As described above, the gas containing the Cl element can also serve as the Si raw material gas. In this case, the Cl element in the Si raw material gas is also present in the amount of Cl element contained in all gases used for growth. This is because the Cl-containing Si raw material gas decomposes at a high temperature corresponding to the epitaxial growth region, releasing the Cl element.

[0076] Once the C / Si ratio and the Cl / Si ratio are defined, all ratios of Si, C, and Cl are determined. Furthermore, when determining the C / Si ratio, the growth rate is determined based on the flow rates of Si and C. Therefore, when determining the growth rate, the C / Si ratio and the Cl / Si ratio define the conditions of the elements contributing to growth.

[0077] In the method for manufacturing the SiC epitaxial wafer according to the present embodiment, the C / Si ratio, the Cl / Si ratio, the film formation pressure, and the growth rate are adjusted in the epitaxial growth step. Furthermore, it is preferable to perform a cleaning step for cleaning the surface of the SiC single crystal on which the epitaxial film is grown before the epitaxial growth step.

[0078] In the cleaning step, after the SiC single-crystal substrate is deposited in the CVD apparatus, hydrogen is introduced as a carrier gas, and the temperature is increased while maintaining a predetermined pressure. In a reduced-pressure state, the surface of the SiC single-crystal substrate is exposed to high-temperature hydrogen gas for cleaning. The temperature at which the surface is cleaned can be optionally selected and is preferably 1550°C or higher and 1650°C or lower, and the cleaning time is preferably 5 minutes or longer and 60 minutes or shorter. The pressure in the cleaning step is preferably 30 Torr (4 kPa) or less, and more preferably in a range of 15 Torr to 30 Torr (2 kPa to 4 kPa). If the pressure is too low, discharge may occur in the epitaxial device. Therefore, the pressure in the cleaning step is preferably set to 15 Torr or more.

[0079] Subsequently, an epitaxial growth step is performed. In the epitaxial growth step, the flow rate of the Si-based raw material gas and the flow rate of the C-based raw material gas are preferably such that the growth rate of the SiC epitaxial layer is 50 μm / h or more, more preferably such that the flow rate is 60 μm / h or more. The upper limit of the growth rate is not particularly limited, but may be, for example, a flow rate at which the growth rate is 300 μm / h or less, or a flow rate at which the growth rate is 200 μm / h or less.

[0080] By increasing the growth rate from the initial growth stage, the basal plane dislocations of the SiC single crystal substrate can be converted into edge dislocations with high efficiency at the interface between the SiC single crystal substrate and the epitaxial layer. It is therefore possible to accelerate the transformation of the Fig.2C, in which the basal plane dislocation is transformed into the edge dislocation after the basal plane dislocation penetrates the epitaxial layer. The initial growth stage here refers to a time when the raw material gas supply is started, and the growth rate is a growth rate that can be determined based on the flow rate or flow rate. Therefore, setting the growth rate to a predetermined value from the initial growth stage means setting the state when the raw material gas supply is started to a state where the growth rate assumes a predetermined value.

[0081] When a growth time is provided in the epitaxial growth step at which the growth rate is 50 µm / h or more, the density of the basal plane dislocations 2A of basal plane dislocations extending from the SiC single crystal substrate 1 without being converted into the edge dislocations 2B can be 0.1 dislocations / cm even in a SiC epitaxial wafer 10 of 15.24 cm (6 inches) or more. 2 or less. Furthermore, if the growth is carried out from the initial stage of growth at a growth rate of 50 µm / h or more, a total basal plane dislocation density of basal plane dislocations located in a region from the SiC single crystal substrate to the outer surface and the basal plane dislocations that are converted into edge dislocations in the epitaxial layer can be 0.1 dislocations / cm 2 or less.

[0082] In the SiC epitaxial wafer 10 of "15.24 cm (6 inches) or more", it is very important that the basal plane dislocation density of the basal plane dislocation 2A extending from the SiC single crystal substrate 1 without being converted into the edge dislocation 2B is 0.1 dislocations / cm 2 or less. For conventional SiC epitaxial wafers of 10.16 cm (4 inches) or less, SiC epitaxial wafers have been reported to have relatively low basal plane dislocation density. However, there is no such report for a SiC epitaxial wafer of 15.24 cm (6 inches) or larger. In the SiC epitaxial wafer of 15.24 cm (6 inches) or larger, variations in the film formation conditions of the SiC single crystal substrate exist, making it difficult to achieve the same result as with 10.16 cm (4 inches).

[0083] For a SiC epitaxial wafer 10 of 10.16 cm (4 inches) or less, with a growth rate of the epitaxial layer 2 of less than 50 µm / h, the basal plane dislocation density may be 0.1 dislocations / cm 2 or less. Examples include a case where the number of basal plane dislocations 1A of the SiC single crystal substrate 1 itself is small, or a case where the film formation conditions are fixed to certain conditions.

[0084] In practice, however, the state of the SiC single-crystal substrate 1 is not identical and varies for each batch or wafer. Furthermore, the film formation conditions must also be changed for various reasons. Therefore, even in a SiC epitaxial wafer 10 of 10.16 cm (4 inches) or less, it is difficult to stably reduce the basal plane dislocation density.

[0085] Furthermore, a small number of basal plane dislocations in the SiC single crystal substrate is more advantageous for reducing the basal plane dislocations extending into the epitaxial layer. However, it is difficult to manufacture a SiC single crystal substrate with a small number of basal plane dislocations, and a SiC single crystal substrate of 15.24 cm (6 inches) or more with a small number of basal plane dislocations is very expensive. When the growth rate of the epitaxial layer is set to 60 μm or more, the efficiency of converting the basal plane dislocations into edge dislocations can be 99.995% or more. Therefore, even if a SiC single crystal substrate with 5000 to 1000 basal plane dislocations per 1 cm 2 which is available at a relatively low price, the basal plane dislocations in the epitaxial layer can be reduced to 0.1 dislocations / cm 2 or less.

[0086] When comprehensively considering the suppression of crystal defects, the C / Si ratio is preferably set to 0.8 to 1.2. Furthermore, it is preferable that the film formation pressure in the epitaxial growth step be the same as the chamber pressure in the SiC substrate cleaning step. When these pressures are equal, there is no disruption of the gas flow caused by pressure fluctuations. This can suppress the formation of Si droplets or the like.

[0087] The formation of Si droplets can be prevented if a gas containing Cl element starts flowing at the same time. When the C / Si ratio is large, it can be considered that Si is not in excess in the film formation environment, so Si droplets are not generated. However, the formation of Si droplets is caused by fluctuations in the raw material ratio in the growth space. Therefore, even if the C / Si ratio is controlled to an appropriate value close to 1, it is difficult to completely suppress local formation of Si droplets caused by fluctuations in the raw material ratio. Especially in epitaxial growth performed on a substrate with a large diameter of 15.24 cm (6 inches) or more, local fluctuations in the raw material ratio are likely to occur, which are difficult to completely eliminate.The formation of Si droplets over the entire surface of the SiC substrate can be suppressed if the Cl element-containing gas flows so that the Cl / Si ratio reaches a certain level or more simultaneously with the flow of the raw material gas.

[0088] Here, "simultaneous" means a state in which a Si-based raw material gas, a C-based raw material gas, and a Cl-containing gas flow at a predetermined flow rate at a time when growth essentially begins. Even if a specific gas is introduced for a short time or in a small amount before growth begins, this is permissible as long as growth is not performed and the substrate surface is not affected.

[0089] The Cl / Si ratio is 8 or more. The generation of Si droplets can be reliably suppressed by adjusting the Cl / Si ratio within the above range. The Cl / Si ratio is affected by the growth rate and growth temperature. However, when the Cl / Si ratio is greater than 6, the formation of Si droplets is suppressed, and when the Cl / Si ratio is 8 or more, the formation of Si droplets can be suppressed to a predetermined value or less. The Cl / Si ratio can be greater than 3 by flowing the Si raw material gas and the gas containing Cl element but not containing Si. In the case of using trichlorosilane as the Si raw material gas, the Cl / Si ratio in the gas composition is 3, but the Cl / Si ratio can be greater than 6 by adding HCl.

[0090] Furthermore, the Cl / Si ratio is preferably 12 or less, and more preferably 10 or less. If the Cl / Si ratio is too high, trapezoidal defects are generated or surface roughness is increased, thus impairing the morphology. Furthermore, as the amount of Cl used increases, the load on a growth device increases, and exhaust gas treatment also becomes expensive.

[0091] Fig. Figures 5A to 5C are differential interference microscopy images of the surface of SiC epitaxial wafers grown with a varied Cl / Si ratio. Epitaxial growth was performed using trichlorosilane as the Si-based raw material gas, propane as the C-based raw material gas, and HCl gas as the chlorine-based gas. The growth temperature was 1600°C, the C / Si ratio was 1, and the growth rate was 60 µm / h.

[0092] Fig.Figure 5A shows a case where the HCl / trichlorosilane ratio is 1 and the Cl / Si ratio is 4. Collection defects, in which pits caused by Si droplets appear in a line, were confirmed (in the areas surrounded by the dashed line in the figure).

[0093] Fig. Figure 5B shows a case where the HCl / trichlorosilane ratio is 3 and the Cl / Si ratio is 6. The depressions caused by Si droplets are smaller than in Fig. 5A, thus demonstrating an effect of increasing the Cl / Si ratio. However, some Si droplet-induced collection defects appeared in the wafer (in the areas surrounded by the dashed line in the figure).

[0094] Fig. Figure 5C shows a case where the HCl / trichlorosilane ratio is 5 and the Cl / Si ratio is 8. No defects caused by Si droplets were confirmed.

[0095] When the Cl / Si ratio is further increased, for example, when the Cl / Si ratio is 19, trapezoidal defects were formed. A trapezoidal defect is a typical defect that affects the surface morphology at a high Cl / Si ratio. The trapezoidal defect is a defect with a trapezoidal shape in a surface view and is a defect having an upper base, where the upper base is a defect that extends in a direction perpendicular to a displacement direction of the substrate, that is, extends in a direction of a step and is formed to continue to the epitaxial growth layer. The trapezoidal defect is caused by a defect such as dislocations existing in the substrate, and the defect is formed by performing selective local etching before epitaxial growth.

[0096] Therefore, if the Cl / Si ratio is too high, the substrate surface is in an etched state during the initial growth phase, and a trapezoidal defect is likely to be generated. Furthermore, the deterioration of the morphology at a high Cl / Si ratio can be measured as surface roughness using AFM or the like.

[0097] The gas containing the Cl element and the raw material gas preferably start flowing simultaneously. When a gas containing Si and Cl is used for the Si-based raw material gas, Si and Cl are supplied simultaneously. Therefore, it is preferable that the gas containing the Cl element also serve as the Si-based raw material gas.

[0098] Even if the Cl element-containing gas also serves as the Si-based raw material gas, it is necessary to flow a non-Si-containing Cl-based gas, such as HCl, to adjust the Cl / Si ratio to 8 or more. In this case, it is preferable that the Cl-based gas that does not contain Si starts flowing at the same time as other raw material gases, so that a certain amount of Cl is present on the substrate at the same time as the start of growth, but no Cl is present before growth. If the Cl-based gas is present before the start of growth, the risk of the substrate surface being etched increases. If the substrate surface is etched, the trapezoidal defects may be generated or the surface roughness increases, resulting in deterioration of the morphology.

[0099] As described above, in the method for manufacturing the SiC epitaxial wafer according to the present embodiment, by increasing the growth rate, the efficiency of conversion from the basal plane dislocation 1A to the edge dislocation 2B is increased, and then the basal plane dislocation density of the basal plane dislocations extending from the SiC single crystal substrate 1 in the epitaxial wafer without being converted into edge dislocations 2B can be 0.1 dislocations / cm 2 or less.

[0100] Furthermore, by setting the growth rate to a predetermined rate or higher, the basal plane dislocation density can be stably controlled to 0.1 dislocations / cm with high reproducibility. 2 or less, even for a different SiC single crystal substrate or different film forming conditions.

[0101] Furthermore, the density of defects caused by Si droplets can be reduced to 0.1 defects / cm 2 or less, since the formation of defects caused by Si droplets is suppressed by initiating growth in such a way that the raw material gas and the Cl element-containing gas are simultaneously supplied under certain C / Si ratios and Cl / Si ratios.

[0102] Furthermore, by setting the Cl / Si ratio to a predetermined value or more, an epitaxial wafer without defects caused by Si droplets can be manufactured. (SiC epitaxial wafer)

[0103] A SiC epitaxial wafer according to the present embodiment can be manufactured using the manufacturing method described above.

[0104] The SiC epitaxial wafer according to the present embodiment includes the SiC single crystal substrate 1 and the SiC epitaxial layer 2 as shown in Fig.1 shown.

[0105] In the SiC single-crystal substrate 1, the main surface has an off-angle of 0.4° to 5° with respect to the (0001) plane. When the off-angle is within the above range, the epitaxial layer 2 can be grown while maintaining the off-angle required for the device.

[0106] The basal plane dislocation density of basal plane dislocations in a region from the SiC single crystal substrate 1 of the epitaxial layer 2 to the outer surface is 0.1 dislocations / cm 2 or less, and the defects caused by Si droplets are 0.1 defects / cm 2 or less. Depending on the manufacturing conditions, the number of defects caused by Si droplets can be reduced to zero.

[0107] The basal plane dislocations are detected using a photoluminescence method. By using light with a wavelength of 400 nm or less as excitation light, a linear defect is detected as a basal plane dislocation. The linear defect runs in the step flow direction during epitaxial growth and luminesces with light with a wavelength of 700 nm. The measurement is performed on the entire surface of the wafer. Specifically, the measurement is performed on an area of ​​80% or more of the wafer, excluding the outer peripheral end. The number of basal plane dislocations detected in the SiC epitaxial wafer is counted and divided by the area of ​​the SiC epitaxial wafer to obtain the basal plane dislocation density.

[0108] The defects caused by Si droplets are detected using a confocal differential interference contrast microscope with a magnification of 20x or higher. The defects caused by Si droplets include both isolated pits and a typical cluster defect, where the pits are arranged vertically. Each isolated pit is counted as one, and a cluster defect is counted as a line of arranged pits, thus providing quantification. The measurement is performed on the entire surface of the wafer in the same way as the measurement of basal plane dislocations. The number of detected defects caused by Si droplets is then counted in the SiC epitaxial wafer, and the number is divided by the area of ​​the SiC epitaxial wafer to obtain the density of Si droplets.

[0109] The diameter of the SiC single-crystal substrate is preferably 150 mm or more (6 inches or more). It is important that the SiC epitaxial wafer be 6 inches or more. This increases the number of SiC devices that can be fabricated from a single SiC epitaxial wafer and reduces the cost of the SiC devices. SiC devices have the problem of being very high in performance but more expensive than Si devices. Therefore, a large SiC device with a low basal plane dislocation density leads to a significant cost reduction.

[0110] The thickness of the epitaxial layer is not limited, but is preferably 10 µm or more.

[0111] The shape of the SiC epitaxial wafer is not particularly limited. The shape of the SiC epitaxial wafer can be a circle or a shape with a notch, such as an orientation flat (OF), which is commonly used.

[0112] In the SiC epitaxial wafer according to the present embodiment, the amount of defects caused by Si droplets and basal plane dislocations (BPD) that lead to device killer defects of the SiC device in the epitaxial layer is small, thereby increasing the quality of the SiC device.

[0113] Furthermore, in modules for automobiles and the like, a large current of 100A is used in a device. Therefore, a SiC chip (a substrate of the SiC device) made from a SiC epitaxial wafer has a large size, for example, 10 mm square. In such a large SiC chip, reducing the basal plane dislocation density is extremely important because the effect of reducing the basal plane dislocation density on yield is extremely high. EXAMPLES

[0114] Examples of the present invention are described below. (Example 1)

[0115] A 15.24 cm (6-inch) SiC single-crystal substrate was fabricated. The fabricated SiC single-crystal substrate is a 4H polytype, and one major surface includes a Si surface with an offset angle of 4° in the <11-20> direction from the (0001) plane.

[0116] The SiC single-crystal substrate was then placed in a growth furnace, and a cleaning step was performed, in which a growth surface was etched with hydrogen gas. The etching temperature was set to 1600°C, which was equal to the epitaxial growth temperature, and the pressure was set to 3999 Pa (30 Torr).

[0117] Next, while supplying hydrogen to the surface of the etched 4H-SiC single crystal substrate and maintaining the same pressure, the supply of trichlorosilane and propane as raw material gases and HCl as a Cl element-containing gas was started to grow an epitaxial layer.

[0118] In the epitaxial growth step, the ratio of the C-based raw material gas to the Si-based raw material gas was set to the C / Si ratio of 1.0 and the gas flow rate was set to a growth rate of 50 µm / h.

[0119] The flow rates of trichlorosilane and HCl were adjusted so that the Cl / Si ratio was 8. Under these conditions, the SiC epitaxial layer was grown to 10 µm.

[0120] The basal plane dislocation density of the fabricated SiC epitaxial wafer was evaluated using a photoluminescence imaging device (manufactured by Photon Design Co. Ltd.). Furthermore, pits caused by Si droplets were counted using a confocal optical surface inspection device with differential interference contrast (SICA). The basal plane dislocations were found to be 0.02 dislocations / cm. 2 (3 pieces / wafer), and the pits caused by Si droplets were 0.03 pits / cm 2 (6 pieces / wafer). (Example 2)

[0121] Example 2 was the same as Example 1 except that the Cl / Si ratio was set to 10.

[0122] The basal plane dislocation density of the resulting SiC epitaxial wafer was evaluated. The basal plane dislocations were 0.04 dislocations / cm 2 and there were no depressions caused by Si droplets. (Example 3)

[0123] Example 3 was the same as Example 1, except that the growth rate was set to 65 µm / h. The basal plane dislocation density of the resulting SiC epitaxial wafer was evaluated. The basal plane dislocations were 0.01 dislocations / cm 2 The depressions caused by Si droplets were 0.053 depressions / cm 2 . (Comparison example 1)

[0124] Comparative Example 1 differs from Example 1 in that the growth rate was 45 µm / h. The other conditions were the same as in Example 1. The basal plane dislocation density of the resulting SiC epitaxial wafer was evaluated. The basal plane dislocations were 8 dislocations / cm 2 and the depressions caused by Si droplets were 0.02 depressions / cm 2 . (Comparison example 2)

[0125] Comparative Example 2 differs from Example 1 in that no HCl was added and the Cl / Si ratio was 3. The other conditions were the same as in Example 1. The basal plane dislocation density of the resulting SiC epitaxial wafer was evaluated. The basal plane dislocations were 0.01 dislocations / cm 2 and the depressions caused by Si droplets were 10 depressions / cm 2 . [Table 1] Growth rate (µm / h) C / Si ratio Cl / Si ratio Basal plane dislocation density (dislocations / cm 2 ) Density of defects caused by Si droplets (defects / cm 2 ) Example 1 50 1 8 0,02 0,03 Example 2 50 1 10 0,04 0 Example 3 65 1 8 0.01 0,05 Comparison example 1 45 1 8 8 0,02 Comparison example 2 60 1 3 0,01 10 Industrial applicability

[0126] According to the present invention, it is possible to obtain a SiC epitaxial wafer having a small number of basal plane dislocations (BPD) causing device killer defects and a small number of defects caused by Si droplets, and a method for producing the same. List of reference symbols 1 SiC single crystal substrate 2 Epitaxial layer 10 SiC epixie wafers 1a Growth surface 1A, 2A basal plane dislocation 2B Threading Edge Dislocation

Claims

[1] SiC epitaxial wafer, with: a SiC single-crystal substrate whose main surface has an offset angle of 0.4° to 5° with respect to a (0001) plane; and an epitaxial layer provided on the SiC single crystal substrate, wherein in the epitaxial layer, a basal plane dislocation density of basal plane dislocations extending from the SiC single crystal substrate to an outer surface is 0.1 dislocations / cm 2 or less and a defect density caused by Si droplets of 0.1 defects / cm 2 or less, wherein the defects caused by the Si droplets are scattered pits and / or cluster defects in which pits are arranged in a direction perpendicular to an offset direction in an in-plane direction of the SiC single crystal substrate. [2] The SiC epitaxial wafer of claim 1, wherein the defect density caused by Si droplets is zero defects / cm 2 is. [3] The SiC epitaxial wafer according to claim 1 or 2, wherein the total basal plane dislocation density of the basal plane dislocations extending from the SiC single crystal substrate to the outer surface and basal plane dislocations converted into edge dislocations in the epitaxial layer is 0.1 dislocations / cm 2 or less. [4] The SiC epitaxial wafer according to any one of claims 1 to 3, wherein the diameter of the SiC single crystal substrate is 150 mm or more. [5] A method for producing a SiC epitaxial wafer as described in claim 1, wherein crystal growth of an epitaxial layer is performed on a SiC single crystal substrate whose main surface has an offset angle of 0.4 to 5° with respect to the (0001) plane, the method comprising the steps of: an epitaxial growth step of growing the epitaxial layer on the SiC single crystal substrate by supplying a Si-based raw material gas, a C-based raw material gas, and a gas containing a Cl element to a surface of the SiC single crystal substrate, wherein the epitaxial growth step is carried out under growth conditions in which the film deposition pressure is 4000 Pa (30 Torr) or less, the Cl / Si ratio is in a range of 8 to 12, the C / Si ratio is in a range of 0.8 to 1.2, and the growth rate from the initial stage of growth is 50 µm / h or more. [6] A method for producing a SiC epitaxial wafer according to claim 5, the method further comprising a cleaning step of cleaning the surface of the SiC single crystal substrate before the epitaxial growth step by heating the surface to 1550°C to 1650°C in a hydrogen atmosphere under a pressure of 4000 Pa (30 Torr) or less. [7] A method for producing a SiC epitaxial wafer according to claim 5 or 6, wherein the gas containing the Cl element serves as the Si-based raw material gas.

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