Semiconductor device and control device

Abstract

To provide a semiconductor device that can release a central processing unit from management by a timer circuit after an initial periodic value is set and can reduce complexity of timing setting.SOLUTION: A semiconductor device 11 configured to perform PFM control includes: a timer circuit 13; a first storage circuit 15 that stores a periodic value of a counter circuit 21; an arithmetic circuit 17 connected to the first storage circuit 15; and an A / D conversion circuit 19 that converts an analog signal into a digital signal. The timer circuit 13 is configured to generate a timer signal in accordance with the periodic value in the first storage circuit 15. The arithmetic circuit 17 includes a bit processing circuit 29 coupled to the first storage circuit 15. The bit processing circuit 29 performs a bit processing operation on bits in a digital value to generate an update signal indicating an updated periodic value.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a control device. [Background technology]

[0002] Patent Document 1 discloses a control device for a DC-DC converter that uses a low-cost CPU and yet is capable of outputting a high-resolution PFM signal.

[0003] The PFM signal generating circuit of Patent Document 1 inputs a 5 MHz reference clock to a CPU to operate a calculation unit. The CPU has an internal counter. The internal counter counts the reference clock to count a value that is N times the period defined by the switching frequency, and generates a signal having a frequency component that is 1 / N of the switching frequency upon completion of the counting operation. The counter output signal is multiplied using a multiplier to generate a PFM signal having a switching frequency component. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2004-194484 A Summary of the Invention [Problem to be solved by the invention]

[0005] When a power supply circuit is controlled using a microcomputer with Pulse Frequency Modulation (PFM) control, the following procedure is performed. The voltage of the node shared between the power supply circuit and the load circuit is taken in via the conversion result of the A / D conversion circuit, the load state is judged, and the value of the periodic buffer circuit of the timer circuit is updated based on the judged result. These procedures are performed via the central processing unit of the microcomputer. For this reason, the response to load fluctuations may be limited by the operating speed of the central processing unit. In addition, processing that exceeds the operating speed of the central processing unit cannot be executed. Furthermore, since the resources of the central processing unit are allocated to the processing of PFM control, the adaptation of PFM control is delayed when the central processing unit prioritizes execution of other processing, or the adaptation of other processing is delayed when the central processing unit is made to interrupt the execution of other processing.

[0006] An object of the present invention is to provide a semiconductor device and a control device that can release a central processing unit from management of a timer circuit after setting an initial period value in PFM control and reduce the complexity of timing settings. [Means for solving the problem]

[0007] A semiconductor device according to a first aspect of the present invention is a semiconductor device configured to perform PFM control, and comprises: at least one timer circuit including a counter circuit that counts clock signals; a first storage circuit configured to store a period value of the timer circuit; a first electrode configured to be connectable to the outside of the semiconductor device; a second electrode configured to be connectable to the outside of the semiconductor device; an A / D conversion circuit configured to receive a signal from the first electrode and convert the signal into a digital signal; and an arithmetic circuit configured to receive a conversion result from the A / D conversion circuit, wherein the timer circuit is configured to generate a timer signal according to the period value of the first storage circuit, and the timer circuit is connected to the second electrode to provide the timer signal, and the arithmetic circuit includes a bit processing circuit, and the bit processing circuit is configured to perform a bit processing operation on at least a portion of the bits of the digital value of the conversion result to generate an update signal indicating an updated period value.

[0008] A control device according to a second aspect of the present invention includes the semiconductor device described in the above aspect, and an external circuit that operates in response to the timer signal from the timer circuit and is provided outside the semiconductor device. Effect of the Invention

[0009] According to the above aspects, a semiconductor device and a control device are provided that can release the central processing unit from management of the timer circuit after setting an initial period value and reduce the complexity of timing settings. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram illustrating a control device and a semiconductor device according to the present embodiment. [Diagram 2] FIG. 2 is a diagram showing waveforms of main nodes in the control device according to the present embodiment. [Diagram 3] FIG. 3 is a diagram showing the timing of updating the first storage circuit by the arithmetic circuit of the control device and the semiconductor device according to the present embodiment. [Figure 4] FIG. 4 is a diagram illustrating an arithmetic circuit of the control device and the semiconductor device according to the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar parts are designated by the same or similar reference numerals, and duplicated description will be omitted.

[0012] FIG. 1 is a diagram illustrating a control device and a semiconductor device according to the present embodiment.

[0013] The semiconductor device 11 is configured to perform PFM control. The semiconductor device 11 includes at least one timer circuit 13, at least one first storage circuit 15, an arithmetic circuit 17, and a voltage detection circuit (A / D conversion circuit 19). In the following description, the A / D conversion circuit 19 will be referred to as the voltage detection circuit.

[0014] The timer circuit 13 includes a counter circuit 21 that counts the clock signal SCLK, and can generate a timer signal STMR with a variable period. The first storage circuit 15 stores a period value TCYC (not shown) of the counter circuit 21. The arithmetic circuit 17 is connected to the first storage circuit 15. The A / D conversion circuit 19 converts a signal from the first electrode 23 into a digital signal SDGT as an analog signal SANA. The timer circuit 13 is configured to generate a timer signal STMR according to the period value TCYC of the first storage circuit 15. The timer circuit 13 is connected to the second electrode 25 to provide the timer signal STMR. The arithmetic circuit 17 includes a second storage circuit 27 and a bit processing circuit 29.

[0015] The second storage circuit 27 stores the digital value of the digital signal SDGT. The bit processing circuit 29 is coupled to the second storage circuit 27 to receive the digital value of the digital signal SDGT from the second storage circuit 27 as a subject for a bit processing operation. The bit processing circuit 29 performs a bit processing operation on the bits in the digital value to generate an update signal SUPD indicative of an updated period value (an update period value TUPD (not shown)).

[0016] The first electrode 23 and the second electrode 25 are configured to be connected to the outside of the semiconductor device 11. The timer circuit 13 can provide a timer signal STMR to an external circuit 31 connected via the second electrode 25. The A / D conversion circuit 19 receives a signal (e.g., an analog signal SANA) from the external circuit 31 via the first electrode 23.

[0017] The exemplary timer circuit 13, specifically, the counter 33, the clear circuit 34, and the output circuit 35 can operate according to a timing signal associated with the clock signal SCLK. The exemplary A / D conversion circuit 19 can operate according to a timing signal associated with the clock signal SCLK. The exemplary arithmetic circuit 17 can operate according to a timing signal associated with the clock signal SCLK. The semiconductor device 11 does not require sending a timing signal from the arithmetic circuit 17 to the A / D conversion circuit 19 and a timing signal from the A / D conversion circuit 19 to the arithmetic circuit 17 in order to operate the A / D conversion circuit 19 and the arithmetic circuit 17 in synchronization. The semiconductor device 11 can reduce the complexity of the timing setting. The output circuit 35 can define the duty of the timer signal STMR independently of the period. The clear circuit 34 clears the counter 33 in response to the counter 33 matching the stored value of the first storage circuit 15 and causes the counter 33 to start the next count.

[0018] The arithmetic circuit 17 provides the update value to the first storage circuit 15 according to a timing signal related to the clock signal SCLK, so that the update can be prevented from interfering with the timer operation.

[0019] In the semiconductor device 11, a typical bit processing operation of the arithmetic circuit 17 may be, for example, a bit shift operation. The bit processing operation is not limited to this, and may include various processes such as a logical OR operation and a logical AND operation on at least some bits of the bit value of the digital signal SDGT, masking of the bit on the LSB side, masking of the bit on the MSB side, and combinations of these processes in addition to the bit shift operation. The bit shift operation may include, for example, a bit shift from the LSB side to the MSB side, and a bit shift from the MSB side to the LSB side.

[0020] Furthermore, when the output bit width of the A / D conversion circuit 19 is different from the bit width of the first storage circuit 15, the arithmetic circuit 17 can generate an update signal SUPD with a bit width that matches the bit width of the first storage circuit 15. Furthermore, the arithmetic circuit 17 can provide the bit-shifted conversion result to the first storage circuit 15 as is. Alternatively, the arithmetic circuit 17 can perform offset processing in which a certain constant value is added to or subtracted from the bit-shifted conversion result in the first storage circuit 15. This provides consistency between the dynamic range of the A / D conversion circuit 19 and the bit width of the period value of the timer circuit 13, and the processed value can be provided to the first storage circuit 15.

[0021] The A / D conversion circuit 19 can operate according to a timing signal associated with the clock signal SCLK depending on the conversion speed of the A / D conversion circuit 19 .

[0022] The arithmetic circuit 17 can update the second storage circuit 27 in response to some or all of the update timings of the digital signal SDGT from the A / D conversion circuit 19. The update can be performed at various timings, such as every time, every other time, or irregularly. When the A / D conversion circuit 19 is shared by a plurality of circuit groups performing a plurality of functions, the time allocated to the arithmetic circuit 17 can be a part of a series of conversion processes in the A / D conversion circuit 19. The A / D conversion circuit 19 can include an A / D converter 22b and a time-division control circuit 22c. When the A / D conversion circuit 19 is used in a time-division manner, the time-division control circuit 22c switches between the input to the A / D converter 22b and the output from the A / D converter 22b.

[0023] The arithmetic circuit 17 can receive an access signal SACS for accessing a conversion result buffer of the A / D conversion circuit 19 when a conversion operation for the arithmetic circuit 17 is performed. In response to the access signal SACS, the arithmetic circuit 17 can receive an updated digital value (SUPD) from the conversion result buffer of the A / D conversion circuit 19 and store it in the second storage circuit 27.

[0024] 1, the control device 10 can include a semiconductor device 11 and at least one external circuit 12 (14, 16) provided outside the semiconductor device 11. The external circuit 12 can operate in response to a timer signal STMR from a timer circuit 13. The external circuits (14, 16) can be connected to respective additional timer circuits (83, 85) via a third electrode 24 and a fourth electrode 26 of the semiconductor device 11.

[0025] In the control device 10, the external circuit 12 may include a power supply circuit 18. The external circuit 12 may further include a load circuit 20 connected to the output of the power supply circuit 18. The A / D conversion circuit 19 receives a signal (voltage signal) from a node ND0 (connection node) between the power supply circuit 18 and the load circuit 20. The power supply circuit 18 may include, for example, a switching power supply.

[0026] Fig. 2 is a diagram showing waveforms of main nodes in the control device according to the present embodiment. Fig. 3 shows the timing of updating the first storage circuit by the arithmetic circuit according to the present embodiment.

[0027] In the external circuit 12, a node ND0 (load voltage) monitored by the A / D conversion circuit 19 fluctuates. The A / D conversion circuit 19 periodically samples the state of the external circuit 12 as a voltage to generate an A / D conversion result. The period value of the timer circuit 13 is determined by bit processing calculation of the conversion result of the A / D conversion circuit 19. While the load voltage is A / D converted as sampling in the period T1, the first storage circuit 15 receives an updated value from the calculation circuit 17. This updated value enables the timer circuit 13 to operate based on the updated period value in the period T2.

[0028] Specifically, when the voltage (load voltage) of the node ND0 of the power supply circuit 18 is low, the conversion result of the A / D conversion circuit 19 also indicates a low value. Accordingly, the value set in the first storage circuit 15 (period buffer) for the timer circuit 13 is made smaller in conjunction with the conversion result of the A / D conversion circuit 19, thereby shortening the period. In response to this, the power supply circuit 18 increases the current supply to the load circuit 20. When the current supplied to the load circuit 20 increases, the voltage of the node ND0 increases. In response to this, the value of the conversion result of the A / D conversion circuit 19 also increases. The conversion result of the A / D conversion circuit 19 indicates a high value. Accordingly, the value set in the first storage circuit 15 (period buffer) for the timer circuit 13 is made larger in conjunction with the conversion result of the A / D conversion circuit 19, thereby lengthening the period. The current supply to the load circuit 20 decreases.

[0029] The exemplary semiconductor device 11 enables the conversion result of the A / D conversion circuit 19 to be transferred to a first storage circuit 15 (e.g., a periodic buffer) for the timer circuit 13 via a bit processing circuit 29 without going through a central processing unit, i.e. directly. The exemplary bit processing circuit 29 can bit-shift the conversion result of the A / D conversion circuit 19 (e.g., n-bit, n is a natural number excluding zero, e.g., 16) to the left, for example, and shifting by 1 bit makes the conversion result of the A / D conversion circuit 19 1 / 2. The bit-shifted value is sent from the arithmetic circuit 17 to the first storage circuit 15, and the first storage circuit 15 (periodic buffer) is updated. The timing for updating the first storage circuit 15 is after the counter value of the timer circuit 13 is cleared in response to the counter value matching the value of the previous period.

[0030] When the load circuit 20 starts to consume a large amount of current, the voltage of the node ND0 decreases. The timer circuit 13 shortens the period of the timer waveform in accordance with the conversion result of the A / D conversion circuit 19, thereby increasing the high-level period of the timer waveform. The power supply circuit 18 increases the output current.

[0031] When the load circuit 20 does not consume much current, the timer circuit 13 lengthens the period of the timer waveform according to the conversion result of the A / D conversion circuit 19, thereby reducing the high-level period of the timer waveform. The power supply circuit 18 reduces the output current. A voltage detection circuit such as the A / D conversion circuit 19 directly controls the period of the timer waveform using a dedicated arithmetic circuit 17.

[0032] More specifically, if the voltage of the node ND0 is equal to or greater than a certain value, a small amount of output current is sufficient from the power supply circuit 18. If the voltage of the node ND0 is less than a certain value, a large amount of current is required.

[0033] 4 is a diagram illustrating an arithmetic circuit of the control device and the semiconductor device according to the present embodiment. The second storage circuit 27, the bit processing circuit 29, the third storage circuit 41, and other circuits 40 of the arithmetic circuit 17 will be described with reference to FIG.

[0034] In the semiconductor device 11, the arithmetic circuit 17 may further include a third storage circuit 41, which may store the pre-update (previous update) value of the digital signal SDGT from the second storage circuit 27 in response to the access signal SACS.

[0035] The arithmetic circuit 17 may further include a first shift direction specification circuit 43. The first shift direction specification circuit 43 may generate a shift direction signal SHFT that specifies the shift direction of the bit shift operation according to the difference in magnitude between the stored value V27 of the second storage circuit 27 and the stored value V35 of the third storage circuit 41.

[0036] The bit processing circuit 29 performs a bit shift operation in accordance with the shift direction signal SHFT.

[0037] The arithmetic circuit 17 may include a judgment circuit 45. The judgment circuit 45 may judge whether an absolute value VABS (not shown) of a difference between a stored value V27 of the second storage circuit 27 and a stored value V35 of the third storage circuit 41 exceeds a shift judgment value TSFT1, and generate a judgment signal SSFT1. The shift judgment value TSFT1 represents a minimum difference for which a bit shift operation should be performed, and may be stored in the fourth storage circuit 47.

[0038] When the determination signal SSFT1 indicates that the absolute value VABS (not shown) exceeds the shift determination value TSFT1, the bit processing circuit 29 performs a bit shift operation in accordance with the shift direction signal SHFT from the first shift direction specification circuit 43. However, the bit processing circuit 29 may perform a bit shift operation every time the stored value V27 of the second storage circuit 27 is updated. Moreover, when the determination signal SSFT1 indicates that the absolute value VABS is equal to or smaller than the shift determination value TSFT1, the bit processing circuit 29 does not perform a bit shift operation.

[0039] The arithmetic circuit 17 may include a magnitude circuit 49. The magnitude circuit 49 may generate a value indicating which of the stored value V27 of the second storage circuit 27 and the stored value V35 of the third storage circuit 41 is larger, and may provide an absolute value VABS based on this value. The magnitude circuit 49 may provide the absolute value VABS to the first shift direction identification circuit 43.

[0040] The arithmetic circuit 17 may include a difference circuit 51 that generates a difference between the stored value V27 of the second storage circuit 27 and the stored value V35 of the third storage circuit 41. The difference circuit 51 may be provided within the magnitude circuit 49, or the difference circuit 51 may be provided separately from the magnitude circuit 49. A signal of the difference of the difference circuit 51 may be provided to the first shift direction identification circuit 43.

[0041] The arithmetic circuit 17 further includes a second determination circuit 65, which can determine whether or not the stored value V27 of the second storage circuit 27 exceeds the upper limit reference value VMAX to generate a second determination signal SSFT2.

[0042] The arithmetic circuit 17 may further include a first alert circuit 67, which may generate an upper limit alert signal SRTU when the second determination signal SSFT2 indicates that the stored value V27 of the second storage circuit 27 exceeds the upper limit reference value VMAX. The arithmetic circuit 17 may include a fifth storage circuit 69 that stores the upper limit reference value VMAX.

[0043] In addition, the arithmetic circuit 17 further includes a third judgment circuit 71, which can judge whether or not the stored value V27 of the second storage circuit 27 exceeds a lower limit reference value VMIN to generate a third judgment signal SSFT3.

[0044] The arithmetic circuit 17 may further include a second alert circuit 73, which may generate a lower limit alert signal SRTD when the third determination signal SSFT3 indicates that the stored value V27 of the second storage circuit 27 exceeds the lower limit reference value VMIN. The arithmetic circuit 17 may include a sixth storage circuit 75 that stores the lower limit reference value VMIN.

[0045] The combination of the arithmetic circuit 17 and the A / D conversion circuit 19 specifies the content of bit processing based on the difference between the latest update value (V27) from the A / D conversion circuit 19 and the previous update value (V35), and this processing is applied to the latest update value. The processed update value is transferred to the first storage circuit 15 at a timing associated with the clock signal SCLK. These updates are performed according to the relationship (proximity relationship) between the latest update value on the time axis and the previous update value in its vicinity.

[0046] The arithmetic circuit 17 may include a difference circuit 53, which generates a difference between the stored value V27 of the second storage circuit 27 and a reference value VREF. The reference value VREF may be specified as a target value for the PFM controlled processing target device. The arithmetic circuit 17 may further include a fourth judgment circuit 59. The fourth judgment circuit 59 may judge whether an absolute value VABS2 (not shown) of the difference between the stored value V27 of the second storage circuit 27 and the reference value VREF exceeds a second shift judgment value TSFT2 or not, and generate a fourth judgment signal SSFT4.

[0047] The second shift determination value TSFT2 can be specified as a value for determining whether the latest updated value of the A / D conversion circuit 19, that is, the absolute value VABS2 of the stored value V27 of the second storage circuit 27 and the reference value VREF, is greater or not.

[0048] When the fourth judgment signal SSFT4 indicates that the absolute value VABS2 exceeds the second shift judgment value TSFT2, the arithmetic circuit 17 can further include a second shift direction specification circuit 57. The second shift direction specification circuit 57 can specify the shift direction of the bit shift operation according to the difference in magnitude between the stored value V27 of the second storage circuit 27 and the reference value VREF.

[0049] When the fourth judgment signal SSFT4 indicates that the absolute value of the difference of the differential circuit 53 exceeds the second shift judgment value TSFT2, the arithmetic circuit 17 can perform a bit shift operation according to the second shift direction signal SHFT2 instead of the shift direction signal SHFT. Also, when the fourth judgment signal SSFT4 indicates that the absolute value of the difference of the differential circuit 53 is equal to or smaller than the second shift judgment value TSFT2, the arithmetic circuit 17 does not perform a bit shift operation.

[0050] The arithmetic circuit 17 can include a seventh storage circuit 61 and an eighth storage circuit 63. The seventh storage circuit 61 can store the second shift judgment value TSFT2, and the eighth storage circuit 63 can store the reference value VREF.

[0051] The semiconductor device 11 may further include additional timer circuits (83, 85). The additional timer circuits (83, 85) may be configured similarly to the timer circuit 13, but are not limited to this.

[0052] The semiconductor device 11 may further include a central processing unit 81. The central processing unit 81 may be connected to the timer circuit 13, the additional timer circuits (83, 85) and the A / D conversion circuit 19. The central processing unit 81 is configured to set, for example, a period value of the first storage circuit 15 for the timer circuit 13. Once the period value of the first storage circuit 15 is determined by the central processing unit 81, the central processing unit 81 is relieved from managing the timer processing.

[0053] The A / D conversion circuit 19 can be configured to receive a signal from the output of another circuit (not shown) that operates in response to the timer signal from the additional timer circuits (83, 85) and convert the received signal as an analog value into a digital value. The A / D conversion circuit 19 can be configured to be operable in a time-division multiplexing manner to generate update signals for the timer circuit 13 and the additional timer circuits (83, 85).

[0054] According to the present embodiment, a semiconductor device 11 and a control device 10 are provided that can release the central processing unit from management of the timer circuit after setting an initial period value and reduce the complexity of timing settings.

[0055] The present embodiment can have various aspects.

[0056] A semiconductor device according to a first aspect of this embodiment is a semiconductor device configured to perform PFM control, and includes at least one timer circuit including a counter circuit that counts clock signals, a first storage circuit configured to store a period value of the timer circuit, a first electrode configured to be connectable to the outside of the semiconductor device, a second electrode configured to be connectable to the outside of the semiconductor device, an A / D conversion circuit configured to receive a signal from the first electrode and convert the signal into a digital signal, and an arithmetic circuit configured to receive a conversion result from the A / D conversion circuit, wherein the timer circuit is configured to generate a timer signal according to the period value of the first storage circuit, and the timer circuit is connected to the second electrode to provide the timer signal, and the arithmetic circuit includes a bit processing circuit, and the bit processing circuit is configured to perform a bit processing operation on at least a portion of the bits of the digital value of the conversion result to generate an update signal indicating an updated period value.

[0057] In the semiconductor device according to the first aspect of the present embodiment, the bit processing operation can be a bit shift operation.

[0058] In a semiconductor device of a third aspect according to the second aspect of this embodiment, the arithmetic circuit includes a second storage circuit that stores the digital value, and the arithmetic circuit updates the second storage circuit in response to some or all of the updating of the conversion result from the A / D conversion circuit, and the arithmetic circuit may further include a third storage circuit that stores a value of the conversion result before the update.

[0059] In a semiconductor device of a fourth aspect according to the third aspect of this embodiment, the arithmetic circuit further includes a shift direction specification circuit that generates a shift direction signal that specifies a shift direction of the bit shift operation based on a sign of a difference between the stored value of the second storage circuit and the stored value of the third storage circuit, and the bit processing circuit can perform the bit shift operation in accordance with the shift direction signal.

[0060] In a semiconductor device of a fifth aspect according to the third or fourth aspect of this embodiment, the arithmetic circuit includes a judgment circuit that judges whether an absolute value of a difference between a stored value of the second storage circuit and a stored value of the third storage circuit exceeds a shift judgment value and generates a judgment signal, and the bit processing circuit performs the bit shift operation when the judgment signal indicates that the absolute value exceeds the shift judgment value, and the bit processing circuit does not perform the bit shift operation when the judgment signal indicates that the absolute value is equal to or smaller than the shift judgment value, and the shift judgment value can represent the minimum difference for which the bit shift operation should be performed.

[0061] In a semiconductor device of a sixth aspect according to any one of the third to fifth aspects of this embodiment, the arithmetic circuit may include a differential circuit that generates a difference between the stored value of the second storage circuit and the stored value of the third storage circuit.

[0062] A semiconductor device of a seventh aspect according to any one of the first to sixth aspects of this embodiment further includes a central processing unit connected to the first storage circuit, and the central processing unit may be configured to set the period value of the first storage circuit.

[0063] A semiconductor device of an eighth aspect according to any one of the first to seventh aspects of this embodiment further includes an additional timer circuit, the additional timer circuit having a counter circuit that counts the clock signal and an additional storage circuit that stores a period value, and is configured to generate a timer signal having a variable period according to the period value of the additional storage circuit, the A / D conversion circuit being configured to receive a signal from an output of another circuit that operates in response to the timer signal from the additional timer circuit and convert the received signal into a digital value, and the A / D conversion circuit being capable of operating in a time-division multiplexing manner to generate update signals for the timer circuit and the additional timer circuit.

[0064] The control device of the ninth aspect of this embodiment may include a semiconductor device described in any one of the first to seventh aspects, and an external circuit that operates in response to the timer signal from the timer circuit and is provided outside the semiconductor device.

[0065] In a control device of a tenth aspect in accordance with the ninth aspect of this embodiment, the external circuit further includes a power supply circuit and a load circuit connected to an output of the power supply circuit, and the signal of the A / D conversion circuit may be a voltage signal of a connection node between the power supply circuit and the load circuit.

[0066] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention, all of which are included in the technical concept of the present invention. [Explanation of symbols]

[0067] 10... Control device, 11... Semiconductor device, 12...external circuit, 13. Timer circuit, 15. Storage circuit 16... storage circuit, 17... Arithmetic circuit, 18...power supply circuit, 19 A / D conversion circuit, 20...Load circuit, 21 Counter circuit, 22...Third electrode. 22b A / D converter, 22c... Time sharing control circuit, 23...first electrode, 24...Third electrode, 25...second electrode, 26...4th electrode, 27... second storage circuit, 29. Bit processing circuit, 31...external circuit, 33... Counter, 34 Clear circuit, 35 Output circuit, 41... third storage circuit, 43... Shift direction determination circuit, 45...judgment circuit, 47 Fourth storage circuit, 49. Magnitude circuit, 51...Differential circuit, 53...Differential circuit, 57... Shift direction determination circuit, 59...Fourth judgment circuit, 61...7th storage circuit, 63...8th storage circuit, 65...second judgment circuit, 67 First alert circuit, 69... Fifth storage circuit, 71...Third judgment circuit, 73...Second alert circuit, 75...6th storage circuit, 81...Central processing unit, ND0 node, SACS: Access signal, SANA: Analog signal, SCLK: Clock signal, SDGT: Digital signal, SHFT: First shift direction signal, SHFT2: Second shift direction signal, SRTD...lower limit alert signal, SRTU: Upper limit alert signal, SSFT1: First judgment signal, SSFT2: Second decision signal, SSFT3: Third decision signal, SSFT4: Fourth decision signal, STMR: Timer signal, SUPD...update signal, TCYC: Period value, TSFT1, TSFT2... Shift judgment value TUPD: Update period value, VABS, VABS2: absolute value, VMAX: Upper limit reference value, VMIN: Lower reference value, VREF Reference value.

Claims

1. A semiconductor device configured to perform PFM control, at least one timer circuit including a counter circuit for counting clock signals; a first storage circuit configured to store a period value of the timer circuit; A first electrode configured to be connectable to an outside of the semiconductor device; A second electrode configured to be connectable to an outside of the semiconductor device; an analog-to-digital converter circuit configured to receive a signal from the first electrode and convert the signal into a digital signal; an arithmetic circuit configured to receive a conversion result from the A / D conversion circuit; Equipped with the timer circuit is configured to generate a timer signal according to the period value of the first storage circuit; the timer circuit is connected to the second electrode for providing the timer signal; the arithmetic circuit includes a bit processing circuit, and the bit processing circuit is configured to perform a bit processing operation on at least some of the bits of the digital value of the conversion result to generate an update signal indicating an updated period value. Semiconductor device.

2. The bit processing operation is a bit shift operation.

2. The semiconductor device according to claim 1.

3. the arithmetic circuit includes a second storage circuit for storing the digital value; the arithmetic circuit updates the second storage circuit in response to a part or all of the update of the conversion result from the A / D conversion circuit; the arithmetic circuit further includes a third storage circuit that stores a value before updating the conversion result.

3. The semiconductor device according to claim 2.

4. the arithmetic circuit further includes a shift direction specifying circuit that generates a shift direction signal that specifies a shift direction of the bit shift operation based on a sign of a difference between the stored value of the second storage circuit and the stored value of the third storage circuit; the bit processing circuit performs the bit shift operation in accordance with the shift direction signal; 4. The semiconductor device according to claim 3.

5. the arithmetic circuit includes a determination circuit that determines whether or not an absolute value of a difference between the value stored in the second storage circuit and the value stored in the third storage circuit exceeds a shift determination value to generate a determination signal; the bit processing circuit performs the bit shift operation when the determination signal indicates that the absolute value exceeds the shift determination value; the bit processing circuit does not perform the bit shift operation when the determination signal indicates that the absolute value is equal to or less than the shift determination value; The shift determination value represents a minimum difference for which the bit shift operation should be performed.

4. The semiconductor device according to claim 3.

6. the arithmetic circuit includes a difference circuit that generates a difference between the value stored in the second storage circuit and the value stored in the third storage circuit; 4. The semiconductor device according to claim 3.

7. a central processing unit connected to the first storage circuit; the central processing unit is configured to set the period value in the first storage circuit; 2. The semiconductor device according to claim 1.

8. Further comprising an additional timer circuit; the additional timer circuit has a counter circuit for counting the clock signal and an additional storage circuit for storing a period value, and is configured to generate a timer signal having a variable period according to the period value of the additional storage circuit; the A / D conversion circuit is configured to receive a signal from an output of another circuit that operates in response to a timer signal from the additional timer circuit and convert the received signal into a digital value; the A / D conversion circuit is operable in a time-division multiplexing manner to generate update signals for the timer circuit and the additional timer circuit; 2. The semiconductor device according to claim 1.

9. A semiconductor device according to any one of claims 1 to 8, an external circuit that operates in response to the timer signal from the timer circuit and is provided outside the semiconductor device; A control device comprising:

10. the external circuit further includes a power supply circuit and a load circuit connected to an output of the power supply circuit; the signal of the A / D conversion circuit is a voltage signal of a connection node between the power supply circuit and the load circuit; 10. The control device according to claim 9.

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