Tiled-stress-alleviating pad structure

a stress-alleviating pad and tile technology, applied in the field of semiconductor devices, can solve the problems of increasing costs and affecting yield

Inactive Publication Date: 2017-12-14
GLOBALFOUNDRIES U S INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This CTE mismatch may result in significant thermal-mechanical stresses being generated in the metal pad layer and other layers of the 3D-stacked die during the subsequent processing steps, resulting in undesirable delamination and / or cracking of the pad layer which, in turn, may impact yield, and thereby increase costs.

Method used

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Examples

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Embodiment Construction

[0019]Aspects of the application and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting examples illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as not to unnecessarily obscure the application in details. It should be understood, however, that the detailed description and the specific examples, while indicating embodiments of the application, are given by way of illustration only, and not by way of limitation. Various substitutions, modifications, additions and / or arrangements within the spirit and / or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure.

[0020]The application provides, in part, a structure and method for minimizing thermal-mechanical stresses of an integrated circuit. In preferred embodiments, the structure may be used in conjunction within various compo...

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Abstract

Structure and method for reducing thermal-mechanical stresses generated for a semiconductor device are provided, which includes a tiled-stress-alleviating pad structure.

Description

BACKGROUND[0001]The application relates to semiconductor devices and to methods for fabricating semiconductor devices, and more particularly to a method and structure for fabricating a tiled-stress-alleviating pad structure for use, for instance, in back-end-of line (BEOL) and / or far back end of line (FBEOL) semiconductor structures.[0002]As the density of circuits, such as multi-core or application-specific integrated circuits (ASICs), continues to increase, many designers are working towards three-dimensional (3-D) stacked chip technology as an emerging trend in the industry. By way of example, during conventional far back end of the line (FBEOL) processing of 3-D stacked chip fabrication, metal pad layers are traditionally employed to support a controlled collapse chip connection (C4) element and the corresponding ball limiting metallurgy (BLM) layers. Disadvantageously, these pad layers which, for instance, may include, or be fabricated of, aluminum or aluminum alloy, may have a...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L23/00H01L23/528H01L23/31H01L21/3205
CPCH01L23/562H01L21/32051H01L23/5283H01L23/3171H01L2924/14H01L2924/1433H01L2924/13091H01L2224/13101H01L2224/05076H01L2224/05166H01L2224/05171H01L2224/13111H01L2224/13116H01L2224/13139H01L24/05H01L24/13H01L2224/05015H01L2224/05011H01L2224/0501H01L2924/351H01L2224/0361H01L2224/03618H01L2224/0362H01L24/03H01L2924/00012H01L2924/014H01L2924/00014H01L2924/01074H01L2924/01029H01L24/00
InventorMISRA, EKTAFAROOQ, MUKTA G.TUNGA, KRISHNA
OwnerGLOBALFOUNDRIES U S INC