Method for improving erasing speed of SONOS (Silicon Oxide Nitride Oxide Silicon) by utilizing strained silicon technology

Abstract

The invention discloses a method for manufacturing a SONOS unit transistor with high erasing and writing speed. It is characterized in that after forming the sidewalls of the gate on a P-type substrate that forms several shallow trench isolation areas, it also includes the following steps: 1. Precipitate a barrier layer to cover the transistor; Step 2, etch and remove the barrier layer covering the NMOS area to expose the NMOS area; Step 2, etch the silicon in the active areas on both sides of the gate electrode of the NMOS area; Step 3: Precipitate silicon carbide in the active area through a selective epitaxial process; Step 4: Perform high-temperature annealing to cause the silicon carbide to generate tensile stress on the channel. The energy band of silicon is split. The result of the split is that the effective mass of electrons along the channel direction is reduced. At the same time, the energy valley scattering probability of electrons is also reduced, which significantly increases the electron mobility of the SONOS unit transistor, thus improving the hot electron injection mechanism. SONOS programming efficiency and speed.

Description

technical field

[0001] The invention relates to a silicon-silicon oxide-silicon nitride-silicon oxide-silicon (SONOS) memory, in particular to a method for improving the erasing and writing speed of the SONOS by utilizing strained silicon technology. Background technique

[0002] The basic working principle of non-volatile semiconductor memory is to store charge in the gate dielectric of a MOSFET. Devices in which charges are stored in discrete trapping centers in a suitable dielectric layer are called charge-trapping devices. The most common of these devices is silicon-silicon oxide-nitride-silicon oxide-silicon (SONOS) memory.

[0003] The main two storage mechanisms for storing data in flash memory cells are channel hot electron (CHE) injection and F-N tunneling. Channel hot electron injection is considered to be quite reliable after long-term cycling because it does not place significant stress on the tunnel oxide. But the disadvantage of CHE is that the programming e...

Examples

Embodiment Construction

[0024] The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. The specific embodiments described here are only used to explain the present invention, and are not used to limit the protection scope of the present invention.

[0025] combined reference figure 1 and figure 2 , revealing the method of the present invention to improve the erasing and writing speed of SONOS by utilizing the strained silicon technology, figure 1 In the process, after forming the sidewall 102 of the gate 101 on the P-type substrate 104 with several shallow trench isolation regions 105 formed, the following steps are also included:

[0026] Step 1, precipitation barrier layer ( figure 1 not shown) covering the transistor;

[0027] Step 2, etch and remove the barrier layer covering the NMOS region to expose the NMOS region. In this step, first spin-coat photoresist on the barrier layer, and then perform photolithograph...

technical field

[0001] The invention relates to a silicon-silicon oxide-silicon nitride-silicon oxide-silicon (SONOS) memory, in particular to a method for improving the erasing and writing speed of the SONOS by utilizing strained silicon technology. Background technique

[0002] The basic working principle of non-volatile semiconductor memory is to store charge in the gate dielectric of a MOSFET. Devices in which charges are stored in discrete trapping centers in a suitable dielectric layer are called charge-trapping devices. The most common of these devices is silicon-silicon oxide-nitride-silicon oxide-silicon (SONOS) memory.

[0003] The main two storage mechanisms for storing data in flash memory cells are channel hot electron (CHE) injection and F-N tunneling. Channel hot electron injection is considered to be quite reliable after long-term cycling because it does not place significant stress on the tunnel oxide. But the disadvantage of CHE is that the programming e...

Examples

Embodiment Construction

[0024] The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. The specific embodiments described here are only used to explain the present invention, and are not used to limit the protection scope of the present invention.

[0025] combined reference figure 1 and figure 2 , revealing the method of the present invention to improve the erasing and writing speed of SONOS by utilizing the strained silicon technology, figure 1 In the process, after forming the sidewall 102 of the gate 101 on the P-type substrate 104 with several shallow trench isolation regions 105 formed, the following steps are also included:

[0026] Step 1, precipitation barrier layer ( figure 1 not shown) covering the transistor;

[0027] Step 2, etch and remove the barrier layer covering the NMOS region to expose the NMOS region. In this step, first spin-coat photoresist on the barrier layer, and then perform photolithograph...

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