Low leakage isolation unit

Abstract

An isolation cell that clamps a signal that is transmitted from a first power domain that is powered off to a second power domain that is powered on. To reduce leakage current, some circuits and devices are connected to the first power domain or "from" power domain, while other circuits and devices are connected to the second power domain or "to" power domain.

Description

Technical Field

[0001] The present invention generally relates to isolation cells and methods of isolating output signals, and in particular to low leakage isolation cells. Background Art

[0002] The isolation unit is used to isolate the output signal of the shutdown power domain. The output signal of the shutdown power domain may have an intermediate voltage level, so the isolation unit is used to clamp the signal to a specific voltage level before the signal is transmitted to another voltage domain. Figure 1 1 shows a circuit diagram of an existing isolation unit 10. The isolation unit 10 includes a first inverter 12, a logic circuit 14, and a second inverter 16. The first inverter 12 receives an isolation control signal "iso" and generates an inversion "isob" of the signal "iso". The logic circuit 14 is a NAND gate, which receives an input signal "a" from a first power domain, receives an inverted isolation control signal "isob", and provides a logic output signal "sn1". The second inverter 16 is connected to the logic circuit 14 to receive a logic output signal "sn1", and generates an inversion "x" of the output signal "sn1", which can be provided to a second power domain.

[0003] according to Figure 1 The circuit diagram of the isolation unit 10 is as follows: And the truth table of the isolation unit 10 is:

[0004]

[0005] In normal operation, the first and second inverters 12 and 16 and the logic circuit 14 must be powered by the power supply of the second power domain (the "to" power domain), so that when the first power domain (the "from" power domain) is powered off, the isolation unit 10 can still operate normally.

[0006] In stop mode or power-off mode, low leakage is a key feature of integrated circuits and is also required in mobile devices to improve battery life. However, since the first inverter 12, the logic circuit 14, and the PMOS transistors of the second inverter 16 are connected to the power supply voltage of the second power domain (i.e., V ddc ), the isolation unit 10 has a considerable leakage current.

[0007] A low leakage isolation unit is beneficial. Summary of the invention

[0008] This Summary is provided to introduce a selected, simplified version of the concepts that are detailed in the Detailed Description below. This Summary is not intended to identify key or essential features of the claims nor is it intended to limit the scope of the claims.

[0009] In one embodiment, an isolation unit connected between a first circuit module and a second circuit module is provided, wherein the first circuit module and the second circuit module include different power domains, and the isolation unit includes:

[0010] an input terminal configured to receive an input signal from the first circuit module;

[0011] an output terminal configured to provide an output signal to a second circuit module;

[0012] a control terminal configured to receive a control signal, wherein the isolation unit generates the output signal from the input signal in response to the control signal;

[0013] A first power supply terminal for coupling to a first power supply voltage of the first circuit module; and

[0014] A second power supply terminal for coupling to a second power supply voltage of the second circuit module.

[0015] Optionally, the isolation unit further comprises:

[0016] a first inverter having an input terminal coupled to the control terminal to receive the control signal, wherein the first inverter is coupled to the first power terminal to be powered by a first power supply voltage; and

[0017] A second inverter has an output terminal coupled to the output terminal to provide the output signal thereto, wherein the second inverter is powered by a first supply voltage.

[0018] Optionally, the first inverter comprises:

[0019] a first PMOS transistor having a gate coupled to the control terminal to receive the control signal, a source coupled to the first power terminal, and a drain;

[0020] a first NMOS transistor having a gate coupled to the control terminal, a drain coupled to the drain of the first PMOS transistor, and a source; and

[0021] a second NMOS transistor having a gate coupled to the control terminal, a drain coupled to the source of the first NMOS transistor, and a source coupled to ground;

[0022] wherein a node between the drains of the first PMOS transistor and the first NMOS transistor provides an output of the first inverter; and

[0023] The second inverter comprises:

[0024] a second PMOS transistor having a gate coupled to receive the intermediate input signal, a source coupled to the first power supply terminal, and a drain; and

[0025] a third NMOS transistor having a gate coupled to the gate of the second PMOS transistor, a drain coupled to the drain of the second PMOS transistor, and a source coupled to ground;

[0026] A node between the drain of the second PMOS transistor and the drain of the third NMOS transistor is coupled to the output terminal.

[0027] Optionally, the isolation unit further comprises a logic gate coupled to the input terminal and the second power supply terminal, wherein the logic gate comprises:

[0028] a third PMOS transistor having a gate coupled to the input terminal, a source coupled to the second power supply terminal, and a drain coupled to the input terminal of the second inverter;

[0029] a fourth PMOS transistor having a gate coupled to the output terminal of the first inverter, a source coupled to the second power supply terminal, and a drain coupled to the input terminal of the second inverter;

[0030] a fourth NMOS transistor having a gate coupled to the input terminal, a drain coupled to drains of the third PMOS transistor and the fourth PMOS transistor, and a source; and

[0031] a fifth NMOS transistor having a gate coupled to the output terminal of the first inverter, a drain coupled to the source of the fourth NMOS transistor, and a source coupled to ground.

[0032] Optionally, the isolation unit further comprises:

[0033] a first PMOS transistor having a gate coupled to the input terminal, a source coupled to the first power terminal, and a drain;

[0034] a second PMOS transistor having a gate coupled to the control terminal, a source coupled to the drain of the first PMOS transistor, and a drain;

[0035] a first NMOS transistor having a gate coupled to the input terminal, a drain coupled to the drain of the second PMOS transistor, and a source;

[0036] a second NMOS transistor having a gate coupled to the control terminal, a drain coupled to drains of the second PMOS transistor and the first NMOS transistor, and a source; and

[0037] an inverter coupled to the second power supply terminal to receive the second power supply voltage of the second circuit module, the inverter having an input terminal coupled to a node between drains of the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor; and having an output terminal serving as the output terminal of the isolation unit;

[0038] The isolation unit provides a logic 1 signal at the output terminal in response to the control signal at the control terminal.

[0039] Optionally, the inverter comprises:

[0040] a third PMOS transistor having a gate coupled to a node between the second PMOS transistor and the drains of the first and second NMOS transistors, a source coupled to the second power supply terminal, and a drain;

[0041] a third NMOS transistor having a gate coupled to the gate of the third PMOS transistor, a drain coupled to the drain of the third PMOS transistor, and a source;

[0042] A node between the drains of the third PMOS transistor and the third NMOS transistor provides the output signal at the output terminal.

[0043] Optionally, the isolation unit further comprises:

[0044] a first input inverter and a second input inverter connected in series, wherein the first input inverter is coupled to the control terminal to receive the control signal and is coupled to the first power supply terminal to receive the first power supply voltage of the first circuit module, and the second input inverter is coupled to the second power supply terminal to receive the second power supply voltage of the second circuit module;

[0045] a tri-state gate having an input terminal for receiving the input signal and two gate terminals respectively coupled to the output terminals of the first and second input inverters, wherein the tri-state gate is coupled to the first power supply terminal to receive the first power supply voltage of the first circuit module;

[0046] a latch coupled to the second power supply terminal to receive a second power supply voltage of the second circuit module, wherein the latch has an input terminal coupled to an output terminal of the tri-state gate; and

[0047] an output inverter coupled to the second power supply terminal, wherein the output inverter has an input terminal coupled to the output terminal of the latch and an input terminal connected to the output terminal of the isolation unit to provide the output signal;

[0048] The isolation unit provides a maintained signal of the input signal at the output terminal of the isolation unit in response to the control signal.

[0049] Optionally, the first input inverter comprises:

[0050] a first PMOS transistor having a gate coupled to the control terminal, a source coupled to the first power terminal, and a drain;

[0051] a first NMOS transistor having a gate coupled to the control terminal and the gate of the first PMOS transistor, a drain coupled to the drain of the first PMOS transistor, and a source;

[0052] a second NMOS transistor having a gate coupled to the control terminal and the first PMOS transistor, a gate of the first NMOS transistor, a drain coupled to a source of the first NMOS transistor, and a source coupled to ground;

[0053] wherein a node between the drains of the first PMOS transistor and the second NMOS transistor provides an output of the first input inverter; and wherein the second input inverter comprises:

[0054] a second PMOS transistor having a gate coupled to the output terminal of the first input inverter, a source coupled to the second power supply terminal, and a drain;

[0055] a third NMOS transistor having a gate coupled to the output terminal of the first input inverter, a drain coupled to the drain of the second PMOS transistor, and a source;

[0056] a fourth NMOS transistor having a gate coupled to the output terminal of the first input inverter, a drain coupled to the source of the third NMOS transistor, and a source coupled to ground;

[0057] A node between the drains of the second PMOS transistor and the third NMOS transistor provides the output of the second input inverter.

[0058] Optionally, the tri-state gate includes:

[0059] a third PMOS transistor having a gate coupled to the input terminal, a source coupled to the first power terminal, and a drain;

[0060] a fourth PMOS transistor having a gate coupled to the output terminal of the second input inverter, a source coupled to the drain of the third PMOS transistor, and a drain;

[0061] a fifth NMOS transistor having a gate coupled to the input terminal, a source coupled to ground, and a drain; and

[0062] a sixth NMOS transistor having a gate coupled to the output terminal of the first input inverter, a source coupled to the drain of the fifth NMOS transistor, and a drain coupled to the drain of the fourth PMOS transistor;

[0063] A node between the drains of the sixth NMOS transistor and the fourth PMOS transistor provides an output of the tri-state gate.

[0064] Optionally, the latch includes a first latch inverter and a second latch inverter coupled to the second power supply terminal to receive the second power supply voltage of the second circuit module; and wherein the input terminal of the first latch inverter is coupled to the output terminal of the second latch inverter, and the input terminal of the second latch inverter is coupled to the first latch inverter.

[0065] Optionally, the first latch inverter comprises:

[0066] a fifth PMOS transistor having a gate coupled to the output terminal of the tri-state gate, a source coupled to the second power terminal, and a drain;

[0067] a seventh NMOS transistor having a gate coupled to the output terminal of the tri-state gate, a drain coupled to the drain of the fifth PMOS transistor, and a source coupled to ground; wherein a node between the drains of the fifth PMOS transistor and the seventh NMOS transistor provides the output of the first latch inverter.

[0068] Optionally, the second latch inverter comprises:

[0069] a sixth PMOS transistor having a gate coupled to the output terminal of the first latch inverter, a source coupled to the second power supply terminal, and a drain;

[0070] a seventh PMOS transistor having a gate coupled to the output terminal of the first input inverter, a source coupled to the drain of the sixth PMOS transistor, and a drain;

[0071] an eighth NMOS transistor having a gate coupled to the output terminal of the first latch inverter, a source coupled to ground, and a drain; and

[0072] a ninth NMOS transistor having a gate coupled to the output terminal of the second input inverter, a source coupled to the drain of the eighth NMOS transistor, and a drain coupled to the drain of the seventh PMOS transistor;

[0073] A node between the drains of the ninth NMOS transistor and the seventh PMOS transistor provides an output of the second latch inverter and is coupled to the output of the tri-state gate.

[0074] Optionally, the output inverter comprises:

[0075] an eighth PMOS transistor having a gate coupled to the output terminal of the first latch inverter, a source coupled to the second power supply terminal, and a drain; and

[0076] a tenth NMOS transistor having a gate coupled to the output terminal of the first latch inverter, a drain coupled to the drain of the eighth PMOS transistor, and a source coupled to ground;

[0077] A node between drains of the eighth PMOS transistor and the tenth NMOS transistor is coupled to the output terminal of the isolation unit.

[0078] In one embodiment, a method for clamping an input signal from a first power domain to a second power domain is provided, wherein the first power domain operates at a first power supply voltage and the second power domain operates at a second power supply voltage different from the first power supply voltage, the method comprising:

[0079] receiving an input signal from the first power domain at an input terminal;

[0080] receiving a control signal at a control end;

[0081] providing at least one logic gate receiving the input signal and the control signal and generating a logic signal in response to the input signal and the control signal;

[0082] providing an output inverter having an input terminal for receiving the logic signal and having an output terminal for providing an output signal; and

[0083] The at least one logic gate and the output inverter are configured such that one of the at least one logic gate and the output inverter is coupled to the first supply voltage and the other is coupled to the second supply voltage.

[0084] Optionally, the method further comprises:

[0085] providing an input inverter including the control terminal to receive the control signal as an input terminal, wherein the input inverter is for coupling to the first supply voltage, and wherein the input inverter comprises a PMOS transistor, a first NMOS transistor and a second NMOS transistor connected in series between the first supply voltage and ground; and

[0086] providing a NAND gate as the logic gate, the NAND gate coupling the input signal and the output of the input inverter and generating the logic signal, wherein the logic signal is a NAND operation of the input signal and the output of the input inverter; and wherein the NAND gate is used to couple between the second power supply voltage and ground; and

[0087] The output inverter is used to be coupled between the first supply voltage and ground.

[0088] Optionally, the method further comprises:

[0089] A NOR gate is provided as the logic gate, wherein the NOR gate comprises the input terminal for receiving the input signal and the control terminal for receiving the control signal; wherein the NOR gate generates a logic signal as a NOR operation of the input signal and the control signal; and wherein the NOR gate is used to couple between the first power supply voltage and ground; and

[0090] The output inverter is used to be coupled between the second supply voltage and ground.

[0091] Optionally, the method further comprises:

[0092] Providing a first input inverter including the control terminal as an input terminal; wherein the first input inverter includes a first PMOS transistor and first and second NMOS transistors connected in series between the first supply voltage and ground;

[0093] providing a second input inverter having an input coupled to the output of the first input inverter, wherein the second input inverter comprises a second PMOS transistor and third and fourth NMOS transistors connected in series between the second supply voltage and ground;

[0094] Coupling a tri-state gate to the input terminal to receive the input signal, wherein the tri-state gate comprises a third and a fourth PMOS transistor and a fifth and a sixth NMOS transistor connected in series between the first supply voltage and ground; and wherein the gates of the fourth PMOS transistor and the fifth NMOS transistor are coupled to the output terminals of the second input inverter and the first input inverter, respectively;

[0095] coupling a latch to the output of the tri-state gate; wherein the latch is adapted to be coupled between the second supply voltage and ground; and

[0096] The output inverter is coupled to an output terminal of the latch; wherein the output inverter is configured to be coupled between the second supply voltage and ground.

[0097] Optionally, coupling the latch with the output of the tri-state gate comprises:

[0098] coupling a first latched inverter to the output of the tri-state gate; wherein the first latched inverter comprises a fifth PMOS transistor and a seventh NMOS transistor connected in series between the second supply voltage and ground;

[0099] coupling a second latched inverter to the output of the first latched inverter, wherein the second latched inverter comprises a sixth PMOS transistor, a seventh PMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor connected in series; wherein gates of the seventh PMOS transistor and the ninth NMOS transistor are coupled to the output terminals of the first input inverter and the second input inverter, respectively; and

[0100] An output terminal of the second latch inverter is coupled to an input terminal of the first latch inverter.

[0101] In some embodiments, an isolation unit coupled between a first circuit module and a second circuit module is provided, wherein the first and second circuit modules include different power domains, and the isolation unit includes:

[0102] a logic circuit comprising an input terminal for receiving an input signal from the first circuit module and a control terminal for receiving a control signal; wherein the logic circuit provides a logic signal in response to the control signal; and

[0103] an output circuit coupled to the logic circuit to receive the logic signal, wherein the output circuit provides an output signal to the second circuit module;

[0104] One of the logic circuit and the output circuit is used to couple to one of the supply voltages of the first and second circuit modules; and the other of the logic circuit and the output circuit is used to couple to the other of the supply voltages of the first and second circuit modules.

[0105] Optionally, the logic circuit includes one of the following:

[0106] a NAND gate coupled to a supply voltage of the second circuit module and receiving the input signal and an inversion of the control signal;

[0107] a NOR gate for coupling to a supply voltage of the first circuit module and receiving the input signal and the control signal; and

[0108] A latch circuit is provided for coupling to a supply voltage of the first circuit module. BRIEF DESCRIPTION OF THE DRAWINGS

[0109] The embodiments of the present invention will be further described below with reference to the accompanying drawings, wherein:

[0110] Figure 1 is a circuit diagram of an existing isolation unit 10;

[0111] Figure 2 is a circuit diagram of an isolation unit according to a first embodiment of the present invention;

[0112] Figure 3 is a circuit diagram of an isolation unit according to a second embodiment of the present invention; and

[0113] Figure 4 is a circuit diagram of an isolation unit according to a third embodiment of the present invention. DETAILED DESCRIPTION

[0114] Figure 2 is an isolation unit according to a first exemplary embodiment of the present invention. Figure 1 The structure of the isolation unit 10 is similar, and the isolation unit 20 includes a first inverter 22, a logic circuit 24, and a second inverter 26. The first inverter 22 receives the isolation control signal "iso" and inverts it to provide it to the logic circuit 24. The first inverter 22 is also called an input inverter. The logic circuit 24 receives an input signal "a" from a first power domain or a "from" power domain, and provides a logic output signal to the second inverter 26. The second inverter 26 then provides an output signal "x" as the output signal of the isolation unit 20. The second inverter 26 is also called an output inverter.

[0115] The input inverter 22 includes a first PMOS transistor 222, a first NMOS transistor 224, and a second NMOS transistor 226. Each transistor is connected in series to a first voltage V dd_from and ground (Vss), the gates of the transistors 222, 224, and 226 receive an isolation control signal "iso", wherein the first voltage V dd_from is the supply voltage of the first power domain or the "from" power domain. The output of the input transistor 22 is provided at a node between the drains of the first PMOS transistor 222 and the first NMOS transistor 224. It should be noted that the existing isolation unit 10 does not include the second NMOS transistor 226, and its inverter 12 is connected to the supply voltage of the "to" power domain.

[0116] If the isolation control signal "iso" is logic "1", the first PMOS transistor 222 is turned off, so that the output of the first inverter 22 is logic "0". The additional NMOS transistor 226 does not affect the switching of the first inverter 22. If the isolation control signal "iso" is logic "0", the first PMOS transistor 222 is turned on, and the first NMOS transistor 224 and the additional NMOS transistor 226 are turned off, so that the leakage of the first PMOS transistor 222 is cut off. The additional NMOS transistor 226 reduces or eliminates the leakage of the first inverter 22.

[0117] If the isolation unit 20 is provided as an operating unit or a functional unit, the first power supply terminal V dd_from coupled to the supply voltage of the first power domain; if the isolation unit 20 is provided as a backup unit, the first power terminal V dd_from The first power domain is floating and is configured to be coupled to a supply voltage of the first power domain.

[0118] Logic circuit 24 is a NAND gate, which is similar to Figure 1 The logic circuit 14 includes a second PMOS transistor 242 and a third PMOS transistor 244, and includes a third NMOS transistor 246 and a fourth NMOS transistor 248. The source terminals of the second and third PMOS transistors 242 and 244 are coupled to the second power supply terminal V dd_to The second power supply terminal V dd_to The supply voltage (V dd_to ). If the isolation unit 20 is provided as a functional unit, the second power supply terminal V dd_to coupled to the power supply of the second signal module; if the isolation unit 20 is provided as a backup unit, the second power supply terminal V dd_to Floating and configured to be coupled to a supply voltage of a second power domain.

[0119] The second inverter 26 and Figure 1 The second inverter 16 in FIG. 1 is similar to the second inverter 16 in FIG. 1 , and includes a fourth PMOS transistor 262 and a fifth NMOS transistor 264. The source of the fourth PMOS transistor 262 is coupled to the supply voltage V dd_from If the isolation unit 20 is provided as a functional unit, the first power supply terminal V dd_from coupled to the supply voltage of the first power domain; if the isolation unit 20 is provided as a backup unit, the first power terminal V dd_from The first power domain is floating and is configured to be coupled to a supply voltage of the first power domain.

[0120] Figure 2 Also shown is the power supply terminal V dd_rail, which is the voltage of the signal module, which depends on the "position" of the isolation unit 20. The "position" mentioned here does not necessarily refer to the physical position of the isolation unit 20, but also applies to the electrical connection of the isolation unit 20. For example, when the isolation unit 20 is located in (or connected to) the first power domain, the first power terminal V dd_from is coupled to or can be coupled to the power supply terminal V dd_rail On the other hand, when the isolation unit 20 is located in (or connected to) the second power domain, the second power terminal V dd_to is coupled to or can be coupled to the power supply terminal V dd_rail .

[0121] The truth table of the isolation unit 20 is the same as Figure 1 The truth table of the isolation unit 10 is the same as that of the isolation unit 10. In response to the isolation control signal "iso" being logic "1", the isolation unit 20 provides an output signal "x" of logic "0" at its output terminal. Further, if the isolation control signal "iso" is logic "1", the first PMOS transistor 222 of the first inverter 22 and the fourth PMOS transistor 262 of the second inverter 26 are turned off. Since the supply voltage of the first power domain is turned off (powered off) in the isolation mode, no leakage occurs in the first inverter 22 and the second inverter 26, which means that Figure 1 Compared with the isolation unit 10 in the embodiment of the present invention, at least 50% of leakage is saved. In addition, since the PMOS transistor of the isolation unit 20 can be coupled with the supply voltage in the first power domain and / or the second power domain, the isolation unit 20 can have more "position" flexibility during physical wiring.

[0122] Figure 3 Another embodiment of the isolation unit 30 is shown. The isolation unit 20 includes a logic circuit 32 and an inverter 34. The logic circuit 32 implements a NOR gate, which receives an input signal "a" and an isolation control signal "iso". The inverter 34 is coupled to an output of the logic circuit 32 to receive the logic signal provided by the logic circuit 32. The inverter 34 provides an inversion of the logic signal as an output signal "x" of the isolation unit 30.

[0123] The logic circuit 32 includes a first PMOS transistor 322, a second PMOS transistor 324, a first NMOS transistor 326, and a second NMOS transistor 328. The gates of the first PMOS transistor 322 and the first NMOS transistor 326 are coupled to receive the input signal "a". The source of the first PMOS transistor 322 is coupled to the first power supply terminal V dd_from, the drain of the first PMOS transistor 322 is coupled to the source of the second PMOS transistor 324. The gates of the second PMOS transistor 324 and the second NMOS transistor 328 are coupled to receive the isolation control signal "iso". The drains of the second PMOS transistor 324 and the second NMOS transistor 328 are coupled together to provide the output logic signal of the logic circuit 32. The sources of the first NMOS transistor 326 and the second NMOS transistor 328 are coupled to another supply voltage V ss (land).

[0124] Inverter 34 and Figure 1 The output of inverter 16, Figure 2 The output inverter 34 receives the logic signal provided by the logic circuit 32 and provides its inversion, which is output as the output signal "x" of the isolation unit 30. The output inverter 34 includes a third PMOS transistor 342 and a third NMOS transistor 344. The third PMOS transistor is coupled to the second power supply terminal V dd_to , the third NMOS transistor 344 is coupled to ground (V ss ).

[0125] Depend on Figure 3 The logic expression of the isolation unit 30 is: iso, and the truth table of the isolation unit 30 is:

[0126]

[0127] and Figure 2 The power supply terminal V dd_rail Similarly, when the isolation unit 30 is located in the first power domain, the power terminal V dd_rail Provides the voltage of the first power domain, or when the isolation unit 30 is located in the second power domain, the power supply terminal V dd_rail The logic circuit 32 and the output inverter 34 are coupled to different supply voltages, so that when the isolation control signal “iso” is logic high and the second PMOS transistor 324 is turned off, the voltage V provided to the logic circuit 32 dd_from is from a powered-off power domain, so there is no leakage in the logic circuit 32. Figure 2 Similar to the isolation unit 20 in FIG. 1 , the couplability of the first and second power supply terminals makes the isolation unit 30 flexible in position, which means that the isolation unit 30 can be located in the first power supply domain or the second power supply domain.

[0128] Figure 4An isolation unit 40 according to another embodiment of the present invention is shown. The isolation unit 40 includes a first input inverter 41 , a second input inverter 42 , a tri-state gate 44 , a first latch inverter 45 , a second latch inverter 46 , and an output inverter 48 .

[0129] The first input inverter 41 and Figure 2 The first input inverter 41 is similar to the first inverter 22 in FIG. 1 , and includes a first PMOS transistor 412, a first NMOS transistor 414, and a second NMOS transistor or an additional NMOS transistor 416. The first input inverter 41 receives the isolation control signal “iso” and provides an inverse “ison” of the isolation control signal “iso” at a node between the drains of the first PMOS transistor 412 and the first NMOS transistor 414. The first input inverter 41 is coupled to the first power supply terminal V dd_from and ground (V ss ), wherein the first power supply terminal V dd_from will be connected to the supply voltage of the first power domain (V dd_from ) are coupled.

[0130] The second input inverter 42 is coupled to the first input inverter 41 to receive its output signal “ison” from the first input inverter 41. The second input inverter 42 is similar to the first input inverter 41 and includes a second PMOS transistor 422, a third NMOS transistor 424, and an additional fourth NMOS transistor 426. The second input inverter 42 provides an inversion “isop” of the output signal “ison” of the first input inverter 41. The second input inverter 42 is coupled to a second power supply terminal V dd_to , the second power supply terminal V dd_to The supply voltage (V dd_to ).

[0131] The tri-state gate 44 includes four transistors connected in series, namely a third PMOS transistor 442, a fourth PMOS transistor 444, a fifth NMOS transistor 446, and a sixth NMOS transistor 448. The source of the third PMOS transistor 442 is coupled to the first power supply terminal, which is coupled to the supply voltage (V dd_from). The gate of the third PMOS transistor 442 is coupled to receive the input signal "a". The drain of the third PMOS transistor 442 is coupled to the source of the fourth PMOS transistor 444. The gate of the fourth PMOS transistor 444 is coupled to receive the output signal "isop" of the second input inverter 42. The drain of the fourth PMOS transistor is coupled to the drain of the sixth NMOS transistor 448. The source of the sixth NMOS transistor 448 is coupled to the drain of the fifth NMOS transistor. The gate of the sixth NMOS transistor 448 is coupled to receive the output signal "ison" of the first input inverter 41. The source of the fifth NMOS transistor 446 is coupled to the ground (V ss ). The gate of the fifth NMOS transistor 446 is coupled to the gate of the third PMOS transistor 442 to receive the input signal “a”. The node between the drains of the fourth PMOS transistor 444 and the sixth NMOS transistor 448 provides the output signal of the tri-state gate 44.

[0132] The first latch inverter 45 and Figure 1 , 2 The output inverters 16, 26, and 24 in FIG. 3 are similar. The first latched inverter 45 includes a fifth PMOS transistor 452 coupled to the second power supply terminal V dd_to and a seventh NMOS transistor 454. A node between the drains of the fifth PMOS transistor 452 and the seventh NMOS transistor 454 provides an output signal of the first latched inverter 45.

[0133] The second latch inverter 46 is similar to the tri-state gate 44, and includes transistors connected in series, namely a sixth PMOS transistor 462, a seventh PMOS transistor 464, an eighth NMOS transistor 466, and a ninth NMOS transistor 468. The gate of the seventh PMOS transistor 464 receives the output signal "ison" of the first input inverter 41, and the gate of the ninth NMOS transistor 468 receives the output signal "isop" of the second input inverter 42. The node between the drains of the seventh PMOS transistor 464 and the ninth NMOS transistor 468 provides the output signal of the second latch inverter 46. The first latch inverter 45 and the second latch inverter 46 generally constitute a latch to store the signal at the output end of the tri-state gate 44 and provide the stored signal at the output end of the first latch inverter 45.

[0134] The tri-state gate 44, the first latch inverter 45, and the second latch inverter 46 are provided as a logic gate or latch circuit to provide a holding signal of the input signal "a" in response to the isolation control signal "iso". Before being provided to the latch loop composed of the first latch inverter 45 and the second latch inverter 46, the input signal "a" is inverted by the tri-state gate 44. The output of the first latch inverter 45 is provided to the second latch inverter 46, and the output of the second latch inverter 46 is provided to the first latch inverter 45, so that the first and second latch inverters 45 and 46 latch the input signal "a". If the isolation control signal "iso" is logic "1", the output signal "ison" of the first input inverter 41 is logic "0", and the output signal "isop" of the second input inverter 42 is logic "1". Therefore, the input signals "ison" and "isop" turn off the fourth PMOS transistor 444 and the sixth NMOS transistor 448 of the tri-state gate 44. It should be understood that when the isolation control signal is logic “1”, the first power domain is powered off, and the turning off of the fourth PMOS transistor 444 and the sixth NMOS transistor 448 does not cause any leakage of the tri-state gate 44. Further, the output signal “ison” of logic “0” and the output signal “isop” of logic “1” turn on the seventh PMOS transistor 464 and the ninth NMOS transistor 468 of the second latch inverter 46, so that the held input signal can be provided to the output inverter 48.

[0135] The output inverter 48 is similar to the first latch inverter 45, and includes an eighth PMOS transistor 482 and a tenth NMOS transistor 484 connected in series therewith. The output inverter 48 is connected to the second power supply terminal V dd_to and ground (V ss ), the second power supply terminal V dd_to The node between the drains of the PMOS transistor 482 and the NMOS transistor 484 provides the output signal "x" of the isolation unit 40. The output signal "x" of the isolation unit 40 is a maintained signal of the input signal "a".

[0136] It can be seen that the various embodiments of the present invention provide an isolation unit for isolating and clamping a signal transmitted from a first power domain to a second power domain. The isolation unit includes at least one logic circuit and an input circuit. One of the logic circuit and the output circuit is coupled to the supply voltage of one of the first and second power domains, and the other of the logic circuit and the output circuit is coupled to the supply voltage of the other of the first and second power domains. The logic circuit receives an isolation control signal and an input signal from the first power domain, and the isolation control signal may indicate a power-off state of the first power domain. For one of the logic circuit and the output circuit coupled to the supply voltage of the first power domain, when the isolation control signal is enabled, the supply voltage of the first power domain is cut off, so that no leakage occurs in the circuit. The isolation unit thus saves at least 50% of leakage current compared to existing isolation units.

[0137] Various exemplary embodiments are described herein with reference to specific illustrated examples. The illustrative examples are selected to assist those skilled in the art to form a clear understanding of and implement the various embodiments. However, the scope of systems, structures, and devices that can be constructed to include one or more embodiments, as well as the scope of methods implemented according to one or more embodiments, are not limited by the illustrative examples shown. On the contrary, those skilled in the art will understand based on this specification that many other configurations, structures, and methods can be implemented according to the various embodiments.

[0138] It should be understood that, with respect to the various positional indications used in the foregoing description of the present invention, such as top, bottom, upper, and lower, those indications are given only with reference to the corresponding drawings, and other positional relationships may be substituted when the orientation of the device changes during manufacture or operation. As mentioned above, those positional relationships are described only for the sake of clarity and are not limiting.

[0139] The foregoing description of this specification is with reference to specific embodiments and specific drawings, but the invention should not be limited thereto, but should be given by the claims. The various drawings described are exemplary and non-restrictive. In the drawings, the dimensions of the various elements may be exaggerated for illustrative purposes and may not be drawn to a specific scale. This description should also include discontinuous changes in tolerances and properties of various components and working methods. Various weakened implementations of the invention should also be included.

[0140] The word "comprising" as used in the present description and claims does not exclude other elements or steps. Unless otherwise specified, when the singular form such as "a", "an" is used to refer to a definite or indefinite element, the plural form of the element shall be included. Thus, the word "comprising" should not be understood as being limited to the items listed thereafter, nor should it be understood as excluding other elements or steps; the scope of the description "a device comprises items A and B" should not be limited to a device comprising only elements A and B. The description indicates that, for the purpose of this description, only elements A and B of the device are relevant.

[0141] It will be apparent to those skilled in the art that various detailed changes may be made without departing from the scope of the claims of the present invention.

Claims

1. An isolation unit connected between a first circuit module and a second circuit module, wherein the first circuit module and the second circuit module include different power domains, characterized in that: The isolation unit comprises: an input terminal configured to receive an input signal from the first circuit module; an output terminal configured to provide an output signal to a second circuit module; a control terminal configured to receive a control signal, wherein the isolation unit generates the output signal from the input signal in response to the control signal; a first power supply terminal for coupling to a first power supply voltage of the first circuit module; a second power supply terminal for coupling to a second power supply voltage of the second circuit module; a first inverter having an input terminal coupled to the control terminal to receive the control signal, wherein the first inverter is coupled to the first power terminal to be powered by a first power supply voltage; and a second inverter having an output terminal coupled to the output terminal to provide the output signal thereto, wherein the second inverter is powered by a first supply voltage; The first inverter comprises: a first PMOS transistor having a gate coupled to the control terminal to receive the control signal, a source coupled to the first power terminal, and a drain; a first NMOS transistor having a gate coupled to the control terminal, a drain coupled to the drain of the first PMOS transistor, and a source; and a second NMOS transistor having a gate coupled to the control terminal, a drain coupled to the source of the first NMOS transistor, and a source coupled to ground; wherein a node between the drains of the first PMOS transistor and the first NMOS transistor provides an output of the first inverter; and The second inverter comprises: a second PMOS transistor having a gate coupled to receive the intermediate input signal, a source coupled to the first power supply terminal, and a drain; and a third NMOS transistor having a gate coupled to the gate of the second PMOS transistor, a drain coupled to the drain of the second PMOS transistor, and a source coupled to ground; A node between the drain of the second PMOS transistor and the drain of the third NMOS transistor is coupled to the output terminal.

2. The isolation unit according to claim 1, characterized in that: The isolation unit further includes a logic gate coupled to the input terminal and the second power supply terminal, wherein the logic gate includes: a third PMOS transistor having a gate coupled to the input terminal, a source coupled to the second power supply terminal, and a drain coupled to the input terminal of the second inverter; a fourth PMOS transistor having a gate coupled to the output terminal of the first inverter, a source coupled to the second power supply terminal, and a drain coupled to the input terminal of the second inverter; a fourth NMOS transistor having a gate coupled to the input terminal, a drain coupled to drains of the third PMOS transistor and the fourth PMOS transistor, and a source; and a fifth NMOS transistor having a gate coupled to the output terminal of the first inverter, a drain coupled to the source of the fourth NMOS transistor, and a source coupled to ground.

3. An isolation unit connected between a first circuit module and a second circuit module, wherein the first circuit module and the second circuit module include different power domains, characterized in that: The isolation unit comprises: an input terminal configured to receive an input signal from the first circuit module; an output terminal configured to provide an output signal to a second circuit module; a control terminal configured to receive a control signal, wherein the isolation unit generates the output signal from the input signal in response to the control signal; a first power supply terminal for coupling to a first power supply voltage of the first circuit module; a second power supply terminal for coupling to a second power supply voltage of the second circuit module; a first PMOS transistor having a gate coupled to the input terminal, a source coupled to the first power terminal, and a drain; a second PMOS transistor having a gate coupled to the control terminal, a source coupled to the drain of the first PMOS transistor, and a drain; a first NMOS transistor having a gate coupled to the input terminal, a drain coupled to the drain of the second PMOS transistor, and a source; a second NMOS transistor having a gate coupled to the control terminal, a drain coupled to drains of the second PMOS transistor and the first NMOS transistor, and a source; and an inverter coupled to the second power supply terminal to receive the second power supply voltage of the second circuit module, the inverter having an input terminal coupled to a node between drains of the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor; and having an output terminal serving as the output terminal of the isolation unit; The isolation unit provides a logic 1 signal at the output terminal in response to the control signal at the control terminal.

4. An isolation unit for connecting between a first circuit module and a second circuit module, wherein the first circuit module and the second circuit module include different power domains, characterized in that: The isolation unit comprises: an input terminal configured to receive an input signal from the first circuit module; an output terminal configured to provide an output signal to a second circuit module; a control terminal configured to receive a control signal, wherein the isolation unit generates the output signal from the input signal in response to the control signal; a first power supply terminal for coupling to a first power supply voltage of the first circuit module; a second power supply terminal for coupling to a second power supply voltage of the second circuit module; a first input inverter and a second input inverter connected in series, wherein the first input inverter is coupled to the control terminal to receive the control signal and is coupled to the first power supply terminal to receive the first power supply voltage of the first circuit module, and the second input inverter is coupled to the second power supply terminal to receive the second power supply voltage of the second circuit module; a tri-state gate having an input terminal for receiving the input signal and two gate terminals respectively coupled to the output terminals of the first and second input inverters, wherein the tri-state gate is coupled to the first power supply terminal to receive the first power supply voltage of the first circuit module; a latch coupled to the second power supply terminal to receive a second power supply voltage of the second circuit module, wherein the latch has an input terminal coupled to an output terminal of the tri-state gate; and an output inverter coupled to the second power supply terminal, wherein the output inverter has an input terminal coupled to the output terminal of the latch and an input terminal connected to the output terminal of the isolation unit to provide the output signal; The isolation unit provides a maintained signal of the input signal at the output terminal of the isolation unit in response to the control signal.

5. A method for clamping an input signal from a first power domain to a second power domain, characterized in that: The first power domain operates at a first power supply voltage, and the second power domain operates at a second power supply voltage different from the first power supply voltage, and the method includes: receiving an input signal from the first power domain at an input terminal; receiving a control signal at a control end; providing at least one logic gate receiving the input signal and the control signal and generating a logic signal in response to the input signal and the control signal; providing an output inverter having an input terminal for receiving the logic signal and having an output terminal for providing an output signal; and configuring the at least one logic gate and the output inverter so that one of the at least one logic gate and the output inverter is coupled to the first supply voltage and the other is coupled to the second supply voltage; The method further comprises: providing an input inverter including the control terminal to receive the control signal as an input terminal, wherein the input inverter is for coupling to the first supply voltage, and wherein the input inverter comprises a PMOS transistor, a first NMOS transistor and a second NMOS transistor connected in series between the first supply voltage and ground; and providing a NAND gate as the logic gate, the NAND gate coupling the input signal and the output of the input inverter and generating the logic signal, wherein the logic signal is a NAND operation of the input signal and the output of the input inverter; and wherein the NAND gate is used to couple between the second power supply voltage and ground; and The output inverter is used to be coupled between the first supply voltage and ground.

6. A method for clamping an input signal from a first power domain to a second power domain, characterized in that: The first power domain operates at a first power supply voltage, and the second power domain operates at a second power supply voltage different from the first power supply voltage, and the method includes: receiving an input signal from the first power domain at an input terminal; receiving a control signal at a control end; providing at least one logic gate receiving the input signal and the control signal and generating a logic signal in response to the input signal and the control signal; providing an output inverter having an input terminal for receiving the logic signal and having an output terminal for providing an output signal; and configuring the at least one logic gate and the output inverter so that one of the at least one logic gate and the output inverter is coupled to the first supply voltage and the other is coupled to the second supply voltage; Characterized in that the method further comprises: Providing a first input inverter including the control terminal as an input terminal; wherein the first input inverter includes a first PMOS transistor and first and second NMOS transistors connected in series between the first supply voltage and ground; providing a second input inverter having an input coupled to the output of the first input inverter, wherein the second input inverter comprises a second PMOS transistor and third and fourth NMOS transistors connected in series between the second supply voltage and ground; Coupling a tri-state gate to the input terminal to receive the input signal, wherein the tri-state gate comprises a third and a fourth PMOS transistor and a fifth and a sixth NMOS transistor connected in series between the first supply voltage and ground; and wherein the gates of the fourth PMOS transistor and the fifth NMOS transistor are coupled to the output terminals of the second input inverter and the first input inverter, respectively; coupling a latch to the output of the tri-state gate; wherein the latch is adapted to be coupled between the second supply voltage and ground; and The output inverter is coupled to an output terminal of the latch; wherein the output inverter is configured to be coupled between the second supply voltage and ground.

7. The method according to claim 6, characterized in that The coupling of the latch to the output of the tri-state gate comprises: coupling a first latched inverter to the output of the tri-state gate; wherein the first latched inverter comprises a fifth PMOS transistor and a seventh NMOS transistor connected in series between the second supply voltage and ground; coupling a second latched inverter to the output of the first latched inverter, wherein the second latched inverter comprises a sixth PMOS transistor, a seventh PMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor connected in series; wherein gates of the seventh PMOS transistor and the ninth NMOS transistor are coupled to the output terminals of the first input inverter and the second input inverter, respectively; and An output terminal of the second latch inverter is coupled to an input terminal of the first latch inverter.

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