Coaxial interconnect structures for semiconductor components

Abstract

The present invention relates to a coaxial interconnect structure for semiconductor components, and in particular describes a coaxial interconnect structure integrated into a semiconductor component and a method for forming the coaxial interconnect structure. The coaxial interconnect structure electrically couples a circuit of an integrated circuit (IC) die to a trace of a package substrate, and includes a signal core extending around an axis, a ground shield extending around the axis, and an insulator disposed between the signal core and the ground shield.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to U.S. Provisional Patent Application No. 62 / 623,416, filed on January 29, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to coaxial interconnect structures for semiconductor components. Background Art

[0004] The background description provided herein is for the purpose of generally presenting the context in which the present disclosure applies. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims of the present disclosure and are not admitted to be prior art by inclusion in this section.

[0005] In the wireless network industry, semiconductor components may operate at high-speed frequencies exceeding, for example, 2.4 GHz. To accommodate such high-speed frequencies and improve the signal performance of semiconductor components, the package substrate or integrated circuit (IC) die of the semiconductor component may incorporate a structure including a ground plane or ground trace.

[0006] Semiconductor components may also include interconnect structures in the form of conductive pillars. Such interconnect structures are typically fabricated directly on the pads of the IC die, serving as a mechanism for attaching the IC die to the substrate, and also providing a channel for signals emitted from the circuits of the IC die. Today, design and manufacturing techniques associated with interconnect structures expose adjacent interconnect structures to each other. Contrary to efforts associated with incorporating ground planes or ground traces in portions of semiconductor components, the exposed nature of the interconnect structure can cause signal degradation due to signal loss or signal interference. Summary of the invention

[0007] This summary is provided to introduce subject matter that is further described in the detailed description and drawings. Therefore, this summary should not be considered to describe essential features nor is it intended to limit the scope of the claimed subject matter.

[0008] The present disclosure describes a coaxial interconnect structure integrated into a semiconductor component and a method of forming the coaxial interconnect structure. The coaxial interconnect structure electrically couples the circuit of an integrated circuit (IC) die to the traces of a package substrate, including a signal core extending around an axis, a ground shield extending around the axis, and an insulator disposed between the signal core and the ground shield.

[0009] In some aspects, a semiconductor component is described. The semiconductor component includes: a packaging substrate having corresponding signal traces and ground traces formed by independent conductive layers of the packaging substrate; an integrated circuit (IC) die having signal pads and ground pads; and a coaxial interconnect structure that electrically couples the signal pads and ground pads of the IC die to the corresponding signal traces and ground traces of the packaging substrate. The coaxial interconnect structure includes a signal core extending around an axis, the axis (i) being orthogonal to a plane of the IC die containing the signal pads and ground pads and (ii) being orthogonal to a plane of the packaging substrate containing the corresponding signal traces and ground traces. The coaxial interconnect structure also includes a ground shield extending around the axis and arranged to surround the perimeter of the signal core, and an insulator arranged between the signal core and the ground shield.

[0010] In other aspects, a semiconductor component is described. The semiconductor component includes: a packaging substrate having corresponding signal traces and ground traces formed by a common conductive layer of the packaging substrate; an integrated circuit (IC) die having signal pads and ground pads; and a coaxial interconnect structure that electrically couples the signal pads and ground pads of the IC die to the corresponding signal traces and ground traces of the packaging substrate. The coaxial interconnect structure includes a signal core extending around an axis, the axis (i) being orthogonal to a plane of the IC die containing the signal pads and ground pads and (ii) being orthogonal to a plane of the packaging substrate containing the corresponding signal traces and ground traces. The coaxial interconnect structure also includes a ground shield extending around the axis and disposed as a portion of a perimeter surrounding the signal core and an insulator disposed between the signal core and the ground shield.

[0011] In other aspects, a method of forming a coaxial interconnect structure is described. The method includes: depositing a first conductive material on a material stack including a signal interconnect pad; and depositing a first coating of a photoresist material on the first conductive material. A portion of the first conductive material is exposed via a first photolithography operation including irradiating and removing the same portion of the first coating of the photoresist material. A second conductive material is deposited on the exposed portion of the first conductive material. The remaining portion of the first coating of the photoresist material is removed to expose a portion of the first conductive material, and the exposed portion of the first conductive material is etched to obtain a signal core extending around an axis. A dielectric material is deposited on the material stack including the signal core, and a second coating of the photoresist material is deposited on the dielectric material. A portion of the dielectric material is exposed via a second photolithography operation including irradiating and removing the same portion of the second coating of the photoresist material. The exposed portion of the dielectric material is removed, and the remaining portion of the second coating of the photoresist material is removed to obtain an insulator extending around the axis. A third conductive material is deposited on the material stack including the signal core and the insulator, and a third coating of the photoresist material is deposited on the third conductive material. A portion of the third conductive material is exposed via a third photolithography operation including irradiation and removal of the same portion of the third coating of the photoresist material. The exposed portion of the third conductive material is removed, and the remaining portion of the third coating of the photoresist material is removed to obtain a ground shield extending around the axis. The signal core, the insulator, and the ground shield are then polished to obtain a coaxial interconnect structure.

[0012] The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The following describes the details of one or more aspects of the coaxial interconnect structure. The same reference numerals may be used in the specification and drawings to indicate similar elements:

[0014] Figure 1 An exemplary operating environment for fabricating semiconductor components having a coaxial interconnect structure according to one or more implementations is shown.

[0015] Figure 2 Details of an exemplary coaxial interconnect structure are shown in accordance with one or more implementations.

[0016] Figure 3 Details of another example coaxial interconnect structure are shown in accordance with one or more implementations.

[0017] Figures 4a to 4c An exemplary method for fabricating an integrated circuit die to have a coaxial interconnect structure is shown in accordance with one or more implementations.

[0018] Figure 5a to Figure 5f Exemplary details of a cross section of an integrated circuit die having a coaxial interconnect structure during different stages of fabrication are shown in accordance with one or more implementations. DETAILED DESCRIPTION

[0019] As part of manufacturing semiconductor components, an integrated circuit (IC) die may be combined with a package substrate (sometimes referred to as an interposer) during an assembly manufacturing process to obtain a semiconductor component. An interconnect structure of the semiconductor component electrically couples the die to the package substrate for propagating signals between the IC die and the package substrate. In certain cases, the interconnect structure includes conductive bonding wires that connect pads of the IC die to pads of the package substrate, while in other cases, the interconnect structure may be a bump in the form of a column or solder ball that connects pads of the IC die to pads of the substrate.

[0020] Bond wires may be fabricated using materials such as aluminum (Al), copper (Cu), silver (Ag), or gold (Au). However, due to their length, bond wires are susceptible to signal loss due to parasitic effects associated with inductance.

[0021] The pillars may be made of materials such as copper (Cu). Generally, the pillars have improved high frequency signal performance compared to bonding wires, in part due to their reduced length. However, as part of the conventional semiconductor component manufacturing process, during the wafer manufacturing process or the package assembly process, these pillars are exposed to adjacent pillars, causing each pillar to experience interference or "crosstalk" from the corresponding adjacent pillar.

[0022] A novel interconnect structure that relies on semiconductor manufacturing processes combines a signal core, a dielectric, and a shield as part of a coaxial signal mechanism disposed between an integrated circuit (IC) die and a package substrate. The coaxial interconnect structure achieves improved signaling performance for high-frequency signals that can be used as part of a semiconductor component operating at high frequencies (e.g., ≥2.4 GHz). The present disclosure describes methods and apparatus for manufacturing such a coaxial interconnect structure as part of a semiconductor component.

[0023] Operating Environment

[0024] Figure 1 An exemplary operating environment 100 for fabricating semiconductor components having a coaxial interconnect structure is shown in accordance with one or more implementations.

[0025] As shown, semiconductor wafer fabrication facility 102 includes a semiconductor wafer fabrication tool group. The semiconductor wafer fabrication tool group includes an electroplating tool 104, a photolithography exposure tool 106, and an etching tool 108. Generally, the semiconductor wafer fabrication tool group can perform a sequence of fabrication process steps on a semiconductor wafer 110.

[0026] The semiconductor components 112 may be assembled to include an integrated circuit (IC) die 114 having one or more coaxial interconnects 116. Examples of IC dies 114 typically associated with very large scale integrated circuit (VLSI) circuits include logic dies, application specific integrated circuit (ASIC) dies, system on chip (SoC) dies, memory dies (such as dynamic random access memory (DRAM) dies or flash memory dies), etc. In one aspect, a sequence of manufacturing process steps utilizing an electroplating tool 104, a photolithography exposure tool 106, and an etching tool 108 may fabricate the coaxial interconnects 116 on a plurality of IC dies 114 included on the semiconductor wafer 110 before the semiconductor wafer 110 is diced for assembly into a plurality of semiconductor components 112.

[0027] Typically, the electroplating tool 104 can use an electrochemical deposition process to deposit or "grow" various metals on the exposed metal of the IC die 114. The exposed metal (sometimes referred to as seed metal or under-bump metallization (UBM) metal) is typically a conductive metal in the form of a pad that provides a corresponding conductive path to the circuit of the IC die 114. Examples of metals that can be deposited by the electroplating tool 104 include copper (Cu), gold (Au), nickel (Ni), palladium (Pd), silver (Ag), and tin (Sn). The electroplating tool 104 can deposit materials used in the construction of the coaxial interconnect 116, including materials that can be used for signal cores or ground shields.

[0028] Other deposition tools (not shown) may also be used to deposit materials on the semiconductor wafer 110. Other deposition tools include chemical vapor deposition (CVD) tools, physical vapor deposition (PVD) tools, and sputtering tools. In certain cases, other deposition tools may deposit dielectric materials on the semiconductor wafer, while in other cases, other deposition tools may be used instead of the electroplating tool 104 to deposit the above-mentioned metals.

[0029] Typically, the photolithography exposure tool 106 exposes or radiates energy or particles (such as ultraviolet (UV), extreme ultraviolet (EUV) light, electron beams, ion beams, or x-ray electromagnetic waves) through a patterned photolithography mask onto a thin film of photoresist material coating the semiconductor wafer 110. As received by the photoresist film, a pattern corresponding to the patterned photolithography mask may be developed by a development tool (not shown) to mask portions of material (e.g., material deposited by the electroplating tool 104) from processes including removal via an etching manufacturing process. The operations performed by the photolithography exposure tool 106 may actually mask features from being etched during construction of the coaxial interconnect 116.

[0030] In general, the etching tool 108 removes exposed (e.g., unmasked) portions of material to obtain features corresponding to the pattern developed as part of the operation performed by the photolithography exposure tool 106. The etching tool 108 can remove the exposed portions of the material via a dry etching process, a wet etching process, etc. The etchant used by the etching tool 108 can be adjusted to react with one or more materials (e.g., etch one or more materials) while remaining benign to other materials (e.g., not etching). The etching tool 108 can be used to etch features that define the coaxial interconnect 116 during the construction of the coaxial interconnect 116.

[0031] Multiple operations of plating, exposure, and etching may be performed within the operating environment 100 to form coaxial interconnects 116 on the semiconductor wafer 110 before the semiconductor wafer 110 is diced for assembly into a plurality of semiconductor components 112. Notably, in certain alternative operating environments (not shown), the coaxial interconnects 116 may be formed on a packaging substrate (using other tools that perform similar operations) rather than on the semiconductor wafer 110. Such alternative operating environments may include an assembly or packaging facility (not shown) where final operations complete the fabrication of the semiconductor components 112.

[0032] Figure 2 Detail 200 of an exemplary coaxial interconnect structure is shown according to one or more embodiments. The coaxial interconnect structure may be Figure 1 The coaxial interconnect 116 in Figure 1 The semiconductor component 112 is included in the embodiment of the present invention.

[0033] As shown in the side view (a cross-sectional view of a portion of semiconductor component 112), coaxial interconnect 116 electrically couples signal pads 202 of IC die 114 to corresponding signal traces 204 of package substrate 206. In this example, the package substrate may be a multi-layer printed circuit board (PCB) formed of a composite fiber-based epoxy material and includes multiple layers of conductive materials, such as copper (Cu), aluminum (Al), etc.

[0034] The coaxial interconnect 116 also electrically couples the ground pad 208 of the IC die 114 to a corresponding ground trace 210 of the package substrate 206. Furthermore, as shown in this exemplary coaxial interconnect structure, the corresponding signal trace 204 and the corresponding ground trace 210 are formed from separate conductive layers of the package substrate 206. As part of the overall coaxial interconnect structure, a conductive material such as a tin-lead (Sn—Pb) solder material (shown by elements 212-1 and 212-2) may be included as part of the coaxial interconnect structure.

[0035] like Figure 2As shown in the cross section AA of FIG. 1 , the coaxial interconnect 116 is composed of a signal core 214, a ground shield 216, and an insulator 218. For example, the signal core 214 can be a conductive material, which is a copper (Cu) material, a titanium (Ti) material, or a tungsten (W) material. For example, the ground shield 216 can be a conductive material of a copper (Cu) material or a tin (Sn) material. For example, the insulator 218 can be a dielectric material of a polyimide (PI) material, a polybenzoxazole (PBO) material, or a borophosphosilicate glass (BPSG) material.

[0036] As with this example of the coaxial interconnect 116 , the ground shield 216 completely surrounds the perimeter of the dielectric body 218 and the perimeter of the signal core 214 .

[0037] In addition, if Figure 2 As shown, the coaxial interconnect 116 (e.g., each of the signal core 214, the ground shield 216, and the insulator 218) extends about an axis 220, which is orthogonal to the plane of the IC die 114 containing the signal pads 202 and the ground pads 208. The axis 220 is also orthogonal to the plane of the package substrate 206 containing the corresponding signal traces 204 and the corresponding ground traces 210. However, orthogonal is just an example, and in certain cases, the coaxial interconnect 116 can be "close to" orthogonal or even "offset". In this case, an alternative manufacturing technique can cause the axis 220 to be + / -15° relative to a theoretical axis that is orthogonal to the plane of the package substrate 206.

[0038] Figure 3 Detail 300 of an exemplary coaxial interconnect structure is shown according to one or more embodiments. The coaxial interconnect structure may be Figure 1 The coaxial interconnect 116 in Figure 1 The semiconductor component 112 is included in the embodiment of the present invention.

[0039] As shown in the side view (a cross-sectional view of a portion of semiconductor component 112), coaxial interconnect 116 electrically couples signal pads 302 of IC die 114 to corresponding signal traces 304 of package substrate 306. In this example, the package substrate is a single-layer printed circuit board (PCB) formed of a composite fiber-based epoxy material and includes layers of conductive materials such as copper (Cu), aluminum (Al), etc.

[0040] The coaxial interconnect 116 also electrically couples the ground pad 308 of the IC die 114 to a corresponding ground trace 310 of the package substrate 306. Furthermore, as shown in this exemplary coaxial interconnect structure, the corresponding signal trace 304 and the corresponding ground trace 310 are formed from a common conductive layer of the package substrate 306. As part of the overall coaxial interconnect structure, a conductive material such as a tin-lead (Sn—Pb) solder material (shown by elements 312-1 and 312-2) may be included as part of the coupling.

[0041] like Figure 3 As shown in the cross section AA of FIG. 1 , the coaxial interconnect 116 is composed of a signal core 314, a ground shield 316, and an insulator 318. For example, the signal core 314 can be a conductive material of a copper (Cu) material, a titanium (Ti) material, or a tungsten (W) material. For example, the ground shield 316 can be a conductive material of a copper (Cu) material or a tin (Sn) material. For example, the insulator 318 can be a dielectric material of a polyimide (PI) material, a polybenzoxazole (PBO) material, or a borophosphosilicate glass (BPSG) material.

[0042] As with this example of the coaxial interconnect 116 , the ground shield 316 surrounds a portion of the perimeter of the dielectric body 318 and a portion of the perimeter of the signal core 314 .

[0043] In addition, if Figure 3 As shown, the coaxial interconnect 116 (e.g., each of the signal core 314, the ground shield 316, and the insulator 318) extends about an axis 320 that is orthogonal to the plane of the IC die 114 containing the signal pads 302 and the ground pads 308. The axis 320 is also orthogonal to the plane of the package substrate 306 containing the corresponding signal traces 304 and the corresponding ground traces 310. However, orthogonality is only an example, and in certain cases, the coaxial interconnect 116 can be "close to" orthogonal or even "offset." In this case, an alternative manufacturing technique can cause the axis 220 to be + / - 15° relative to a theoretical axis that is orthogonal to the plane of the package substrate 206.

[0044] like Figure 3 As shown, the discontinuity of the ground shield 316 enables electrical coupling to a single-layer package substrate (e.g., a package substrate 306 having corresponding signal traces 304 and corresponding ground traces 310 formed from a common conductive layer). Other ground shields may be formed with similar discontinuous properties, such as being formed as a ground shield or "post" having multiple segments to enable electrical coupling to a single-layer package substrate.

[0045] Technology used to manufacture coaxial interconnect structures

[0046] Figures 4a to 4cAn exemplary method 400 for fabricating an integrated circuit die to have a coaxial interconnect structure is shown in accordance with one or more implementations. The coaxial interconnect structure may be Figure 1 A coaxial interconnect 116 is provided. Figure 1 A semiconductor wafer fabrication tool set (eg, electroplating tool 104 , photolithography exposure tool 106 , and etching tool 108 ) may be used to fabricate coaxial interconnects 116 on IC die 114 . Figure 5a to Figure 5f 500 illustrates an exemplary detail of a cross section of an integrated circuit chip 114 having a coaxial interconnect 116 during various stages of fabrication in accordance with one or more implementations. In addition, if the exemplary method 400 is not changed, Figure 5a to Figure 5f It is in addition to the operations performed by the exemplary method 400 .

[0047] exist Figure 4a At 402, an operation deposits a first conductive material on a material stack including a signal pad. The material stack may be a material stack of an integrated circuit die (eg, IC die 114) associated with a given state of work in progress (WIP).

[0048] In the context of this example and if Figure 5a As shown in detail 500 of FIG. 1 , operation 502 is performed on a material stack 504. A signal pad 506 is included as part of the material stack 504. As shown, a first conductive material 508 is deposited on the material stack 504 (including the signal pad 506). For example, the first conductive material 508 may be deposited by a sputtering tool, a chemical vapor deposition (CVD) tool, or a physical vapor deposition tool ( Figure 1 The signal pad 506 may be deposited by a metallization (not shown) and may be a combination of under bump metallization (UBM) materials, such as one or more of elemental titanium (Ti), nickel (Ni), copper (Cu), tungsten (W), aluminum (Al), chromium (Cr), or vanadium (V). The signal pad 506 may be electrically coupled to a functional circuit of the IC die 114, such as an input or output (I / O) of the IC die 114.

[0049] Continuing with method 400, Figure 4a As shown in 404 of the embodiment, an operation is performed to deposit a first coating of a photoresist material on the first conductive material. The photoresist material may be a positive photoresist material that changes properties when irradiated by an energy source so that the (irradiated) photoresist material can be removed by a developing tool. In the example of the ongoing setup and as shown in Figure 5a As shown in operation 510, by coating tool ( Figure 1 (not shown) a first coating of a photoresist material 512 is deposited on the first conductive material 508.

[0050] Continuing with method 400, Figure 4aIn 406, a first photolithography operation irradiates and removes the same portion of the first coating of photoresist material to expose a portion of the first conductive material. In this example, the photoresist material is a "positive tone" photoresist material. Figure 1 The photolithography exposure tool 106 can illuminate the same portion of the first coating of photoresist material with the help of a photolithography mask configured to mask the illumination pattern across the IC die 114, which portion of the photoresist material is then exposed by a development tool ( Figure 1 According to the ongoing example and as Figure 5a As shown in operation 514 of , the same portion (not shown) of the first coating of photoresist material 512 has been illuminated and removed to expose a portion of the first conductive material 516 .

[0051] exist Figure 4a At 408, method 400 continues. The second conductive material is deposited on the exposed portion of the first conductive material. For example, Figure 1 The electroplating tool 104 can deposit materials such as copper (Cu) materials via an electro-deposition process. Figure 1 Other example materials deposited on the exposed portion of the first conductive material by an electroplating tool 104 or another tool such as a chemical vapor deposition (CVD), physical vapor deposition (PVD), or sputtering tool include a titanium (Ti) material or a tungsten (W) material. In the context of the current example and as Figure 5b As shown in operation 518 , a second conductive material 520 is deposited on the exposed portions of the first conductive material 516 .

[0052] Continuing with method 400, Figure 4a At 410, operations include removing a remaining portion of the first coating of photoresist material to expose a portion of the first conductive material, and etching the exposed portion of the first conductive material to obtain a signal core extending around the axis. For example, an ashing tool ( Figure 1 ) can remove the remaining portion of the first coating of photoresist material, and Figure 1 The etching tool 108 can remove the exposed portion of the first conductive material. In this case, the etching tool 108 can use an etchant that reacts with the first conductive material but does not react with the second conductive material.

[0053] In the context of the current example and as Figure 5b As shown in operation 522, the remaining portion of the first material coating has been removed, and the exposed portion of the first material layer has been etched to obtain the signal core 524. In addition, as shown in FIG. Figure 5b As shown in operation 522 , the signal core 524 extends about an axis 526 .

[0054] exist Figure 4aAt 412, method 400 continues. As part of the method at 412, an operation deposits a dielectric material onto the material stack including the signal core. As an example, a deposition tool (such as a physical vapor deposition (PVD) tool or a chemical vapor deposition (CVD) tool ( Figure 1 (not shown)) a dielectric material such as a polyimide (PI) material, a polybenzoxazole (PBO) material, or a borophosphosilicate glass (BPSG) material may be deposited on the material stack. In the context of the current example and as Figure 5b As shown in operation 528 , a dielectric material 530 has been deposited on the material stack 504 including the signal core 524 .

[0055] Continue using method 400 and if Figure 4b As shown in 414 of the embodiment, the operation deposits a second coating of a photoresist material on the dielectric material. The photoresist material can be a positive photoresist material that changes properties when irradiated by an energy source so that the (irradiated) photoresist material can be removed by a developing tool. According to the ongoing example and as Figure 5c As shown in operation 532, by coating tool ( Figure 1 (not shown) a second coating of photoresist material 534 is deposited on dielectric material 530.

[0056] Continuing with method 400, Figure 4b At 416, a second photolithography operation illuminates and removes the same portion of the first coating of photoresist material to expose a portion of the dielectric material. In this example, the photoresist material is a "positive tone" photoresist material. Figure 1 The photolithography exposure tool 106 may illuminate the same portion of the second coating of photoresist material with the aid of a photolithography mask configured to mask the illumination pattern across the IC die 114, which portion of the photoresist material is then exposed by a developing tool ( Figure 1 In the context of the example being performed and as Figure 5c As shown in operation 536 , the same portion (not shown) of the second coating of photoresist material 534 has been illuminated and removed to expose a portion of dielectric material 538 .

[0057] exist Figure 4b At 418, method 400 continues by removing the exposed portion of the dielectric material. Figure 1 The operation is performed by the etching tool 108. In the setup of the ongoing example and as Figure 5c As shown in operation 540 , the exposed portions of the dielectric material (shown as 538 at operation 536 ) have been removed.

[0058] exist Figure 4bAt 420, the method 400 is continued by removing the remaining portion of the second coating of the photoresist material to obtain an insulator extending around the axis. For example, an ashing tool ( Figure 1 The remaining portion of the second coating of photoresist material may be removed (not shown). In the context of the ongoing example and as Figure 5d As shown in operation 542 , the remaining portion of the second coating of photoresist material has been removed to provide an insulator 544 extending about axis 526 .

[0059] exist Figure 4b At 422, method 400 is continued by depositing a third conductive material on the material stack (including the signal core and the insulator). As an example, the deposition of the third conductive material can be performed by a sputtering tool, a chemical vapor deposition (CVD) tool, or a physical vapor deposition (PVD) tool ( Figure 1 As an example, the third conductive material may be a material composition including one or more of the elements nickel (Ni), copper (Cu), aluminum (Al), or tin (Sn). According to the ongoing example and as Figure 5d As shown in operation 546 , a third conductive material layer 548 has been deposited on the material stack 504 including the signal core 524 and the insulator 544 .

[0060] exist Figure 4c At 424, method 400 is continued by depositing a third coating of a photoresist material on the third conductive material. The photoresist material may be a positive photoresist material that changes properties when irradiated by an energy source such that the (irradiated) photoresist material may be removed by a developing tool. In the example setup in progress and as Figure 5d As shown in operation 550, by coating tool ( Figure 1 (not shown) a third coating of photoresist material 552 is deposited on the third conductive material 548.

[0061] exist Figure 4c At 426, method 400 continues with a third photolithography operation irradiating and removing the same portion of the third coating of photoresist material to expose a portion of the third conductive material. In this example, the photoresist material is a "positive tone" photoresist material. Figure 1 The lithography exposure tool 106 can illuminate the same portion of the third coating of photoresist material with the help of a lithography mask configured to mask the illumination pattern across the IC die 114, and then pass through a development tool ( Figure 1 In the context of the ongoing example and as shown in FIG. Figure 5e As shown in operation 554 , the same portion (not shown) of the third coating of photoresist material 552 has been irradiated and removed to expose a portion of the third conductive material 556 .

[0062] Continuing with method 400, Figure 4c At operation 428, the exposed portion of the third conductive material is removed. For example, Figure 1 The operation is performed by etching tool 108. According to the example being performed and as Figure 5e As shown in operation 558 of FIG. 5 , the exposed portion of the dielectric material (shown as 556 at operation 554 ) has been removed.

[0063] exist Figure 4c At 430, method 400 is continued and an operation is performed to remove the remaining portion of the third coating of photoresist material to obtain a ground shield extending around the axis. For example, an ashing tool ( Figure 1 The remaining portion of the third coating of photoresist material may be removed (not shown). In the context of the present example and as Figure 5e As shown in operation 560 , the remaining portion of the third coating of photoresist material has been removed to provide a ground shield 562 extending about axis 526 .

[0064] This method is Figure 4c Continuing at 432, an operation is performed to polish the signal core, the insulator and the ground shield to obtain a coaxial interconnect structure. This operation can be performed by including an electrochemical polishing tool or a thinning tool ( Figure 1 In the context of the current example and as shown in Figure 5f As shown in operation 564 , the signal core, insulator, and ground shield have been polished to obtain a coaxial interconnect structure 566 .

[0065] Additional tools may perform operations to connect an IC die having such a coaxial interconnect structure 566 to a package substrate as part of a semiconductor component. For example, such tools may include a thermal compression tool (for thermocompression bonding), a dispensing tool (for underfilling an IC die), and a solder reflow tool (for solder-based bonding), among others.

[0066] Modifications

[0067] Various modifications are possible to the above-described configuration of the coaxial interconnect structure and to the above-described manufacturing operations.

[0068] As an example of structural variation, a dielectric material (e.g., Figure 2 The insulator 218) may in some cases be a material in a gas phase (eg, air) rather than a solid phase.

[0069] As another example of structural variation, and as part of advanced semiconductor packaging technology, a packaging substrate (e.g., Figure 2The packaging substrate 206 may be a silicon interposer or another integrated circuit die with through silicon via (TSV) interconnects.

[0070] As an example of a variation of the manufacturing technique, the photolithography operation may be based on a "negative" photoresist material rather than the described "positive" photoresist material. In this case, the illuminated portion of the photoresist material and the removed portion of the photoresist material will not be the same portion of the material.

[0071] As another example of variations in manufacturing techniques, specific instances of manufacturing operations may include forming a substrate (e.g., Figure 2 Instead of manufacturing the coaxial interconnect structure on an IC die (e.g., IC die 114), the coaxial interconnect structure is manufactured on a package substrate 206 of FIG. 1 . Although the tools performing the manufacturing operations on the package substrate are different from those performing the manufacturing operations on the package substrate, the coaxial interconnect structure is manufactured on the package substrate 206 of FIG. Figure 1 The tools shown and described are different, but the operations will reflect those described for method 400 .

[0072] Although the subject matter has been described in language specific to structural features and / or methodological operations, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or operations described herein, including the order in which they are performed.

Claims

1. A semiconductor component, comprising: a package substrate having corresponding signal and ground traces formed at separate conductive layers of the package substrate; An integrated circuit IC bare die having a signal pad and a ground pad; as well as a coaxial interconnect structure configured to electrically couple the signal pad and the ground pad of the IC die to corresponding signal traces and the ground traces of the package substrate, wherein the coaxial interconnect structure comprises: a signal core extending about an axis that is (i) orthogonal to a plane of the IC die containing the signal pads and the ground pads and (ii) orthogonal to a plane of the package substrate containing corresponding signal traces and the ground traces; a ground shield extending about the axis and arranged so that the ground shield surrounds a perimeter of the signal core; and an insulator, disposed between the signal core and the ground shield, The signal core and the insulator are deposited on the signal pad, and the ground shield is deposited on the ground pad. 2 . The semiconductor component of claim 1 , wherein the package substrate is a multilayer printed circuit board (PCB).

3. The semiconductor component of claim 2, wherein the multilayer printed circuit board (PCB) is formed of a composite fiber-based epoxy material and includes multiple layers of copper or aluminum. 4 . The semiconductor component of claim 1 , wherein the package substrate is a silicon interposer having through silicon via (TSV) interconnects. 5 . The semiconductor component of claim 1 , wherein the integrated circuit die is a memory die, the memory die being a dynamic random access memory (DRAM) die or a flash memory die. The semiconductor component of claim 1 , wherein the integrated circuit die is a logic die.

7. The semiconductor component of claim 1, wherein the integrated circuit die is a system on a chip (SoC) die. The semiconductor component according to claim 1 , wherein the signal core is a copper (Cu) material. 9 . The semiconductor component according to claim 1 , wherein the signal core is a titanium (Ti) or tungsten (W) material. 10 . The semiconductor component according to claim 1 , wherein the insulator is a polyimide (PI) material, a polybenzoxazole (PBO) material, or a borophosphosilicate glass (BPSG) material. The semiconductor component according to claim 1 , wherein the insulator is a material in a gas phase. 12 . The semiconductor component of claim 1 , wherein the ground shield is a copper (Cu) material.

13. The semiconductor component of claim 1, wherein the ground shield is a tin (Sn) material.

14. A semiconductor component, comprising: a package substrate having corresponding signal traces and ground traces formed at a common conductive layer of the package substrate; An integrated circuit IC bare die having a signal pad and a ground pad; as well as a coaxial interconnect structure configured to electrically couple the signal pad and the ground pad of the IC die to corresponding signal traces and the ground traces of the package substrate, wherein the coaxial interconnect structure comprises: a signal core extending about an axis that is (i) orthogonal to a plane of the IC die containing the signal pads and the ground pads and (ii) orthogonal to a plane of the package substrate containing corresponding signal traces and the ground traces; a ground shield extending about the axis and arranged so that the ground shield surrounds a portion of a perimeter of the signal core; and an insulator, disposed between the signal core and the ground shield, The signal core and the insulator are deposited on the signal pad, and the ground shield is deposited on the ground pad.

15. The semiconductor component of claim 14, wherein the packaging substrate is a single layer printed circuit board (PCB) comprising a composite fiber-based epoxy material, and the packaging substrate comprises a single layer of copper or aluminum.

16. The semiconductor component of claim 14, wherein the integrated circuit die is a memory die, the memory die is a dynamic random access memory die or a flash memory die, a logic die, or a system-on-chip die. The semiconductor component according to claim 14 , wherein the signal core is a copper (Cu) material. 18 . The semiconductor component according to claim 14 , wherein the signal core is a titanium (Ti) or tungsten (W) material. 19 . The semiconductor component of claim 14 , wherein the insulator is one of a polyimide (PI) material, a polybenzoxazole (PBO) material, or a borophosphosilicate glass (BPSG) material.

20. The semiconductor component of claim 14, wherein the ground shield is a copper (Cu) material.

21. A method for manufacturing a coaxial interconnect structure, the method comprising: depositing a first conductive material on the material stack including the signal pad; depositing a first coating of a photoresist material on the first conductive material; irradiating and removing the same portion of the first coating of photoresist material via a first photolithography operation to expose a portion of the first conductive material; depositing a second conductive material on the exposed portions of the first conductive material; removing a remaining portion of the first coating of the photoresist material to expose a portion of the first conductive material, and etching the exposed portion of the first conductive material to obtain a signal core, the signal core extending around an axis; depositing a dielectric material on the material stack including the signal core; depositing a second coating of a photoresist material on the dielectric material; irradiating and removing a portion of the second coating of the photoresist material to expose a portion of the dielectric material via a second photolithography operation; removing exposed portions of the dielectric material; removing a remaining portion of the second coating of photoresist material to provide an insulator extending about the axis; depositing a third conductive material on the material stack including the signal core and the insulator; depositing a third coating of photoresist material on the third conductive material; irradiating and removing a portion of the third coating of the photoresist material to expose a portion of the third conductive material via a third photolithography operation; removing the exposed portion of the third conductive material; removing a remaining portion of the third coating of photoresist material to provide a ground shield extending about the axis; as well as The signal core, the insulator and the ground shield are polished to obtain the coaxial interconnection structure.

22. The method of claim 21, wherein depositing the second conductive material comprises depositing a copper (Cu) material.

23. The method of claim 21, wherein depositing the dielectric material comprises depositing a polyimide (PI) material, a polybenzoxazole (PBO) material, or a borophosphosilicate glass (BPSG) material.

24. The method of claim 21, wherein depositing the third conductive material comprises depositing a tin (Sn) material.

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