A digital circuit device for high-frequency radio frequency identification chip demodulation blind area processing

Abstract

The present invention relates to a digital circuit device for processing a high-frequency radio frequency identification chip demodulation blind area, comprising: a radio frequency data processing circuit, which uses a radio frequency output clock to sample and process radio frequency output data, so that the timing relationship between the processed data and the clock is relatively fixed; a radio frequency clock processing circuit, which uses the output signal of the radio frequency data processing circuit to perform a logical operation on the radio frequency output clock, and the processed output clock signal can effectively avoid burrs; a combined output circuit, which performs a logical operation on the output data and the output clock according to the logical requirements of the demodulation digital circuit for the clock signal and the data signal, so that its output signal meets the logical requirements of the demodulation digital circuit for correct decoding. The output data and the output clock processed by this device have a stable timing relationship, and can effectively avoid burrs on the clock, which can meet the needs of the subsequent demodulation digital circuit for stable operation, thereby effectively avoiding the blind area phenomenon of the high-frequency radio frequency identification chip.

Description

Technical Field

[0001] The present invention belongs to the field of high-frequency radio frequency identification chips, specifically, to the technical field of contactless radio frequency chip demodulation circuits specified in high-frequency radio frequency identification protocols, including but not limited to ISO14443-A, ISO-15693, MiFare1, ISO18092, NFC, etc. Background Art

[0002] High-frequency RFID chips mainly follow ISO 14443, ISO-15693, MiFare1, ISO18092, NFC and other protocols. The protocol defines that its carrier frequency is 13.56MHz and the subcarrier frequency is 1 / 128 of the carrier frequency. The subcarrier will include a pause, and each subcarrier cycle represents 1 bit of data. The position of the pause in a subcarrier cycle defines whether the data represented by the current subcarrier is 0 or 1.

[0003] The card reader modulates the subcarrier signal at the carrier frequency and sends it to the RFID chip. That is, the modulated signal sent by the card reader to the RFID chip represents 1 bit of data every 128 carrier cycles.

[0004] The demodulation function circuit can correctly decode the modulated signal sent by the card reader and decode the data sent by the card reader.

[0005] The demodulation function circuit is generally divided into two parts: demodulation analog circuit and demodulation digital circuit. The main functions of the demodulation analog circuit are:

[0006] 1. Output the clock signal recovered from the carrier: RF output clock. The recovered RF output clock frequency is 13.56MHz. The RF output clock is output normally during non-pause period. During pause period, there is no RF output clock output because there is no carrier.

[0007] 2. Output the demodulated data signal: RF output data. The RF output data signal is represented by a value of 1 during the non-pause period and a value of 0 during the pause period.

[0008] The RF output clock and RF output data signals output by the demodulation analog circuit are sent to the demodulation digital circuit. The main function of the demodulation digital circuit is to decode the received RF output clock and RF output data signals to decode the data sent by the card reader.

[0009] Correct operation of the demodulation digital circuit requires that the timing relationship between the output clock signal of the demodulation analog circuit, i.e., the RF output clock, and the demodulated data signal, i.e., the RF output data, be relatively stable.

[0010] In reality, most demodulation analog circuits have poor performance. When the field strength of the card reader changes or the position of the card on the card reader changes, the timing relationship between the RF output clock and the RF output data is different at the arrival of each pause, and the output RF output clock may also have glitches, which may cause the demodulation digital circuit to fail to decode, and the RFID chip will show a blind spot phenomenon. Summary of the invention

[0011] The present invention discloses a digital circuit device for demodulation blind area processing in a high-frequency radio frequency identification chip. The present invention can adapt to the situation where the timing relationship between the radio frequency output clock and the radio frequency output data signals output by the demodulation analog circuit under different field strengths is unstable and the radio frequency output clock may carry burrs, and can effectively solve the blind area problem.

[0012] In order to achieve the above-mentioned object, the present invention provides a digital circuit device for demodulation blind area processing in a high-frequency radio frequency identification chip, which processes the radio frequency output clock and radio frequency output data of two signals output by the demodulation analog circuit. The processed two signals are the device output clock and the device output data, and the device output clock and the device output data are then sent to the demodulation digital circuit for decoding.

[0013] The device disclosed by the invention comprises: a radio frequency data processing circuit, a radio frequency clock processing circuit and a combined output circuit.

[0014] The RF data processing circuit realizes the function of processing RF output data. Its input is RF output clock and RF output data. The output signal is RF data processing circuit output data. It is connected to RF clock processing circuit and combined output circuit.

[0015] In the radio frequency data processing circuit, the radio frequency output clock samples the radio frequency output data, so that the processed radio frequency data processing circuit output data and the radio frequency output clock have a fixed timing relationship.

[0016] The RF clock processing circuit realizes the function of processing the RF output clock, and its input signal is the RF output clock and the RF data processing circuit output data, and its output is the RF clock processing circuit output clock.

[0017] In this circuit, since the output data of the RF data processing circuit has a fixed timing relationship with the RF output clock, the two can be logically operated according to the valid edge used in the processing in the RF data processing circuit. This can effectively avoid the occurrence of glitches in the clock after the logical operation, and also avoid the glitches carried by the original RF output clock.

[0018] The signal after logical processing with the output data of the radio frequency data processing circuit is the output clock of the radio frequency clock processing circuit, which is connected to the combination output circuit as the output signal of the radio frequency clock processing circuit.

[0019] The combined output circuit implements inversion or other logic operations on the output signal of the RF data processing circuit, the RF data processing circuit output data, and the output signal of the RF clock processing circuit, the RF clock processing circuit output clock.

[0020] Although the output data of the RF data processing circuit and the output clock of the RF clock processing circuit have a fixed timing relationship, they may not meet the requirements of the demodulation digital circuit for the logical relationship between the two, so it is necessary to perform inversion or other logical operations. The choice of inversion or other logical operations depends on the logical relationship required for decoding by the subsequent demodulation digital circuit.

[0021] The output signals of the combinational output circuit are the combinational output circuit output data and the combinational output circuit output clock, both of which serve as inputs of the demodulation digital circuit.

[0022] It can be seen that the output signals of the combined output circuit: the combined output circuit output data and the combined output circuit output clock, have a relatively stable timing relationship, and the combined output circuit output clock has no glitches, which can effectively avoid decoding errors in the digital demodulation circuit, thereby avoiding the blind spot phenomenon in the radio frequency identification chip under different card reader field strengths. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the connection relationship between the digital circuit device for high-frequency radio frequency identification chip blind area processing and the demodulation analog circuit and the demodulation digital circuit of the present invention.

[0024] Figure 2 This is a structural diagram and connection schematic diagram of a digital circuit device for processing blind areas of a high-frequency radio frequency identification chip in the present invention. DETAILED DESCRIPTION

[0025] The following is based on Figure 1 and Figure 2 , specifically describe the preferred embodiments of the present device.

[0026] like Figure 1 As shown, the connection relationship between the digital circuit device for high-frequency radio frequency identification chip blind area processing and the demodulation analog circuit and the demodulation digital circuit provided by the present invention is shown, and its input is the radio frequency output clock and radio frequency output data, and its output is the combined output circuit output data and the combined output circuit data clock. The radio frequency output clock and radio frequency output data are both outputs of the demodulation analog circuit, and the combined output circuit output data and the combined output circuit output clock are used as inputs of the demodulation digital circuit.

[0027] like Figure 2 As shown, the structure and connection relationship of the digital circuit device for blind area processing in the high-frequency radio frequency identification chip provided by the present invention are shown.

[0028] The RF output clock and RF output data enter the device as input signals and first enter the RF data processing circuit. In the RF data processing circuit, a two-stage register is first used to sample and process the RF output data signal using the rising edge of the RF output clock signal, and the signal output by the second register is the output data of the RF data processing circuit.

[0029] The output signal of the RF data processing circuit, the rising edge and falling edge of the RF data processing circuit output data have a stable timing relationship with the rising edge of the RF output clock. The RF data processing circuit output data is the output of the RF output data processing circuit, and is input to the RF clock processing circuit and the combined output circuit respectively.

[0030] like Figure 2 As shown, the input of the RF clock processing circuit is the RF output clock and the output data of the RF data processing circuit.

[0031] In the RF clock processing circuit, the output data of the RF data processing circuit is inverted and ORed with the RF output clock signal. The signal after the operation is the output clock of the RF clock processing circuit. Since the output data of the RF data processing circuit and the rising edge of the RF output clock have a stable timing relationship, the output clock of the RF clock processing circuit after processing will not have burrs. The output clock of the RF clock processing circuit is used as the output signal of the RF clock processing circuit and is input into the combination output circuit.

[0032] like Figure 2 As shown, the input of the combined output circuit is the output clock of the RF clock processing circuit and the output data of the RF data processing circuit, which come from the RF clock processing circuit and the RF data processing circuit respectively.

[0033] According to the requirements of the subsequently connected demodulation digital circuit, in this embodiment, the output clock of the RF clock processing circuit and the output data of the RF data circuit are both inverted and the processed signals are used as output signals. The output signals are the output clock of the combined output circuit and the output data of the combined output circuit, and both will be used as input signals of the subsequently connected demodulation digital circuit.

[0034] It can be seen that the combined output circuit output clock and the combined output circuit output data are used as input signals of the demodulation digital circuit. Compared with the original signals RF output clock and RF output data output by the analog demodulation circuit, their relative timing relationship is stable and the burrs on the clock signal are avoided, which can provide the demodulation digital circuit with stable decoding and effectively avoid the decoding errors that may occur during the processing of the demodulation digital circuit, thereby avoiding the blind spot phenomenon exhibited in the high-frequency RFID chip under different field strengths.

[0035] Although the content of the present invention has been described in detail through the above preferred embodiments, after reading the above contents, various modifications and substitutions of the present invention will be obvious to those skilled in the art. For example, in the above embodiments, the rising edge sampling is replaced by the falling edge sampling in the radio frequency data processing circuit, or other logical operations are used in the radio frequency clock processing circuit and the combination output circuit. Therefore, those skilled in the art can make various modifications or extend the application principles of the embodiments by referring to the description of the present invention without departing from the spirit and scope of the present invention, and these should also be regarded as the protection scope of the present invention.

Claims

1. A digital circuit device for high-frequency radio frequency identification chip demodulation blind area processing, characterized in that: Including: radio frequency data processing circuit; A radio frequency clock processing circuit connected to the radio frequency data processing circuit; A combined output circuit connected to the radio frequency data processing circuit and the radio frequency clock processing circuit; The RF data processing circuit, in which the RF output clock samples the RF output data, the processed signal is the RF data processing circuit output data, the RF data processing circuit output data and the RF output clock have a fixed timing relationship, and the output signal of this circuit is the RF data processing circuit output data; In the RF data processing circuit, a two-stage register is firstly used to sample and process the RF output data signal using the rising edge of the RF output clock signal, and the signal output by the second register is the output data of the RF data processing circuit.

2. The digital circuit device for high-frequency radio frequency identification chip demodulation blind area processing as claimed in claim 1, characterized in that: The RF clock processing circuit, in this circuit, uses the output signal of the RF data processing circuit, the RF data processing circuit output data, as one of the input signals. Since the RF data processing circuit output data already has a fixed timing relationship with the RF output clock, the RF data processing circuit output data and the RF output clock are logically processed according to the effective edge sampled in the RF data processing circuit, effectively avoiding the situation where the clock after logical processing generates glitches. The signal after logical processing is the RF clock processing circuit output clock, and the output signal of this circuit is the RF clock processing circuit output clock.

3. The digital circuit device for high-frequency radio frequency identification chip demodulation blind area processing as claimed in claim 1, characterized in that: A combined output circuit, in which the output signals of the RF data processing circuit and the RF clock processing circuit, the RF data processing circuit output data and the RF clock processing circuit output clock, are processed; logical operations are performed on the output signals of the RF data processing circuit and the RF clock processing circuit according to the logical relationship between the combined output circuit output data and the combined output circuit output clock required by the demodulation digital circuit; the output signals of this circuit are the combined output circuit output data and the combined output circuit output clock.

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