Inverter Circuit

Abstract

The present disclosure relates to an inverter circuit. An inverter includes a semiconductor substrate. 2 The FET switch is disposed at the first surface of the semiconductor substrate, and the further switch is disposed at the first surface of the semiconductor substrate. 2 The FET switch has a current path coupled between a first reference terminal and a second reference terminal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of French Patent Application No. 1852165, filed on March 13, 2018, which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to electronic circuits, such as inverter circuits. Background Art

[0004] An inverting circuit or inverter is a circuit that can invert a signal. Such a circuit is a component that includes a transistor. Summary of the invention

[0005] The present invention relates generally to electronic circuits and, more particularly, to logic circuits. A specific embodiment is applied to forming an inverter.

[0006] One embodiment provides a method including Z 2 -Inverter for FET switch.

[0007] According to one embodiment, Z 2 A first gate of the FET switch is coupled to a first terminal to which a first potential is applied.

[0008] According to one embodiment, Z 2 -FET switches are N-type.

[0009] According to one embodiment, Z 2 -FET switches are P-type.

[0010] According to one embodiment, the inverter comprises at least two Z 2 -FET switch.

[0011] According to one embodiment, the first switch is an N-type Z 2 -FET switch, and the second switch is a P-type Z 2 -FET switch.

[0012] According to one embodiment, the anode of the first switch is coupled to the second terminal to which the second potential is applied and the cathode is coupled to the third terminal to which the third potential is applied, and the anode of the second switch is coupled to the second terminal and the cathode is coupled to the fourth terminal to which the fourth potential is applied.

[0013] According to one embodiment, the second potential is a power supply potential.

[0014] According to one embodiment, the fourth potential is a reference potential.

[0015] According to one embodiment, the reference potential is ground.

[0016] According to one embodiment, each Z 2 -FET switches all include a second gate.

[0017] According to one embodiment, the second gate is located on a surface opposite to a surface on which the first gate is located.

[0018] According to one embodiment, the second gate includes an N-type doped portion and a P-type doped portion.

[0019] According to one embodiment, the P-type doped portion is coupled to a fifth terminal to which a fifth positive potential is applied, and the N-type doped portion is coupled to a sixth terminal to which a sixth negative potential is applied.

[0020] According to one embodiment, each Z 2 -FET switches all include an anode region, a cathode region, a P-type doped region separating the anode region from the cathode region, and an insulating gate region located on top of the P-type doped region and contacting a portion of the P-type doped region on a substrate.

[0021] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It shows that N-type Z 2 -Simplified cross-section diagram of a FET switch;

[0023] Figure 2 It shows P type Z 2 -Simplified cross-section diagram of a FET switch;

[0024] Figure 3 is a circuit diagram of one embodiment of an inverter; and

[0025] Figure 4 is a circuit diagram of another embodiment of an inverter. DETAILED DESCRIPTION

[0026] In different drawings, the same elements are denoted by the same reference numerals. For clarity, only those steps and elements that are helpful for understanding the described embodiments are shown and described in detail.

[0027] In the following description, when referring to terms defining absolute positions (such as the terms "front", "rear", "upper", "lower", "left", "right", etc.) or terms defining relative positions (such as the terms "above", "below", "upper", "lower", etc.) or terms defining directions (such as the terms "horizontal", "vertical", etc.), it refers to the direction of the drawings. The terms "approximately", "substantially" and "magnitude" are used herein to specify a tolerance of plus or minus 10%, preferably plus or minus 5% of the value.

[0028] In this specification, the term "connected" will be used to indicate a direct electrical connection without intermediate electronic components, for example through conductive tracks, while the term "coupled" or the term "linked" will be used to indicate a direct electrical connection (meaning "connected") or a connection via one or more intermediate components (resistors, capacitors, etc.).

[0029] Figure 1 It is a schematic diagram showing Z 2 - Cross-sectional view of a FET switch, more specifically an N-type switch I N .exist Figure 1 In the switch I N More specifically, the dual ground plane (DGP) Z 2 -FET type switch.

[0030] Switch I N The semiconductor layer 1 is formed inside and on top of a SOI (“Silicon on Insulator”) structure, which includes a semiconductor layer 1 (currently made of silicon), which is located on an insulating layer 3 (currently called BOX (for “buried oxide”)), and the insulating layer 3 is located on a semiconductor support 5 (currently made of silicon). The semiconductor support 5 serves as a switch I N The active region is defined in layer 1 and comprises an anode region A separated by an intermediate region 11. N and cathode region K N (or anode A N and cathode K N ). Anode area A N is heavily P-type doped (P+) and is located Figure 1 The cathode region K N is heavily N-type doped (N+) and is located Figure 1 The middle region 11 is a heavily P-type doped (P-) region and is located in the anode region A. N and cathode region K N As an example, the middle region can be made of compressed silicon germanium. The back gate BG is divided into a P-type doped portion BG P and N-type doped part BG N As a variant, the back gate can be doped only P-type. Partial BG P Located at anode A N on one side (on Figure 1 ), while part of BG N Located at cathode K N On one side. Figure 1 The dotted line 6 separates the BG part. N and BG P An insulating gate is formed on the portion of the layer 11 located on the anode region 7 side. The insulating region includes a so-called front gate FG made of polysilicon. NThe gate region FG N and an insulating layer 15 located on a portion of the layer 11 .

[0031] Now we will describe the N-type Z 2 - Operation of the FET switch. During the operation phase, a potential is applied to the back gate BG. More specifically, part of BG N coupled to the terminal to which a positive potential is applied, and part of the BG P Coupled to the terminal to which a negative potential is applied. In addition, to the forward gate FG N To turn on the switch I N , to the anode A N Apply a positive potential and then to the front gate FG N Apply a pulse at zero potential, which causes the attraction switch I N The front gate FG N Therefore, the switch I N is in a low impedance state and is thus turned on.

[0032] Figure 2 It is P type Z 2 -FET switch I P Cross-sectional view of . Figure 2 Switch I P Similar to Figure 1 Switch I N , so the switch I P It comprises a semiconductor layer 1 on an insulating layer 3, which itself is on a semiconductor layer 5. The layer 1 is divided into three regions: the anode region A P , the middle region 11 and the cathode region K P . Switch I P The back gate and front gate of P Indicates. Switch I P and switch I N The difference is: switch I P The insulating gate is formed in layer 11 located in the cathode region K P On the side part (on Figure 2 The insulated gate then still includes the front gate FG P and an insulating layer 15 located on the partial layer 11. The back gate is divided into two parts: one is N-type doped (BG N ) and one is P-type doped (BG P ).

[0033] We will now describe the P-type Z 2 -FET switch I P During the operation phase, the back gate BG is coupled to a terminal to which a potential is applied. More specifically, part of the BG Pcoupled to the terminal to which a positive potential is applied, and part of the BG N Coupled to the terminal to which a negative potential is applied. In addition, to the forward gate FG P To close the switch I P , to the cathode K P Apply zero potential, then forward gate FG P Apply a positive potential pulse, which causes the attraction switch I P The front gate FG P Then, switch I P is in a low impedance state and is thus turned on.

[0034] Figure 3 It includes N type Z 2 -FET switch I N and P-type Z 2 -FET switch I P A circuit diagram of an embodiment of the inverter 20 is shown in FIG.

[0035] exist Figure 3 In, N type and P type Z 2 -FET switch is represented in the form of a diode, to which specific connections have been added. The anode of the diode corresponds to the anode of the switch, and its cathode corresponds to the cathode of the switch. The symbol includes a front gate FG N And the two doped parts of the back gate BG N and BG P Connection of the front gate FG N The connection is located on the side of the diode symbol (on the Figure 3 left-hand side), n-type Z 2 -FET switch anode side and p-type Z 2 -Cathode side of the FET switch. Indicates the N-type doped portion of the back gate BG N The connection is located on the side of the diode symbol on the anode side (on the Figure 3 The right-hand side of the figure shows the P-type doped part BG of the back gate. P The connection is located on the cathode side of the diode symbol (on the Figure 3 In addition, to help distinguish N-type Z 2 -FET switch and P-type Z 2 -FET switch, P-type Z 2 The symbol for a -FET switch includes a black dot on the cathode side.

[0036] In the inverter 20, the switch I N and I P The switch I is connected in series between a terminal to which a power supply potential Vdd is applied and a terminal (eg, ground) to which a reference potential Vss is applied. More specifically, the switch IN The anode of the switch is coupled to (preferably connected to) a terminal to which a potential Vdd is applied, and the switch I N The cathode of the switch I is coupled to (preferably connected to) an output terminal providing an output potential Vout. P The anode of the switch I is coupled to (preferably connected to) an output terminal providing an output potential Vout, and the switch I P The cathode of the switch I is coupled to (preferably connected to) a terminal to which a reference potential Vss is applied. N and I P The front gate of the switch I is coupled to (preferably connected to) a terminal to which an input potential Vin is applied. N and I P The N-type doped portion of the back gate is coupled to (eg, connected to) an applied positive potential V N Terminals of switch I N and I P The P-type doped portion of the back gate is coupled to (eg, connected to) an applied negative potential V P Terminals.

[0037] Since the switch I P The cathode of the switch receives a reference potential (Vss) which is usually zero, so a positive pulse on the input potential Vin turns on the switch I P . Then, the output potential is equal to the potential Vss.

[0038] Since the switch I N The anode of the switch receives a positive potential (Vdd), so a negative pulse or zero pulse on the input potential Vin turns on the switch I N Then, the output potential is equal to the potential Vdd.

[0039] Figure 4 Yes, including Z 2 - A circuit diagram of an embodiment of an inverter 30 including a FET switch and an N-channel MOS transistor T. The inverter 30 is similar to the inverter 20 except that the switch I P Replaced by transistor T.

[0040] When the input potential Vin is positive, the transistor T is turned on, and then the output potential is equal to the potential Vss.

[0041] Since the switch I N The anode of the switch receives a positive potential (Vdd), so a negative pulse or zero pulse on the input potential Vin turns on the switch I N Then, the output potential is equal to the potential Vdd.

[0042] As a variation, based on Figure 3 The structure of switch I N A P-channel MOS transistor can be used instead.

[0043] Typically, the following terms are used:

[0044] Lightly doped semiconductor layer means that the concentration of doping atoms is 10 14 to 5x10 15 Atom / cm 3 The layer within the range;

[0045] Heavily doped semiconductor layer means that the concentration of doping atoms is 10 17 to 10 18 Atom / cm 3 ; and

[0046] Very heavily doped semiconductor layer, with a doping atomic concentration of 10 18 to 10 20 Atom / cm 3 The layer within the range.

[0047] Specific embodiments have been described. Various changes, modifications and improvements will occur to those skilled in the art. Specifically, a fully lightly P-type doped back gate N-type and P-type Z 2 -FET switch, also called single ground plane Z 2 -FET switch.

[0048] Various embodiments with different variations are described above. It should be noted that those skilled in the art can combine various elements of these different embodiments and variations without creative labor.

[0049] These changes, modifications and improvements are intended to be part of this disclosure and are within the spirit and scope of the present invention. Therefore, the above description is intended to be illustrative only and not limiting. The present invention is limited only by the following claims and their equivalents.

Claims

1. An inverter, comprising: Semiconductor substrate; Z 2 - a FET switch disposed at the first surface of the semiconductor substrate; as well as A further switch is disposed at the first surface of the semiconductor substrate, the further switch having a first reference terminal and a second reference terminal connected to the Z 2 - a current path of a FET switch coupled in series with a current path; Wherein Z 2 The FET switch has an anode coupled to the first reference terminal, a cathode coupled to the inverter output terminal, and a gate coupled to the inverter input terminal.

2. The inverter according to claim 1, wherein the Z 2 -FET switches are N-type.

3. The inverter according to claim 1, wherein the Z 2 -FET switches are P-type.

4. The inverter according to claim 1, wherein the further switch comprises a second Z 2 -FET switch.

5. The inverter according to claim 4, wherein the Z 2 -FET switch is N-type Z 2 -FET switch, and the further switch is a P-type Z 2 -FET switch.

6. The inverter of claim 5, wherein the further switch has an anode coupled to the inverter output terminal and a cathode coupled to the second reference terminal. The inverter according to claim 6 , wherein the first reference terminal is a power supply terminal. The inverter according to claim 6 , wherein the second reference terminal is a reference terminal.

9. The inverter of claim 8, wherein the reference terminal is ground.

10. The inverter according to claim 4, wherein the Z 2 The FET switch and the further switch each comprise a first gate and a second gate. 11 . The inverter according to claim 10 , wherein the first gate is located on an upper surface of the semiconductor substrate, and wherein the second gate is located on a lower surface of the semiconductor substrate, the lower surface being opposite to the upper surface. 12 . The inverter of claim 10 , wherein each second gate comprises an N-type doped portion and a P-type doped portion.

13. The inverter according to claim 12, wherein for the Z 2 - a FET switch and the further switch, the P-type doped part being coupled to a positive potential and the N-type doped part being coupled to a negative potential.

14. The inverter according to claim 1, wherein the Z 2 -FET switches include: an anode region, forming the anode disposed in the semiconductor substrate; a cathode region, forming the cathode disposed in the semiconductor substrate; A P-type doped region separating the anode region from the cathode region; as well as The insulating gate region is located on the top of the P-type doping region and contacts a portion of the P-type doping region.

15. The inverter of claim 1, wherein the further switch comprises a MOSFET.

16. An inverter, comprising: N-type Z 2 - a FET switch having a cathode coupled to the inverter output terminal, an anode coupled to the positive reference terminal, a top gate coupled to the inverter input terminal, and a back gate having a P-type doped portion coupled to a positive potential and an N-type doped portion coupled to a negative potential; as well as P-type Z 2 -FET switch, with connection to the N-type Z 2 -a cathode of the FET switch and a cathode of the inverter output terminal, an anode coupled to a negative reference terminal, a top gate coupled to the inverter input terminal, and a back gate having a P-type doped portion coupled to the positive potential and an N-type doped portion coupled to a negative potential.

17. An inverter, comprising: A silicon-on-insulator substrate having a semiconductor layer over an insulating layer, the insulating layer being over a semiconductor substrate; First Z 2 - a FET switch having an anode region disposed in the semiconductor layer, a cathode region disposed in the semiconductor layer, a P-type doped region disposed in the semiconductor layer between the anode region and the cathode region, an insulating gate region located on top of the P-type doped region and in contact with a portion of the P-type doped region, and a back gate disposed in the semiconductor substrate below the anode region, the cathode region and the P-type doped region; Second Z 2 - a FET switch having an anode region disposed in the semiconductor layer, a cathode region disposed in the semiconductor layer, a P-type doped region disposed in the semiconductor layer between the anode region and the cathode region, an insulating gate region located on top of the P-type doped region and in contact with a portion of the P-type doped region, and a back gate disposed in the semiconductor substrate below the anode region, the cathode region and the P-type doped region; input terminal, coupled to the first Z 2 -The gate region of the FET switch and the second Z 2 - Gate region of the FET switch; output terminal, coupled to the first Z 2 - the cathode region of the FET switch and the second Z 2 - cathode region of the FET switch; A first reference terminal coupled to the first Z 2 - Anode region of FET switch; as well as A second reference terminal coupled to the second Z 2 -Anode region of the FET switch.

18. The inverter according to claim 17, wherein the first Z 2 The back gate of the FET switch comprises a first N-type doped portion and a first P-type doped portion, and wherein the second Z 2 The back gate of the FET switch comprises a second N-type doped portion and a second P-type doped portion. 19 . The inverter of claim 18 , wherein the first P-type doped portion and the second P-type doped portion are coupled to a positive potential, and the first N-type doped portion and the second N-type doped portion are coupled to a negative potential.

20. The inverter according to claim 17, wherein the first Z 2 -FET switch is N-type, and the second Z 2 -FET switches are P-type.

21. The inverter of claim 17, wherein the first reference terminal is a power terminal, and the second reference terminal is a ground terminal.

Images