Vertical storage device

Abstract

A vertical memory device includes: a substrate including a first region and a second region adjacent to the first region; a first conductive layer extending on the first region and the second region; a second conductive layer extending on the first region and the second region, the second conductive layer being stacked on the first conductive layer. The upper surface of the substrate has a step portion at a boundary between the first region and the second region, and the upper surface of the substrate in the first region is lower than the upper surface of the substrate in the second region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0045979 filed on April 20, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The inventive concept relates to a vertical type memory device. Background Art

[0004] The size of electronic products is gradually reduced, while such electronic products still need to process high-capacity data. Therefore, the integration of semiconductor memory devices used in such electronic products is increased. Among the methods that can increase the integration of semiconductor memory devices, a vertical memory device has been proposed in which memory cells having a vertical transistor structure (rather than the existing planar transistor structure) are stacked. Summary of the invention

[0005] Some example embodiments of the inventive concepts will provide a vertical type memory device having improved reliability.

[0006] According to some example embodiments of the inventive concept, a vertical memory device includes: a substrate including a first region and a second region adjacent to the first region; a first conductive layer extending on the first region and the second region; a second conductive layer extending on the first region and the second region, the second conductive layer being stacked on the first conductive layer. An upper surface of the substrate has a step portion at a boundary between the first region and the second region, and an upper surface of the substrate in the first region is lower than an upper surface of the substrate in the second region.

[0007] According to some example embodiments of the present invention, a vertical memory device includes: a substrate including a cell array region and a connection region adjacent to the cell array region; a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate and forming a step structure in the connection region; a plurality of channel structures in the cell array region, the plurality of channel structures passing through the plurality of gate electrode layers; and a plurality of dummy channel structures in the connection region, the plurality of dummy channel structures passing through at least one of the plurality of gate electrode layers. The upper surface of the substrate has a step portion at a boundary between the cell array region and the connection region. The vertical lengths of the plurality of channel structures are greater than the vertical lengths of the plurality of dummy channel structures.

[0008] According to some example embodiments of the present invention, a vertical memory device includes: a substrate including a cell array region and a connection region adjacent to the cell array region; a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, the lowest one of the plurality of gate electrode layers forming a step structure in the connection region; a plurality of channel structures in the cell array region and passing through the plurality of gate electrode layers; and a plurality of dummy channel structures in the connection region and passing through at least one of the plurality of gate electrode layers. The upper surface of the substrate has a step portion at a boundary between the cell array region and the connection region. Each of the plurality of channel structures includes a first epitaxial layer in contact with the substrate, each of the plurality of dummy channel structures includes a second epitaxial layer in contact with the substrate, and the height of the upper surface of the first epitaxial layer is different from the height of the upper surface of the second epitaxial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description given in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a schematic diagram illustrating a configuration of a vertical type memory device according to some example embodiments of the inventive concept;

[0011] Figure 2 It is conceptually shown Figure 1 A circuit diagram of a cell array region;

[0012] Figure 3 is a schematic plan view of a vertical memory device according to some example embodiments of the inventive concept;

[0013] Figures 4 to 6 are schematic cross-sectional views of vertical memory devices according to some example embodiments of the inventive concept;

[0014] Fig. 7A and Figure 7B is a diagram illustrating a gate dielectric layer of a semiconductor device according to some example embodiments of the inventive concept;

[0015] Figure 8 are schematic cross-sectional views of vertical memory devices according to some example embodiments of the inventive concept;

[0016] Fig. 9 are schematic cross-sectional views of vertical memory devices according to some example embodiments of the inventive concept;

[0017] Fig.10 are schematic cross-sectional views of vertical memory devices according to some example embodiments of the inventive concept;

[0018] Fig.11A and Fig. 11B is a diagram illustrating a peripheral circuit region of a vertical type memory device according to some example embodiments of the inventive concept;

[0019] Figures 12 to 16 is a schematic diagram illustrating a method of manufacturing a vertical type memory device according to some example embodiments of the inventive concept; and

[0020] Figures 17 to 19 2 is a schematic diagram illustrating a method of manufacturing a vertical type memory device according to some example embodiments of the inventive concept. DETAILED DESCRIPTION

[0021] Hereinafter, example embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0022] Figure 1 is a schematic diagram of a vertical type memory device according to some example embodiments.

[0023] refer to Figure 1 , the vertical memory device may include a memory cell region and a peripheral circuit region. The peripheral circuit region may include a row decoder region ROW DCR, a page buffer region PBR, a column decoder region COL DCR, etc. The memory cell region may include a cell array region CAR and a connection region CNR. According to example embodiments, the connection region CNR may be between the cell array region CAR and the row decoder region ROW DCR.

[0024] A memory cell array composed of a plurality of memory cells may be in the cell array region CAR. In example embodiments, the memory cell array may include memory cells arranged in a three-dimensional manner, and a plurality of word lines and bit lines electrically connected to the memory cells.

[0025] The row decoder that selects the word line of the memory cell array may be in the row decoder region ROW DCR, and the wiring structure may be in the connection region CNR, the wiring structure including contact plugs and wiring, electrically connecting the memory cell array and the row decoder to each other. The row decoder may select one of the word lines of the memory cell array by address information. The row decoder may provide word line voltages to the selected word line and the unselected word lines, respectively, in response to a control signal of the control circuit.

[0026] A page buffer may be in the page buffer region PBR to read information stored in the memory cell. The page buffer may temporarily store data to be stored in the memory cell, or may sense data already stored in the memory cell, depending on the operation mode. The page buffer may operate as a write driver circuit in a program operation mode, and operate as a sense amplifier circuit in a read operation mode.

[0027] A column decoder connected to a bit line of the memory array may be in the column decoder region COL DCR. The column decoder may provide a data transmission path between the page buffer and an external device (eg, a memory controller).

[0028] The cell array region CAR may include a plurality of cell array blocks BLK. Each cell array block BLK may include: a gate electrode layer stacked on a substrate, and a channel structure including a channel and a gate dielectric layer to form a three-dimensionally arranged memory cell. The gate electrode layer may be conductive. The gate electrode layer may include a conductive layer. Each cell array block BLK may include a bit line electrically connected to the memory cell.

[0029] Figure 2 It is conceptually shown Figure 1 Circuit diagram of the cell array region CAR.

[0030] Reference Figure 2 , the memory cell array in the cell array region CAR may include: a plurality of memory cell strings S, including memory cells MC connected in series to each other; and a ground selection transistor GST and string selection transistors SST1 and SST2, connected in series to both ends of the memory cell MC. The plurality of memory cell strings S may be connected in parallel to respective bit lines BL0 to BL2. The plurality of memory cell strings S may be connected in common to a common source line CSL. For example, the plurality of memory cell strings S may be between a plurality of bit lines BL0 to BL2 and a common source line CSL. In some example embodiments, the plurality of common source lines CSL may also be arranged in a two-dimensional manner.

[0031] The memory cells MC connected in series to each other can be controlled by word lines WL0 to WLn to select the memory cells MC. Each memory cell MC may include a data storage element. The gate electrodes of the memory cells MC at substantially the same distance from the common source line CSL may be commonly connected to one of the word lines WL0 to WLn, thereby being in an equipotential state. Similarly, although the gate electrodes of the memory cells MC are at substantially the same distance from the common source line CSL, the gate electrodes arranged in different rows or columns may also be independently controlled.

[0032] The ground selection transistor GST may be controlled by the ground selection line GSL and may be connected to the common source line CSL. The string selection transistor SST may be controlled by the string selection lines SSL1 and SSL2 and may be connected to the bit lines BL0 to BL2. Figure 2 A structure in which one ground selection transistor GST and two string selection transistors SST1 and SST2 are connected to a plurality of memory cells MC connected in series is shown, but one ground selection transistor GST and one string selection transistor SST1 or SST2 may be connected to the plurality of memory cells MC, or a plurality of ground selection transistors GST may also be connected to the plurality of memory cells MC. One or more dummy lines DWL or buffer lines may also be between the uppermost word line WLn among the word lines WL0 to WLn and the string selection lines SSL1 and SSL2. In some example embodiments, one or more dummy lines DWL may also be between the lowermost word line WL0 and the ground selection line GSL.

[0033] For example, when a signal is applied to string selection transistors SST1 and SST2 through string selection lines SSL1 and SSL2, the signal applied through bit lines BL0, BL1, and BL2 can be sent to memory cells MC connected in series with each other, so that data read and write operations can be performed. In addition, by providing a specific (or alternatively, a predetermined) erase voltage through the substrate, an erase operation of erasing data written to the memory cell MC can also be performed. In some example embodiments, the memory cell array may further include at least one or more dummy memory cell strings electrically isolated from the bit lines BL0 to BL2.

[0034] Figure 3 is a schematic plan view of a vertical type memory device 10 according to some example embodiments. Figure 4 Shown along Figure 3 A cross-sectional view taken along line II' and line II-II'. Figure 5 is along Figure 3 A cross-sectional view taken along line III-III′. Figure 6 is along Figure 3 A cross-sectional view taken along line IV-IV′.

[0035] refer to Figure 3 , the vertical type memory device 10 according to some example embodiments may include a memory cell region CR and a peripheral circuit region PCR.

[0036] The memory cell region CR may include a cell array region CAR in which memory cells are formed, and a connection region CNR connecting wirings to gate electrodes of the memory cells. The peripheral circuit region PCR may include a high voltage region HVR and a low voltage region LVR.

[0037] The stacked structure GS may extend in the first direction D1 in the cell array region CAR and the connection region CNR. The stacked structure GS may include a plurality of gate electrode layers alternately stacked on a substrate. The stacked structure GS may be divided into a plurality of cell array blocks BLK by a plurality of separation patterns 180. The plurality of separation patterns 180 may extend continuously in the first direction D1 in the cell array region CAR and the connection region CNR. The plurality of separation patterns 180 may be electrically connected to the substrate. The plurality of separation patterns 180 may be formed of a conductive material. For example, the plurality of separation patterns 180 may include at least one of a metal such as tungsten, copper, titanium, aluminum, etc., a doped semiconductor material, and a conductive metal nitride film. The plurality of separation patterns 180 may be a common source line. The plurality of separation patterns 180 may be electrically insulated from the plurality of gate electrode layers of the stacked structure GS. An insulating layer 182 may be between the plurality of separation patterns 180 and the stacked structure GS. The insulating layer 182 may be formed of an insulating material. For example, the insulating layer 182 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), or a combination thereof. Optionally, the auxiliary separation pattern 183 may be between the separation patterns 180 in the connection region CNR. The auxiliary separation pattern 183 may be formed of a conductive material and electrically insulated from the plurality of gate electrode layers by the insulating layer 182.

[0038] In the cell array region CAR, a plurality of channel structures CHS may be connected to the substrate through the stack structure GS, and a plurality of second dummy channel structures DCS2 may pass through the string insulating layer 185. In the connection region CNR, a plurality of first dummy channel structures DCS1 may be connected to the substrate through the stack structure GS, and a plurality of contact plugs 171 may be connected to a plurality of gate electrode layers.

[0039] A plurality of channel structures CHS may be arranged in a plurality of rows and columns. A plurality of channel structures CHS may be arranged in a hexagonal close-packed lattice form or a zigzag form; however, the inventive concept is not limited thereto. Three channel structures CHS adjacent to each other may be at the vertices of an equilateral triangle. A line segment connecting the centers of three adjacent channel structures CHS may form an equilateral triangle. For example, the channel structure CHS may have a circular cross section. The arrangement of the plurality of channel structures CHS is not limited to Figure 3 The arrangement shown in , and various modifications may be made.

[0040] The stacked structure GS may form a staircase structure including a plurality of staircase layers in the connection region CNR. The plurality of gate electrode layers of the stacked structure GS may extend to have different lengths to form a staircase structure. The plurality of staircase layers may be provided as pad regions where the plurality of contact plugs 171 are located.

[0041] A plurality of first dummy channel structures DCS1 may pass through a plurality of stepped layers. Four adjacent first dummy channel structures DCS1 may be located at the corners of a quadrilateral shape. The contact plug 171 may be between four adjacent first dummy channel structures DCS1. For example, the first dummy channel structure DCS1 may have an elliptical cross section. The cross-sectional area of ​​the first dummy channel structure DCS1 may be greater than the cross-sectional area of ​​the channel structure CHS. For example, the first dummy channel structure DCS1 may have a circular cross section, and the diameter of the channel structure CHS may be smaller than the diameter of the first dummy channel structure DCS1. However, the layout of the plurality of dummy channel structures DCS is not limited to the layout shown in the figure.

[0042] The plurality of channel structures CHS are connected to the bit lines to perform read / write operations, while the plurality of first dummy channel structures DCS1 and the second dummy channel structures DCS2 may not be connected to the bit lines. For example, the plurality of first dummy channel structures and the second dummy channel structures may float during operation of the memory device 10. The plurality of first dummy channel structures DCS1 may be used to support the stacked structures GS in the connection region CNR.

[0043] The high voltage transistor HVT may be in the high voltage region HVR, and the low voltage transistor LVT may be in the low voltage region LVR.

[0044] refer to Figure 4 , Figure 5 and Figure 6 , the vertical memory device 10 may include a substrate 101 , a stack structure GS, a channel structure CHS, a first dummy channel structure DCS1 , a high voltage transistor HVT, a low voltage transistor LVT, and the like.

[0045] The substrate 101 may include a semiconductor material, such as a group IV semiconductor material, a group III-V compound semiconductor material, or a group II-VI compound semiconductor material. The stacked structure GS may include a plurality of gate electrode layers 131 alternately stacked (e.g., alternately stacked between a plurality of mold insulating layers 116) on the substrate 101. The plurality of gate electrode layers 131 may be stacked on the substrate 101 in a third direction (e.g., Z direction) perpendicular to the upper surface of the substrate 101 to be spaced apart from each other. The plurality of gate electrode layers 131 may extend in a first direction (e.g., X direction) intersecting the third direction (Z direction), and may be in the cell array region CAR and the connection region CNR. The plurality of gate electrode layers 131 may extend in a second direction (e.g., Y direction) intersecting the first direction (X direction) and the third direction (Z direction). The stacked structure GS may have a stepped structure including a plurality of stepped layers in the connection region CNR. The plurality of gate electrode layers 131 may extend in a first direction (X direction) to have different lengths to form a stepped structure in the connection region CNR. The plurality of mold insulating layers 116 may be between the plurality of gate electrode layers 131, or on the plurality of gate electrode layers 131. The plurality of mold insulating layers 116 may extend in the first direction to have different lengths to form a stepped structure together with the gate electrode layers 131. Portions of the plurality of gate electrode layers 131 may extend to have the same length. Portions of the plurality of mold insulating layers 116 may extend to have the same length. The number of the plurality of gate electrode layers 131 is not limited to Figure 4 and Figure 5 The number of gate electrode layers 131 constituting the memory cell may be increased to increase the storage capacity of the vertical memory device 10. For example, tens to hundreds of gate electrode layers 131 may be stacked on the substrate 101.

[0046] The gate electrode layer 131 closest to the substrate 101 (e.g., the lowest gate electrode layer 131a) may be set as a ground selection line or a lower selection line, and one or two uppermost gate electrode layers 131b in the stacked structure GS may be set as a string selection line or an upper selection line. The remaining intermediate gate electrode layer 131c of the stacked structure GS may be set as a word line. The buffer insulating layer 112 may be between the lowest gate electrode layer 131a and the substrate 101. The first interlayer insulating layer 114 may be between the lowest gate electrode layer 131a and the intermediate gate electrode layer 131c adjacent to the first interlayer insulating layer 114. The first interlayer insulating layer 114 may be between the ground selection line and the word line. The first interlayer insulating layer 114 may cover the high voltage transistor HVT and the low voltage transistor LVT. The second interlayer insulating layer 125 may be on the stacked structure GS of the connection region CNR, and may be on the first interlayer insulating layer 114 of the high voltage region HVR and the low voltage region LVR.

[0047] The upper surface of the substrate 101 may have a stepped portion at a boundary between the cell array region CAR and the connection region CNR.

[0048] The buffer insulating layer 112 may have a uniform thickness on the upper surface of the substrate 101 in the cell array region CAR and the connection region CNR. The buffer insulating layer 112 may have a bent portion bent along the upper surface of the substrate 101 at a boundary between the cell array region CAR and the connection region CNR.

[0049] The lowermost gate electrode layer 131a may be formed to have a uniform thickness on the buffer insulating layer 112 between the cell array region CAR and the connection region CNR. The lowermost gate electrode layer 131a may have a bent portion bent along the upper surface of the substrate 101 at a boundary between the cell array region CAR and the connection region CNR.

[0050] The thickness of the first interlayer insulating layer 114 formed on the lowermost gate electrode layer 131a may not have a uniform thickness in the cell array region CAR and the connection region CNR. The thickness of the first interlayer insulating layer 114 in the cell array region CAR may be greater than the thickness of the first interlayer insulating layer 114 in the connection region CNR.

[0051] The upper surface of the substrate 101 may have different levels in the high pressure region HVR and the low pressure region LVR. The upper surface of the substrate 101 in the high pressure region HVR may be at a lower level than the upper surface of the substrate 101 in the low pressure region LVR. In some example embodiments, the upper surfaces of the substrate 101 in the high pressure region HVR and the low pressure region LVR may be located at the same level.

[0052] The high voltage transistor HVT may include a high voltage gate insulating layer 212a and a gate electrode 214, and the low voltage transistor LVT may include a low voltage gate insulating layer 212b and a gate electrode 214. The low voltage gate insulating layer 212b may be thinner than the high voltage gate insulating layer 212a. A capping layer 216 may be on the gate electrode 214, and a partition wall 220 may be on a sidewall of the gate electrode 214. A device isolation layer 205 may be between the high voltage transistor HVT and the low voltage transistor LVT. The device isolation layer 205 may be formed at a boundary between the high voltage region HVR and the low voltage region LVR, and a lower portion of the device isolation layer 205 between the high voltage transistor HVT and the low voltage transistor LVT may have a step portion. In the example Fig.11A In the case where the device isolation layer 205 is formed in the low voltage region LVR to be adjacent to the boundary between the high voltage region HVR and the low voltage region LVR, or in the case where Fig. 11BIn the case where the device isolation layer 205 is shown to be formed in the high voltage region HVR to be adjacent to the boundary between the high voltage region HVR and the low voltage region LVR, a lower portion of the device isolation layer 205 between the high voltage transistor HVT and the low voltage transistor LVT may not have a stepped portion. In some example embodiments, the device isolation layer 205 may be formed in both the low voltage region LVR and the high voltage region HVR to be adjacent to the boundary between the high voltage region HVR and the low voltage region LVR.

[0053] The first insulating layer 222 and the second insulating layer 224 may cover the high voltage transistor HVT and the low voltage transistor LVT.

[0054] A height of a step portion formed on the upper surface of the substrate 101 at a boundary between the cell array region CAR and the connection region CNR may be greater than a level difference between upper surfaces of the substrate 101 in the high voltage region HVR and the low voltage region LVR.

[0055] A height of a stepped portion formed on the upper surface of the substrate 101 at a boundary between the cell array region CAR and the connection region CNR may be greater than a thickness of the high voltage gate insulating layer 212 a of the high voltage transistor HVT.

[0056] The gate electrode layer 131 may include a metal material, a metal nitride, a metal silicide material, polysilicon, or a combination thereof; however, the inventive concept is not limited thereto. The metal material may include, for example, tungsten (W), copper (Cu), aluminum (Al), or a combination thereof; however, the inventive concept is not limited thereto. The metal silicide material may be a silicide material including a metal selected from, for example, cobalt (Co), nickel (Ni), hafnium (Hf), platinum (Pt), tungsten (W), titanium (Ti), or a combination thereof; however, the inventive concept is not limited thereto. The metal nitride may include, for example, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof; however, the inventive concept is not limited thereto. The buffer insulating layer 112, the first interlayer insulating layer 114, and the mold insulating layer 116 may include silicon oxide; however, the inventive concept is not limited thereto. The second interlayer insulating layer 125 may include silicon oxide or a low dielectric material; however, the inventive concept is not limited thereto. The low dielectric material may be an insulating material having a lower dielectric constant than silicon oxide; however, the inventive concept is not limited thereto.

[0057] The plurality of channel structures CHS may be in the cell array region CAR to pass through the plurality of gate electrode layers 131. The diameters of the plurality of channel structures CHS may be gradually reduced toward the substrate 101. The plurality of first dummy channel structures DCS1 may pass through at least a portion of the plurality of gate electrode layers 131 in the connection region CNR. The vertical length of the plurality of channel structures CHS may be greater than the vertical length of the plurality of first dummy channel structures DCS1. The vertical length refers to the length in the Z direction.

[0058] Each of the plurality of channel structures CHS in the cell array region CAR may include an epitaxial layer 151, a gate dielectric layer 161, a channel layer 165, an insulating layer 167, and a contact pad 169. The plurality of first dummy channel structures DCS1 may have the same structure as that of the plurality of channel structures CHS. The horizontal cross-section of the plurality of first dummy channel structures DCS1 may have a shape different from that of the plurality of channel structures CHS. The horizontal cross-section refers to a cross-section cut in a direction parallel to the upper surface of the substrate 101. The horizontal cross-section of the plurality of first dummy channel structures DCS1 may be elliptical, and the horizontal cross-section of the plurality of channel structures CHS may be circular. In some example embodiments, the horizontal cross-section of the plurality of first dummy channel structures DCS1 and the horizontal cross-section of the plurality of channel structures CHS may be circular. The first dummy channel structures DCS1 may have a larger diameter or a larger cross-sectional area than the channel structures CHS, respectively.

[0059] The epitaxial layer 151 may be between the channel layer 165 and the substrate 101, and may electrically connect the channel layer 165 and the substrate 101 to each other. The height of the upper surface of the epitaxial layer 151 may be higher than the height of the upper surface of the lowermost gate electrode layer 131a. Figure 4 , the height of the upper surface of the epitaxial layer 151 formed in the cell array region CAR is shown to be the same as the height of the upper surface of the epitaxial layer 151 formed in the connection region CNR, but some example embodiments thereof are not limited thereto. In some example embodiments, the height of the upper surface of the epitaxial layer 151 formed in the cell array region CAR may be different from the height of the upper surface of the epitaxial layer 151 formed in the connection region CNR. In some example embodiments, the height of the upper surface of the epitaxial layer 151 formed in the cell array region CAR may be higher than the height of the upper surface of the epitaxial layer 151 formed in the connection region CNR. In some example embodiments, the height of the upper surface of the epitaxial layer 151 formed in the cell array region CAR may be lower than the height of the upper surface of the epitaxial layer 151 formed in the connection region CNR (see Figure 8). The epitaxial layer 151 may be formed by a selective epitaxial growth process. The epitaxial layer 151 may include a semiconductor material such as single crystal silicon. The epitaxial layer 151 may be doped with n-type and / or p-type impurities. However, the inventive concept is not limited thereto. The epitaxial layer 151 may include germanium and / or carbon. The epitaxial layer 151 may be a heteroepitaxial layer.

[0060] The insulating layer 155 may be partially between the epitaxial layer 151 and the lowermost gate electrode layer 131 a .

[0061] The channel layer 165 may extend perpendicularly to the upper surface of the substrate 101 and may have an inner space. The inner space of the channel layer 165 may be filled with an insulating layer 167. The channel layer 165 may include a semiconductor material such as polysilicon, single crystal silicon, etc. The insulating layer 167 may include an insulating material such as silicon oxide, etc. The contact pad 169 may include a semiconductor material such as polysilicon, etc.

[0062] The gate dielectric layer 161 may be at least between the gate electrode layer 131 and the channel layer 165. The gate dielectric layer 161 may be formed to surround an outer surface of the channel layer 165.

[0063] refer to Fig. 7A The gate dielectric layer 161 may include a tunneling layer 162, a charge trapping layer 163, and a blocking layer 164 in sequence from the outer surface of the channel layer 165. The tunneling layer 162, the charge trapping layer 163, and the blocking layer 164 may all extend vertically along the channel layer 165. The tunneling layer 162 may include, for example, silicon oxide. The charge trapping layer 163 may include, for example, silicon nitride. The blocking layer 164 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON) and / or high-k dielectric material. The high-k dielectric material may be or include aluminum oxide (Al 2 O 3 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 )、ZrO 2 ), zirconium oxide (ZrSi x O y ), hafnium oxide (HfO 2 ), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHfx O y ), Hafnium Aluminum Oxide (HfAl x O y ) and praseodymium oxide (Pr 2 O 3 )

[0064] refer to Figure 7B The gate dielectric layer 161 may include a tunneling layer 162 , a charge trapping layer 163 , a first blocking layer 164 a and a second blocking layer 164 b in sequence from an outer surface of the channel layer 165 .

[0065] The tunneling layer 162, the charge trapping layer 163, and the first barrier layer 164a may extend vertically along the channel layer 165. The second barrier layer 164b may surround the gate electrode layer 131. The second barrier layer 164b may be formed of a high-k dielectric material. The first barrier layer 164a may be formed of a relatively low dielectric constant material compared to the material of the second barrier layer 164b.

[0066] refer to Figure 5 and Figure 6 , the separation pattern 180 may extend continuously in the cell array region CAR and the connection region CNR along the first direction (e.g., the X direction). A plurality of separation patterns 180 may divide a plurality of gate electrode layers 131 into a plurality of regions. A plurality of separation patterns 180 may be insulated from a plurality of gate electrode layers 131 by an insulating layer 182. A plurality of separation patterns 180 may be electrically connected to the substrate 101 by a plurality of gate electrode layers 131. A plurality of separation patterns 180 may be connected to the impurity region 108 formed in the upper portion of the substrate 101. The lower surface of the separation pattern 180 may have a step portion at a boundary between the cell array region CAR and the connection region CNR to correspond to the shape of the substrate 101. The separation pattern 180 may be formed of a conductive material. For example, the separation pattern 180 may include at least one of a metal such as tungsten, copper, titanium, aluminum, etc., a doped semiconductor material, and a conductive material such as a conductive metal nitride film. The separation pattern 180 may be a common source line.

[0067] Fig. 9 is a schematic cross-sectional view of a vertical type memory device 10B according to some example embodiments. Fig. 9 is with Figure 4 The corresponding cross-sectional view will be omitted. Figure 4 A description of the parts that are the same as those in , and a description of the parts that are different from them will be provided below.

[0068] refer to Fig. 9 , the upper surface of the substrate 101 may have a stepped portion at a boundary between the cell array region CAR and the connection region CNR.

[0069] The buffer insulating layer 112′ on the upper surface of the substrate 101 may have different thicknesses in the cell array region CAR and the connection region CNR. The thickness of the buffer insulating layer 112′ in the cell array region CAR may be greater than the thickness in the connection region CNR. The buffer insulating layer 112′ may include a first buffer insulating layer 112a and a second buffer insulating layer 112b. The first buffer insulating layer 112a and the second buffer insulating layer 112b may be in the cell array region CAR, and only the second buffer insulating layer 112b may be in the connection region CNR. The first buffer insulating layer 112a may have a portion whose thickness gradually decreases at a boundary between the cell array region CAR and the connection region CNR. The thickness of the first buffer insulating layer 112a may be the same as the thickness of the high-voltage gate insulating layer 212a. The upper surface of the buffer insulating layer 112′ may be flat, and the lower surface of the buffer insulating layer 112′ may have a step portion in the cell array region CAR and the connection region CNR.

[0070] The lowermost gate electrode layer 131a may be formed to have a uniform thickness on the buffer insulating layer 112' in the cell array region CAR and the connection region CNR. Alternatively, the lowermost gate electrode layer 131 may not have a bent portion at a boundary between the cell array region CAR and the connection region CNR.

[0071] Alternatively, the thickness of the first interlayer insulating layer 114 formed on the lowermost gate electrode layer 131 a may be the same in the cell array region CAR and the connection region CNR.

[0072] A height of a step portion formed on the upper surface of the substrate 101 at a boundary between the cell array region CAR and the connection region CNR may be the same as a level difference between upper surfaces of the substrate 101 in the high voltage region HVR and the low voltage region LVR.

[0073] Fig.10 is a schematic cross-sectional view of a vertical memory device 10C according to some example embodiments. Figure 4 Descriptions of the parts that are the same as those in , and descriptions of the parts that are different from them will be provided.

[0074] refer to Fig.10 , the vertical type memory device 10C may include a memory cell region CR and a peripheral circuit region PCR in a vertical direction. The memory cell region CR may be above the peripheral circuit region PCR. Alternatively, in some example embodiments, the memory cell region CR may also be below the peripheral circuit region PCR.

[0075] The memory cell region CR can be connected to the reference Figure 4The substrate 101′, the gate electrode layer 131 stacked on the substrate 101′, the channel structure CHS, the first dummy channel structure DCS1, etc. may include polysilicon. The substrate 101′ may have a step portion at a boundary between the cell array region CAR and the connection region CNR.

[0076] The peripheral circuit region PCR may include a base substrate 201, a high voltage transistor HVT, and a low voltage transistor LVT on the base substrate 201. The peripheral circuit region PCR may include contact plugs and wirings connected to the high voltage transistor HVT and the low voltage transistor LVT.

[0077] The device isolation layer 205 may be formed in the base substrate 201, and the device isolation layer 205 defines the active regions of the high voltage transistor HVT and the low voltage transistor LVT. The base substrate 201 may include a semiconductor material, for example, a Group IV semiconductor material, a Group III-V compound semiconductor material, or a Group II-VI compound semiconductor material; however, the inventive concept is not limited thereto. The base interlayer insulating layer 250 may cover the high voltage transistor HVT and the low voltage transistor LVT. The substrate 101′ may be on the base interlayer insulating layer 250.

[0078] The substrate 101' may have the same size as the base substrate 201, or may be formed to be smaller than the base substrate 201. The memory cell region CR and the peripheral circuit region PCR may be electrically connected to each other in a region not shown.

[0079] Figures 12 to 17 is a schematic diagram illustrating a method of manufacturing the vertical type memory device 10 according to some example embodiments.

[0080] refer to Fig.12 , the high voltage transistor HVT and the low voltage transistor LVT may be formed in the high voltage region HVR and the low voltage region LVR of the substrate 101 , respectively.

[0081] The upper surface of the substrate 101 in the high pressure region HVR may be located at a lower level than the upper surface of the substrate 101 in the low pressure region LVR. Alternatively, in some example embodiments, the upper surfaces of the substrate 101 in the high pressure region HVR and the low pressure region LVR may be located at the same level.

[0082] The high voltage transistor HVT may include a high voltage gate insulating layer 212a and a gate electrode 214, and the low voltage transistor LVT may include a low voltage gate insulating layer 212b and a gate electrode 214. A capping layer 216 may be on the gate electrode 214, and a partition wall 220 may be on a sidewall of the gate electrode 214. A device isolation layer 205 may be between the high voltage transistor HVT and the low voltage transistor LVT. The device isolation layer 205 may be formed by, for example, a shallow trench isolation (STI) process and / or a deep trench isolation (DTI) process.

[0083] refer to Fig.13 , the cell array region CAR of the substrate 101 may be partially removed. After forming a mask pattern 270 that exposes only the cell array region CAR, an etching process may be performed. The mask pattern 270 may be or include a photoresist pattern and may be removed after the etching process is completed, thereby forming a step portion on the upper surface of the substrate 101 at a boundary between the cell array region CAR and the connection region CNR.

[0084] refer to Fig.14 , the buffer insulating layer 112 and the lowermost sacrificial layer 121a may be formed on the cell array region CAR and the connection region CNR of the substrate 101. The first insulating layer 222 and the second insulating layer 224 may be formed on the high voltage region HVR and the low voltage region LVR of the substrate 101. The buffer insulating layer 112 and the first insulating layer 222 may be simultaneously formed by a single deposition process. In addition, the lowermost sacrificial layer 121a and the second insulating layer 224 may be simultaneously formed by a single deposition process. The lowermost sacrificial layer 121a may be formed of a material having an etching selectivity relative to the buffer insulating layer 112. For example, the buffer insulating layer 112 and the first insulating layer 222 may be formed of silicon oxide, and the lowermost sacrificial layer 121a and the second insulating layer 224 may be formed of silicon nitride; however, the inventive concept is not limited thereto.

[0085] The first interlayer insulating layer 114 may be formed to cover the lowermost sacrificial layer 121a and the second insulating layer 224. The first interlayer insulating layer 114 may be formed of a material having an etching selectivity relative to the lowermost sacrificial layer 121a. Forming the first interlayer insulating layer 114 may include a deposition process of forming a silicon oxide film on the substrate 101 and a planarization process (e.g., a chemical mechanical polishing (CMP) process). The height of the first interlayer insulating layer 114 may be adjusted to prevent or reduce the possibility of exposure of the second insulating layer 224.

[0086] refer to Fig.15, the sacrificial layers 121 and the mold insulating layers 116 may be alternately stacked on the first interlayer insulating layer 114. The sacrificial layers 121 may include a lowermost sacrificial layer 121a, an uppermost sacrificial layer 121b, and an intermediate sacrificial layer 121c between the lowermost sacrificial layer 121a and the uppermost sacrificial layer 121b. The sacrificial layers 121 may be formed of a material having an etching selectivity with respect to the mold insulating layers 116. For example, the mold insulating layers 116 may be formed of silicon oxide, and the sacrificial layers 121 may be formed of silicon nitride.

[0087] Next, a step structure may be formed by patterning the molded insulating layer 116 and the sacrificial layer 121 of the connection region CNR. The step structure may be formed by patterning the molded insulating layer 116 and the sacrificial layer 121 multiple times. Each step layer constituting the step structure may include two molded insulating layers 116 and two sacrificial layers 121. In some example embodiments, each step layer may include three or more molded insulating layers 116 and three or more sacrificial layers 121. The length of the molded insulating layer 116 and the sacrificial layer 121 in the first direction (e.g., the X direction) may decrease as the distance of the molded insulating layer 116 and the sacrificial layer 121 from the substrate 101 increases.

[0088] Subsequently, a second interlayer insulating layer 125 may be formed on the substrate 101. The second interlayer insulating layer 125 may be formed to have a sufficient thickness to cover the sacrificial layer 121 of the connection region CNR and the mold insulating layer 116. Forming the second interlayer insulating layer 125 may include a process of depositing silicon oxide or a low dielectric material and a planarization process (e.g., a CMP process).

[0089] refer to Fig.16 , the channel structure CHS may be formed in the cell array region CAR, and the first dummy channel structure DCS1 may be formed in the connection region CNR.

[0090] First, a channel hole may be formed in the cell array region CAR, and a dummy channel hole may be formed in the connection region CNR by an anisotropic etching process. The channel hole and the dummy channel hole may pass through the mold insulating layer 116, the sacrificial layer 121, the first interlayer insulating layer 114, etc. to expose the substrate 101.

[0091] Next, an epitaxial layer 151 may be formed in the lower portion of the channel hole and the lower portion of the dummy channel hole. The epitaxial layer 151 may be formed by performing selective epitaxial growth (SEG) using the substrate 101 as a seed. The epitaxial layer 151 may be formed of a semiconductor material such as silicon. The epitaxial layer 151 may be doped with impurities. Doping of impurities may be performed during the selective epitaxial growth process. The impurities may be impurities of the same conductivity type as the impurities in the substrate 101, or impurities of the opposite conductivity type. The epitaxial layer 151 may be grown heteroepitaxially or homoepitaxially. The epitaxial layer 151 may include germanium and / or carbon. However, the inventive concept is not limited thereto.

[0092] The gate dielectric layer 161 may be formed to cover the sidewalls of the channel hole and the dummy channel hole. The gate dielectric layer 161 may include a blocking layer, a charge storage layer, and a tunneling layer formed in sequence. The gate dielectric layer 161 may be formed by a deposition process.

[0093] The channel layer 165 may be formed to cover the gate dielectric layer 161 in the channel hole and the dummy channel hole. The channel layer 165 may be formed of a semiconductor material such as polysilicon or amorphous silicon.

[0094] An insulating layer 167 may be formed to fill the remaining space of the channel hole and the dummy channel hole. A contact pad 169 may be formed on the channel layer 165. The insulating layer 167 may be formed of an insulating material such as silicon oxide, etc. The contact pad 169 may be formed using a doped semiconductor material.

[0095] Reference again Figure 4 After removing the sacrificial layer 121 from the cell array region CAR and the connection region CNR through a wet etching process, the gate electrode layer 131 may be formed. Before forming the gate electrode layer 131, an insulating layer 155 may first be formed on the sidewall of the epitaxial layer 151 through an oxidation process.

[0096] Figures 17 to 19 is a schematic diagram illustrating a method of manufacturing a vertical type memory device 10B according to some example embodiments.

[0097] refer to Fig.17 , the cell array region CAR and the high voltage region HVR of the substrate 101 may be partially removed.

[0098] After forming a mask pattern 271 to expose only the cell array region CAR and the high voltage region HVR, an etching process may be performed. The mask pattern 271 may be or include a photoresist pattern and may be removed after the etching process is completed. In this process, a step portion may be formed on the upper surface of the substrate 101 at a boundary between the cell array region CAR and the connection region CNR. The upper surface of the substrate 101 in the cell array region CAR may be located at a lower level than the upper surface of the substrate 101 in the connection region CNR. In this process, a step portion may be formed on the upper surface of the substrate 101 at a boundary between the high voltage region HVR and the low voltage region LVR. The upper surface of the substrate 101 in the high voltage region HVR may be located at a lower level than the upper surface of the substrate 101 in the low voltage region LVR.

[0099] A height of a step portion formed on the upper surface of the substrate 101 at a boundary between the cell array region CAR and the connection region CNR may be the same as a height of a step portion formed on the upper surface of the substrate 101 at a boundary between the high voltage region HVR and the low voltage region LVR.

[0100] refer to Fig.18 The high voltage transistor HVT and the low voltage transistor LVT may be respectively formed in the high voltage region HVR and the low voltage region LVR of the substrate 101. A first buffer insulating layer 112a may be formed in the cell array region CAR of the substrate 101.

[0101] The high voltage transistor HVT may include a high voltage gate insulating layer 212a and a gate electrode 214, and the low voltage transistor LVT may include a low voltage gate insulating layer 212b and a gate electrode 214. A capping layer 216 may be on the gate electrode 214, and a partition wall 220 may be on a sidewall of the gate electrode 214.

[0102] The first buffer insulating layer 112a may be formed simultaneously in the process of forming the high voltage gate insulating layer 212a. Forming the high voltage gate insulating layer 212a and the first buffer insulating layer 112a may include a process of oxidizing the substrate 101 (eg, thermally oxidizing the substrate 101).

[0103] refer to Fig.19, the second buffer insulating layer 112b and the lowermost sacrificial layer 121a may be formed on the cell array region CAR and the connection region CNR of the substrate 101. The second buffer insulating layer 112b may form a buffer insulating layer 112′ together with the first buffer insulating layer 112a. The first insulating layer 222 and the second insulating layer 224 may be formed on the high voltage region HVR and the low voltage region LVR of the substrate 101. Next, a first interlayer insulating layer 114 may be formed to cover the lowermost sacrificial layer 121a and the second insulating layer 224. The first interlayer insulating layer 114 may be formed of a material having an etching selectivity relative to the lowermost sacrificial layer 121a. Forming the first interlayer insulating layer 114 may include a process of depositing a silicon oxide film on the substrate 101 and a planarization process (e.g., a chemical mechanical polishing (CMP) process). The height of the first interlayer insulating layer 114 may be adjusted to prevent or reduce the possibility of exposure of the second insulating layer 224.

[0104] Next, you can execute the above reference Fig.13 and Fig.14 Describe the process.

[0105] Reference again Figure 8 After removing the sacrificial layer 121 from the cell array region CAR and the connection region CNR through a wet etching process, the gate electrode layer 131 may be formed. Before forming the gate electrode layer 131, an insulating layer 155 may first be formed on the sidewall of the epitaxial layer 151 through an oxidation process.

[0106] As described above, according to example embodiments, since the upper surface of the epitaxial layer is stably formed to be higher than the upper surface of the ground selection line and the lowermost gate electrode layer, a vertical memory device can be obtained, which has improved leakage current characteristics through the dummy channel structure in the connection area and has improved reliability.

[0107] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A vertical storage device, include: A substrate comprising a first region and a second region adjacent to the first region; a first conductive layer extending over the first region and the second region; as well as a second conductive layer extending on the first region and the second region, the second conductive layer being stacked on the first conductive layer, wherein the upper surface of the substrate has a step portion at a boundary between the first region and the second region, and the upper surface of the substrate in the first region is lower than the upper surface of the substrate in the second region, and A first distance between a lower surface of the second conductive layer in the first region and an upper surface of the substrate in the first region is greater than a second distance between a lower surface of the second conductive layer in the second region and an upper surface of the substrate in the second region.

2. The vertical storage device according to claim 1, in, The first conductive layer has a bent portion along the stepped portion.

3. The vertical storage device according to claim 1, in, A difference between the first interval and the second interval is the same as a height of the step portion.

4. The vertical storage device according to claim 1, further comprising: include: a separation pattern on the first region and the second region of the substrate, the separation pattern separating the first conductive layer and the second conductive layer, The lower surface of the separation pattern has a stepped portion at a boundary between the first region and the second region.

5. The vertical storage device according to claim 1, further comprising: include: at least one channel structure in the first region and passing through the first conductive layer and the second conductive layer; as well as at least one dummy channel structure in the second region and passing through at least one of the first conductive layer and the second conductive layer, Wherein, a vertical length of the at least one channel structure is greater than a vertical length of the at least one dummy channel structure.

6. The vertical storage device according to claim 5, in, A horizontal cross-sectional area of ​​the at least one dummy channel structure is greater than a horizontal cross-sectional area of ​​the at least one channel structure.

7. The vertical storage device according to claim 5, in, Each of the at least one channel structure and the at least one dummy channel structure comprises: a channel layer extending vertically to the upper surface of the substrate; and an epitaxial layer between the channel layer and the substrate, and A height of an upper surface of the epitaxial layer in the first region is different from a height of an upper surface of the epitaxial layer in the second region.

8. The vertical storage device according to claim 1, further comprising: include: a high-voltage transistor in a third region of the substrate, the high-voltage transistor comprising a high-voltage gate insulating layer, the third region of the substrate being adjacent to the second region of the substrate; as well as a low voltage transistor in the third region of the substrate, the low voltage transistor comprising a low voltage gate insulating layer, the thickness of the low voltage gate insulating layer being smaller than the thickness of the high voltage gate insulating layer, Wherein, the height of the step portion at the boundary between the first region and the second region is the same as the thickness of the high-voltage gate insulating layer.

9. A vertical storage device, include: A substrate, comprising a cell array region and a connection region adjacent to the cell array region; A plurality of gate electrode layers are stacked on the cell array region and the connection region of the substrate and form a stepped structure in the connection region; a plurality of channel structures in the cell array region, the plurality of channel structures passing through the plurality of gate electrode layers; as well as a plurality of dummy channel structures in the connection region, the plurality of dummy channel structures passing through at least one of the plurality of gate electrode layers, wherein the upper surface of the substrate has a step portion at a boundary between the cell array region and the connection region, and The vertical lengths of the plurality of channel structures are greater than the vertical lengths of the plurality of dummy channel structures, The plurality of gate electrode layers include a first gate electrode layer adjacent to the substrate and a second gate electrode layer adjacent to the first gate electrode layer, and Wherein, a first spacing between a lower surface of the second gate electrode layer in the cell array region and an upper surface of the substrate in the cell array region is greater than a second spacing between a lower surface of the second gate electrode layer in the connection region and an upper surface of the substrate in the connection region.

10. The vertical storage device according to claim 9, further comprising: include: an interlayer insulating layer between the first gate electrode layer and the second gate electrode layer, The thickness of the interlayer insulating layer in the cell array region is greater than the thickness of the interlayer insulating layer in the connection region.

11. The vertical storage device according to claim 9, in, The first gate electrode layer includes a bent portion bent along the upper surface of the substrate.

12. The vertical storage device according to claim 9, in, A difference between the first interval and the second interval is the same as a height of the step portion.

13. A vertical storage device, include: A substrate, comprising a cell array region and a connection region adjacent to the cell array region; A plurality of gate electrode layers are stacked on the cell array region and the connection region of the substrate and form a stepped structure in the connection region; a plurality of channel structures in the cell array region and passing through the plurality of gate electrode layers; as well as a plurality of dummy channel structures in the connection region and passing through at least one of the plurality of gate electrode layers, wherein the upper surface of the substrate has a step portion at a boundary between the cell array region and the connection region, and Each of the plurality of channel structures includes a first epitaxial layer in contact with the substrate, each of the plurality of dummy channel structures includes a second epitaxial layer in contact with the substrate, and a height of an upper surface of the first epitaxial layer is different from a height of an upper surface of the second epitaxial layer, The plurality of gate electrode layers include a first gate electrode layer adjacent to the substrate and a second gate electrode layer adjacent to the first gate electrode layer, and Wherein, a first spacing between a lower surface of the second gate electrode layer in the cell array region and an upper surface of the substrate in the cell array region is greater than a second spacing between a lower surface of the second gate electrode layer in the connection region and an upper surface of the substrate in the connection region.

14. The vertical storage device according to claim 13, in, A height of an upper surface of the first epitaxial layer is lower than a height of an upper surface of the second epitaxial layer.

15. The vertical storage device according to claim 13, in, An upper surface of the substrate has a stepped portion at a boundary between the cell array region and the connection region, and vertical lengths of the plurality of channel structures are greater than vertical lengths of the plurality of dummy channel structures.

16. The vertical storage device according to claim 13, in, The first gate electrode layer includes a bent portion bent along an upper surface of the substrate.

17. A vertical storage device, include: A substrate comprising a first region and a second region adjacent to the first region; a first conductive layer extending over the first region and the second region; as well as a second conductive layer extending on the first region and the second region, the second conductive layer being stacked on the first conductive layer, wherein the upper surface of the substrate has a step portion at a boundary between the first region and the second region, and the upper surface of the substrate in the first region is lower than the upper surface of the substrate in the second region, and A third interval between a lower surface of the first conductive layer in the first region and an upper surface of the substrate in the first region is greater than a fourth interval between a lower surface of the first conductive layer in the second region and an upper surface of the substrate in the second region.

18. The vertical storage device according to claim 17, in, A difference between the third interval and the fourth interval is the same as a height of the step portion.

19. A vertical storage device, include: A substrate, comprising a cell array region and a connection region adjacent to the cell array region; A plurality of gate electrode layers are stacked on the cell array region and the connection region of the substrate and form a stepped structure in the connection region; a plurality of channel structures in the cell array region, the plurality of channel structures passing through the plurality of gate electrode layers; as well as a plurality of dummy channel structures in the connection region, the plurality of dummy channel structures passing through at least one of the plurality of gate electrode layers, wherein the upper surface of the substrate has a step portion at a boundary between the cell array region and the connection region, The vertical lengths of the plurality of channel structures are greater than the vertical lengths of the plurality of dummy channel structures, A first gate electrode layer of the plurality of gate electrode layers is adjacent to the substrate; and A buffer insulating layer is provided between the first gate electrode layer and the substrate, The thickness of the buffer insulating layer in the cell array region is greater than the thickness of the buffer insulating layer in the connection region.

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