An LED chip with a high-stability current blocking layer

Abstract

The present invention discloses an LED chip with a high-stability current blocking layer, comprising a DBR reflective layer, an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, a current blocking layer and a P-type electrode, wherein the P-type semiconductor layer is arranged above the light-emitting layer, and the P-type semiconductor layer is provided with a first annular groove. The beneficial effect of the present invention is as follows: before growing silicon dioxide, the present invention designs the surface structure of the P-type semiconductor layer, etches a first annular groove on the P-type semiconductor layer and directly below the P-type electrode, and then grows silicon dioxide, so that the formed current blocking layer is tightly combined with the P-type semiconductor layer, the structure is stable, and the current blocking layer is not easy to fall off from the P-type semiconductor layer. The depth of the first annular groove on the P-type semiconductor layer is 500A, which will not damage the structural performance of the P-type semiconductor, and the depth of the second annular groove on the N-type semiconductor layer is 500A, which will not damage the structural performance of the N-type semiconductor layer.

Description

Technical Field

[0001] The invention relates to an LED chip, in particular to an LED chip with a high-stability current blocking layer, belonging to the technical field of LED chip application. Background Art

[0002] LED chips (i.e. light-emitting diodes) are mainly composed of three parts: substrate layer, epitaxial layer and chip layer. The substrate layer is sapphire Al2O3, with a thickness of about 400um; the epitaxial layer (i.e. the light-emitting layer, with a thickness of about 6um) includes a buffer layer, an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer; the chip layer includes a current blocking layer, a transparent conductive layer, a passivation protection layer and a P, N-type electrode layer, as well as a DBR reflective layer under the substrate.

[0003] The current blocking layer is a silicon dioxide film that is grown on the P-type semiconductor layer by plasma enhanced vapor deposition (PECVD) and is grown directly below the P-type electrode. It has the same shape as the P-type electrode and is slightly wider than the P-type electrode. The function of the current blocking layer is to increase the uniformity of current flow, thereby improving the luminous efficiency of the LED. Because the P-type electrode is opaque, the light emitted from this area is invalid light. In order to improve the luminous efficiency, a current blocking layer is grown in the invalid area directly below the P-type electrode to block the current, forcing the current that originally flows through the invalid area to flow to other valid areas.

[0004] The current blocking layer in the existing LED chip is directly grown on the P-type semiconductor layer. The adhesion between the current blocking layer and the P-type semiconductor layer is poor, and the bonding is poor. The current blocking layer is prone to fall off, which leads to the problem of chip electrode falling off. Summary of the invention

[0005] The purpose of the present invention is to solve the problem that the current blocking layer in the existing LED chip is directly grown on the P-type semiconductor layer, the adhesion between the current blocking layer and the P-type semiconductor layer is poor, the bonding is poor, and the current blocking layer is prone to falling off, thereby causing the chip to fall off the electrode, and to propose an LED chip with a high stability current blocking layer.

[0006] The objective of the present invention can be achieved by the following technical scheme: an LED chip with a high-stability current blocking layer, comprising a DBR reflective layer, an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, a current blocking layer and a P-type electrode, wherein the P-type semiconductor layer is arranged above the light-emitting layer, and the P-type semiconductor layer is provided with a first annular groove, the first annular groove is etched on the P-type semiconductor layer and directly below the P-type electrode, and silicon dioxide is grown, the silicon dioxide film is grown on the surface of the first annular groove, the formed current blocking layer is tightly combined with the P-type semiconductor layer, the structure is stable, and the current blocking layer is not easy to fall off from the P-type semiconductor layer, the current blocking layer is arranged above the first annular groove, and a passivation protection layer is arranged above the P-type semiconductor layer, and the current blocking layer is arranged at one end of the passivation protection layer;

[0007] The P-type electrode is arranged directly above the first annular groove, and the diameter of the first annular groove is smaller than the diameter of the P-type electrode, and the depth of the first annular groove is 500A;

[0008] A second annular groove is disposed above one end of the N-type semiconductor layer, and an N-type electrode is disposed above the second annular groove;

[0009] The diameter of the second annular groove is smaller than that of the N-type electrode, and the depth of the second annular groove is 500A. The depth of the first annular groove on the P-type semiconductor layer is 500A, which will not damage the structural performance of the P-type semiconductor. The depth of the second annular groove on the N-type semiconductor layer is 500A, which will not damage the structural performance of the N-type semiconductor layer. The thickness of the current blocking layer is 1600-2000A.

[0010] The preparation process of the LED chip specifically includes the following steps:

[0011] Step 1: Using metal organic chemical vapor deposition (MOCVD) equipment, on a sapphire substrate with a diameter of 4 inches, a buffer layer, an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer are grown in sequence by epitaxial growth to obtain an epitaxial wafer;

[0012] The epitaxial wafer is subjected to photolithography pattern preparation, a positive photoresist is used as a mask, and then an inductively coupled plasma device is used to etch the epitaxial wafer after photolithography, and the P-type semiconductor layer, the light-emitting layer and the N-type semiconductor layer with a depth of 4000A on one side are removed to expose the N-type semiconductor table, thereby obtaining the P-type semiconductor layer and the N-type semiconductor layer;

[0013] Step 2: The product obtained in step 1 is subjected to photolithography pattern preparation, a positive photoresist is used as a mask, and then an inductively coupled plasma device is used to etch away the P-type semiconductor with a depth of 500 Å on the P-type semiconductor layer and the N-type semiconductor with a depth of 500 Å on the N-type semiconductor layer, thereby obtaining a first annular groove and a second annular groove on the P-type semiconductor layer and the N-type semiconductor layer;

[0014] Step 3: using a plasma enhanced chemical vapor deposition (PECVD) device, growing silicon dioxide on the first annular groove on the obtained P-type semiconductor layer to obtain a current blocking layer;

[0015] The method of growing silicon dioxide by plasma enhanced chemical vapor deposition is to chemically react SiH4 gas with N2O gas to generate product SiO2 which is deposited on the product. The chemical reaction formula is: SiH4 + 2N2O → SiO2 + 2H2 + 2N2.

[0016] Step 4: sputtering a transparent conductive layer;

[0017] Using magnetron sputtering equipment, sputtering and depositing an ITO film onto the product obtained in step 3 to obtain a transparent conductive layer. The material of the ITO film is indium tin oxide with a molecular ratio of Sn2O3:In2O3=1:9. The indium tin oxide (ITO) transparent conductive film is an n-type semiconductor material with a body-centered cubic ferromanganese structure. After Sn is doped into In2O3, the Sn element replaces the In element in the In2O3 lattice and exists in the form of SnO2;

[0018] Step 5: using electron beam evaporation equipment to evaporate metal films on the surface of the product obtained in step 4, the evaporated metal films are Cr, Al, Cr, Pt, Au in sequence, and then the metal films in the areas other than the positions of the P-type electrode and the N-type electrode are removed to obtain the P-type electrode and the N-type electrode;

[0019] Step 6: Use plasma enhanced chemical vapor deposition (PECVD) equipment to grow silicon dioxide as a passivation protective layer, and then remove the silicon dioxide above the P-type electrode and the N-type electrode to complete the preparation of the LED chip; the growth method of the passivation protective layer is the same as the growth method of the current blocking layer, both of which are to grow silicon dioxide. Silicon dioxide can be used as both a current blocking layer and a passivation layer of the LED chip to protect the chip from being corroded by water vapor in the external environment.

[0020] The preparation process of the first annular groove and the second annular groove specifically comprises the following steps:

[0021] S1: Spinning, using a spinner to evenly spin-coat a layer of positive photoresist on the product obtained in the above step 1;

[0022] S2: Photolithography mask. Use a photolithography machine to place the product obtained in S1 under the photoresist plate engraved with the ring pattern, align the position, and then perform exposure processing. The part of the photoresist covered by the pattern is not exposed, and the part of the photoresist not covered by the pattern is exposed;

[0023] S3: Development, using a developer, putting the product obtained in S2 into a developer, the photoresist of the exposed part reacts with the developer and is dissolved, while the photoresist of the unexposed part is not dissolved, so that on the obtained product, the part where the pattern needs to be etched is not blocked by the photoresist, and the part where the pattern does not need to be etched is blocked by the photoresist;

[0024] S4: Plasma etching, using inductively coupled plasma etching (ICP) equipment to etch the developed product, the part not blocked by the photoresist is etched away, and the part blocked by the photoresist is not etched;

[0025] S5: Degumming and cleaning: the etched product is placed in a degumming solution for cleaning, and the degumming solution dissolves all the photoresist;

[0026] S6: After degumming and cleaning, the product is dried in a dryer, and the obtained product has a first annular groove and a second annular groove.

[0027] A further technical improvement of the present invention is that a sapphire substrate layer is arranged above the DBR reflective layer, and a buffer layer is arranged above the sapphire substrate layer.

[0028] A further technical improvement of the present invention is that a transparent conductive layer is provided between the P-type semiconductor layer and the passivation protection layer.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] 1. The present invention provides an LED chip with a high-stability current blocking layer. Before growing silicon dioxide, the surface structure of the P-type semiconductor layer is designed. A first annular groove is etched on the P-type semiconductor layer and directly below the P-type electrode, and silicon dioxide is then grown. The silicon dioxide film is grown on the surface of the first annular groove. The formed current blocking layer is tightly combined with the P-type semiconductor layer, has a stable structure, and is not easy to fall off from the P-type semiconductor layer.

[0031] 2. The present invention provides an LED chip with a high-stability current blocking layer. Before growing an N-type electrode, a surface structure design is performed on the N-type semiconductor layer. A second annular groove is etched on the N-type semiconductor and directly below the N-type electrode. Then the N-type electrode is grown. The N-type electrode is grown on the surface of the second annular groove. The formed N-type electrode is tightly combined with the N-type semiconductor layer, has a stable structure, and the N-type electrode will not fall off.

[0032] 3. The depth of the first annular groove on the P-type semiconductor layer is 500A, which will not damage the structural performance of the P-type semiconductor. The depth of the second annular groove on the N-type semiconductor layer is 500A, which will not damage the structural performance of the N-type semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to facilitate understanding by those skilled in the art, the present invention is further described below with reference to the accompanying drawings.

[0034] Figure 1 It is a schematic diagram of the overall structure of the present invention.

[0035] Figure 2 This is a schematic diagram of the structure of an existing LED chip of the present invention.

[0036] In the figure: 1. DBR reflective layer; 2. sapphire substrate layer; 3. buffer layer; 4. N-type semiconductor layer; 5. light-emitting layer; 6. P-type semiconductor layer; 7. current blocking layer; 8. transparent conductive layer; 9. passivation protection layer; 10. P-type electrode; 11. N-type electrode. DETAILED DESCRIPTION

[0037] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] See also Figure 1-2 As shown, an LED chip with a high-stability current blocking layer comprises a DBR reflective layer 1, an N-type semiconductor layer 4, a light-emitting layer 5, a P-type semiconductor layer 6, a current blocking layer 7 and a P-type electrode 10, wherein the P-type semiconductor layer 6 is arranged above the light-emitting layer 5, and the P-type semiconductor layer 6 is provided with a first annular groove, the first annular groove is etched on the P-type semiconductor layer 6 and directly below the P-type electrode 10, and silicon dioxide is grown, and a silicon dioxide film is grown on the surface of the first annular groove, the formed current blocking layer 7 is tightly combined with the P-type semiconductor layer 6, the structure is stable, and the current blocking layer 6 is not easy to fall off from the P-type semiconductor layer 6, the current blocking layer 7 is arranged above the first annular groove, and a passivation protection layer 9 is arranged above the P-type semiconductor layer 6, and the current blocking layer 7 is arranged at one end of the passivation protection layer 9;

[0039] The P-type electrode 10 is disposed directly above the first annular groove, and the diameter of the first annular groove is smaller than the diameter of the P-type electrode 10, and the depth of the first annular groove is 500A;

[0040] A second annular groove is disposed above one end of the N-type semiconductor layer 4, and an N-type electrode 11 is disposed above the second annular groove;

[0041] Among them, the diameter of the second annular groove is smaller than the N-type electrode 11, and the depth of the second annular groove is 500A, the depth of the first annular groove on the P-type semiconductor layer 6 is 500A, which will not damage the structural performance of the P-type semiconductor 6, and the depth of the second annular groove on the N-type semiconductor layer 4 is 500A, which will not damage the structural performance of the N-type semiconductor layer 4, and the thickness of the current blocking layer 7 is 1600-2000A;

[0042] The preparation process of the LED chip specifically includes the following steps:

[0043] Step 1: Using a metal organic chemical vapor deposition (MOCVD) device, a buffer layer 3, an N-type semiconductor layer 4, a light emitting layer 5 and a P-type semiconductor layer 6 are sequentially grown on a sapphire substrate having a diameter of 4 inches by an epitaxial growth method to obtain an epitaxial wafer;

[0044] The epitaxial wafer is subjected to photolithography pattern preparation, a positive photoresist is used as a mask, and then an inductively coupled plasma device is used to etch the epitaxial wafer after photolithography, so as to remove the P-type semiconductor layer (6), the light-emitting layer 5 and the N-type semiconductor layer 4 with a depth of about 4000 Å on one side, and expose the N-type semiconductor table, thereby obtaining the P-type semiconductor layer 6 and the N-type semiconductor layer 4;

[0045] Step 2: The product obtained in step 1 is subjected to photolithography pattern preparation, a positive photoresist is used as a mask, and then an inductively coupled plasma device is used to etch away the P-type semiconductor with a depth of 500A on the P-type semiconductor layer 6 and the N-type semiconductor with a depth of 500A on the N-type semiconductor layer 4, thereby obtaining a first annular groove and a second annular groove on the P-type semiconductor layer 6 and the N-type semiconductor layer 4;

[0046] Step 3: using a plasma enhanced chemical vapor deposition (PECVD) device, growing silicon dioxide on the first annular groove on the obtained P-type semiconductor layer 6 to obtain a current blocking layer;

[0047] The method of growing silicon dioxide by plasma enhanced chemical vapor deposition is to chemically react SiH4 gas with N2O gas to generate product SiO2 which is deposited on the product. The chemical reaction formula is: SiH4 + 2N2O → SiO2 + 2H2 + 2N2.

[0048] Step 4: sputtering a transparent conductive layer 8;

[0049] Using a magnetron sputtering device, sputtering and depositing an ITO film onto the product obtained in step 3 to obtain a transparent conductive layer 8. The material of the ITO film is indium tin oxide with a molecular ratio of Sn2O3:In2O3=1:9. The indium tin oxide (ITO) transparent conductive film is an n-type semiconductor material with a body-centered cubic ferromanganese structure. After Sn is doped into In2O3, the Sn element replaces the In element in the In2O3 lattice and exists in the form of SnO2.

[0050] Step 5: using electron beam evaporation equipment to evaporate metal films on the surface of the product obtained in step 4, the evaporated metal films are Cr, Al, Cr, Pt, Au in sequence, and then the metal films in the area other than the positions of the P-type electrode 10 and the N-type electrode 11 are removed to obtain the P-type electrode 10 and the N-type electrode 11;

[0051] Step 6: Use plasma enhanced chemical vapor deposition (PECVD) equipment to grow silicon dioxide as a passivation protective layer 9, and then remove the silicon dioxide above the P-type electrode 10 and the N-type electrode 11 to complete the preparation of the LED chip; the growth method of the passivation protective layer is the same as the growth method of the current blocking layer, both of which are to grow silicon dioxide. Silicon dioxide can be used as both a current blocking layer and a passivation layer of the LED chip to protect the chip from being corroded by water vapor in the external environment.

[0052] The preparation process of the first annular groove and the second annular groove specifically comprises the following steps:

[0053] S1: Spinning, using a spinner to evenly spin-coat a layer of positive photoresist on the product obtained in the above step 1;

[0054] S2: Photolithography mask. Use a photolithography machine to place the product obtained in S1 under the photoresist plate engraved with the ring pattern, align the position, and then perform exposure processing. The part of the photoresist covered by the pattern is not exposed, and the part of the photoresist not covered by the pattern is exposed;

[0055] S3: Development, using a developer, putting the product obtained in S2 into a developer, the photoresist of the exposed part reacts with the developer and is dissolved, while the photoresist of the unexposed part is not dissolved, so that on the obtained product, the part where the pattern needs to be etched is not blocked by the photoresist, and the part where the pattern does not need to be etched is blocked by the photoresist;

[0056] S4: Plasma etching, using inductively coupled plasma etching (ICP) equipment to etch the developed product, the part not blocked by the photoresist is etched away, and the part blocked by the photoresist is not etched;

[0057] S5: Degumming and cleaning: the etched product is placed in a degumming solution for cleaning, and the degumming solution dissolves all the photoresist;

[0058] S6: After degumming and cleaning, the product is dried in a dryer, and the obtained product has a first annular groove and a second annular groove.

[0059] A further technical improvement of the present invention is that a sapphire substrate layer 2 is arranged above the DBR reflective layer 1 , and a buffer layer 3 is arranged above the sapphire substrate layer 2 .

[0060] A further technical improvement of the present invention is that a transparent conductive layer 8 is provided between the P-type semiconductor layer 6 and the passivation protection layer 9 .

[0061] Compared with the prior art, the present invention has the following beneficial effects:

[0062] 1. The present invention provides an LED chip with a high-stability current blocking layer. Before growing silicon dioxide, the surface structure of the P-type semiconductor layer 6 is designed. A first annular groove is etched on the P-type semiconductor layer 6 and directly below the P-type electrode 10, and then silicon dioxide is grown. The silicon dioxide film grows on the surface of the first annular groove. The formed current blocking layer 7 is tightly combined with the P-type semiconductor layer 6, and the structure is stable. The current blocking layer 6 is not easy to fall off from the P-type semiconductor layer 6.

[0063] 2. The present invention provides an LED chip with a high-stability current blocking layer. Before growing the N-type electrode 11, the surface structure of the N-type semiconductor layer 4 is designed, and a second annular groove is etched on the N-type semiconductor 4 and directly below the N-type electrode 11, and then the N-type electrode 11 is grown. The N-type electrode 11 grows on the surface of the second annular groove. The formed N-type electrode 11 is tightly combined with the N-type semiconductor layer 4, and the structure is stable, and the N-type electrode 11 will not fall off.

[0064] 3. The depth of the first annular groove on the P-type semiconductor layer 6 is 500A, which will not damage the structural performance of the P-type semiconductor 6. The depth of the second annular groove on the N-type semiconductor layer 4 is 500A, which will not damage the structural performance of the N-type semiconductor layer 4.

[0065] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to only specific implementation methods. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. An LED chip with a high stability current blocking layer, characterized in that: The invention comprises a DBR reflective layer (1), an N-type semiconductor layer (4), a light-emitting layer (5), a P-type semiconductor layer (6), a current blocking layer (7) and a P-type electrode (10), wherein the P-type semiconductor layer (6) is arranged above the light-emitting layer (5), and the P-type semiconductor layer (6) is provided with a first annular groove, the current blocking layer (7) is arranged above the first annular groove, and a passivation protection layer (9) is arranged above the P-type semiconductor layer (6), and the current blocking layer (7) is arranged at one end of the passivation protection layer (9); The P-type electrode (10) is arranged directly above the first annular groove, the diameter of the first annular groove is smaller than the diameter of the P-type electrode (10), and the depth of the first annular groove is 500A; A second annular groove is provided above one end of the N-type semiconductor layer (4), and an N-type electrode (11) is provided above the second annular groove; The diameter of the second annular groove is smaller than that of the N-type electrode (11), the depth of the second annular groove is 500A, and the thickness of the current blocking layer (7) is 1600-2000A; The preparation process of the LED chip specifically includes the following steps: Step 1: using a metal organic chemical vapor deposition device, sequentially growing a buffer layer (3), an N-type semiconductor layer (4), a light emitting layer (5) and a P-type semiconductor layer (6) on a sapphire substrate having a diameter of 4 inches, to obtain an epitaxial wafer; The epitaxial wafer is subjected to photolithography pattern preparation, a positive photoresist is used as a mask, and then an inductively coupled plasma device is used to etch the epitaxial wafer after photolithography to remove the P-type semiconductor layer (6), the light-emitting layer (5) and the N-type semiconductor layer (4) with a depth of 4000 Å on one side, exposing the N-type semiconductor table, thereby obtaining the P-type semiconductor layer (6) and the N-type semiconductor layer (4); Step 2: The product obtained in step 1 is subjected to photolithography pattern preparation, a positive photoresist is used as a mask, and then an inductively coupled plasma device is used to etch away the P-type semiconductor with a depth of 500 Å on the P-type semiconductor layer (6) and the N-type semiconductor with a depth of 500 Å on the N-type semiconductor layer (4), thereby obtaining a first annular groove and a second annular groove on the P-type semiconductor layer (6) and the N-type semiconductor layer (4); Step 3: using plasma enhanced chemical vapor deposition equipment to grow silicon dioxide on the first annular groove on the obtained P-type semiconductor layer (6) to obtain a current blocking layer; Step 4: sputtering a transparent conductive layer (8); Using a magnetron sputtering device, sputtering and depositing an ITO film onto the product obtained in step 3 to obtain a transparent conductive layer (8), wherein the material of the ITO film is indium tin oxide; Step 5: using electron beam evaporation equipment to evaporate metal films on the surface of the product obtained in step 4, wherein the evaporated metal films are Cr, Al, Cr, Pt, and Au in sequence, and then the metal films in the areas other than the positions of the P-type electrode (10) and the N-type electrode (11) are removed to obtain the P-type electrode (10) and the N-type electrode (11); Step 6: Using plasma enhanced chemical vapor deposition equipment, grow silicon dioxide as a passivation protection layer (9), and then remove the silicon dioxide above the P-type electrode (10) and the N-type electrode (11), thereby completing the preparation of the LED chip; The preparation process of the first annular groove and the second annular groove specifically comprises the following steps: S1: Spinning, using a spinner to evenly spin-coat a layer of positive photoresist on the product obtained in the above step 1; S2: Photolithography mask. Use a photolithography machine to place the product obtained in S1 under the photoresist plate engraved with the ring pattern, align the position, and then perform exposure processing. The part of the photoresist covered by the pattern is not exposed, and the part of the photoresist not covered by the pattern is exposed; S3: Development, using a developer, putting the product obtained in S2 into a developer, the photoresist of the exposed part reacts with the developer and is dissolved, while the photoresist of the unexposed part is not dissolved, so that on the obtained product, the part where the pattern needs to be etched is not blocked by the photoresist, and the part where the pattern does not need to be etched is blocked by the photoresist; S4: plasma etching, using an inductively coupled plasma etching device to etch the developed product, the part not blocked by the photoresist is etched away, and the part blocked by the photoresist is not etched; S5: Degumming and cleaning: the etched product is placed in a degumming solution for cleaning, and the degumming solution dissolves all the photoresist; S6: After degumming and cleaning, the product is dried in a dryer, and the first annular groove and the second annular groove are obtained; A sapphire substrate layer (2) is arranged above the DBR reflective layer (1), and a buffer layer (3) is arranged above the sapphire substrate layer (2); A transparent conductive layer (8) is provided between the P-type semiconductor layer (6) and the passivation protection layer (9).

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