A Data Acquisition System Based on DSP and CPLD

Abstract

The present invention provides a data acquisition system based on DSP and CPLD, wherein the signal conditioning circuit collects the external analog quantity of the input signal, and the external analog quantity enters the dual 4-to-1 analog switch after passing through the signal conditioning circuit, and the dual 4-to-1 analog switch outputs the voltage signal to the AD7656 chip in a time-sharing manner; the AD7656 chip completes the digital quantity conversion of the input voltage signal, and the digital quantity is transmitted to the DSP chip through a 16-bit data bus, and the DSP and CPLD perform timing control on the AD7656 chip. The present invention simplifies the forward conditioning circuit, removes the ratio adjustment and level boosting and processing circuits required for sampling with the A / D on the DSP chip, reduces the sampling error, and on the other hand, broadens the working voltage range, and is more flexible to use.

Description

Technical Field

[0001] The invention relates to the field of anti-skid brakes in aircraft brake system engineering, in particular to a data acquisition system for anti-skid brakes. Background Art

[0002] At present, the most widely used aircraft braking system in my country is the digital fly-by-wire anti-skid braking system. The braking system calculates the servo valve control signal based on external analog signals such as command sensor signals, speed signals, and pressure signals, and adjusts the brake pressure in real time. The accuracy of data acquisition has a great influence on the control effect of the braking system, which requires the core control component of the braking system - the anti-skid brake control unit to have a high data acquisition capability.

[0003] The data acquisition system of the anti-skid brake control unit of the existing aircraft wheel brake system uses the AD converter of the CPU chip to complete the analog quantity acquisition function. Common ones are:

[0004] 1) The single-chip microcomputer JL80C196KB has an 8-channel, 8-bit resolution A / D converter with an input voltage range of 0 to 5V;

[0005] 2) The DSP chip TMS320F240 has a built-in 16-channel, 10-bit resolution A / D converter with an input voltage range of 0 to 5V;

[0006] 3) The DSP chip CMDSPF2812 has a built-in 16-channel, 12-bit resolution A / D converter with an input voltage range of 0 to 3.3V;

[0007] In practical applications, it is difficult to achieve ideal accuracy due to the influence of printed circuit board layout and wiring, external interference, bias error and other factors. The analog signal needs to be scaled down and clamped before AD acquisition can be performed. Summary of the invention

[0008] In order to overcome the deficiencies of the prior art, the present invention provides a data acquisition system based on DSP and CPLD.

[0009] The technical solution adopted by the present invention to solve its technical problem is:

[0010] A data acquisition system based on DSP and CPLD comprises a signal conditioning circuit, a dual 4-to-1 analog switch, an AD7656 chip, a CPLD complex programmable logic chip and a DSP chip; wherein the signal conditioning circuit collects the external analog quantity of the input signal, the external analog quantity enters the dual 4-to-1 analog switch after passing through the signal conditioning circuit, and the dual 4-to-1 analog switch outputs the voltage signal to the AD7656 chip in a time-sharing manner; the AD7656 chip is a 6-channel 16-bit analog-to-digital conversion chip, which completes the conversion of the input voltage signal into a digital quantity, and the digital quantity is transmitted to the DSP chip through a 16-bit data bus; the DSP and the CPLD perform timing control on the AD7656 chip, including AD7656 chip state configuration, data conversion start control and read enable control.

[0011] The data acquisition system based on DSP and CPLD has a total of 12 external analog signals as input, including 4 brake command signals, 2 wheel speed signals, 2 brake pressure signals, 2 servo valve voltage signals and 2 servo valve current signals. The external analog signals are processed by the signal conditioning circuit and input into two dual 4-to-1 analog switches respectively. The dual 4-to-1 analog switches include dual 4-to-1 analog switches 1 and dual 4-to-1 analog switches 2. Each dual 4-to-1 analog switch includes two channels, namely the first group of channels and the second group of channels. Each group of channels has 4 input terminals and 1 output terminal. The input terminal of the first group of channels of the dual 4-to-1 analog switch 1 is 1-4, the input end of the second group of channels of the dual 4-to-1 analog switch 1 is 5-8, and the interface correspondence is: 4-way brake command signal is input to the first group of 4-to-1 switches of the dual 4-to-1 analog switch 1, 2-way wheel speed signal and 2-way brake pressure signal are input to the second group of 4-to-1 switches of the dual 4-to-1 analog switch 1, 2-way servo valve voltage signal and 2-way servo valve current signal are input to the first group of 4-to-1 switches of the dual 4-to-1 analog switch 2, and the second group of 4-to-1 switches of the dual 4-to-1 analog switch 2 is a reserved interface; each dual 4-to-1 analog switch integrates two groups of channel-linked 4-to-1 analog switches, and the output logic of each 4-to-1 analog switch is:

[0012] When the level states of the selection signals P0 and P1 of the two channels in the 4-to-1 analog switch are both low, the two output terminals in the dual 4-to-1 analog switch are respectively connected to the first input terminal of each group of channels, that is, the two output terminals are respectively connected to the input terminals 1 and 5;

[0013] When the level states of the selection signals P0 and P1 of the two channels in the 4-to-1 analog switch are low and high respectively, the two output terminals in the dual 4-to-1 analog switch are respectively connected to the second input terminal of each group of channels, that is, the two output terminals are respectively connected to the input terminals 2 and 6;

[0014] When the level states of the selection signals P0 and P1 of the two channels in the 4-to-1 analog switch are high and low respectively, the two output terminals in the dual 4-to-1 analog switch are respectively connected to the third input terminal of each group of channels, that is, the two output terminals are respectively connected to the input terminals 3 and 7;

[0015] When the level states of the selection signals P0 and P1 of the two channels in the 4-to-1 analog switch are both high, the two output terminals in the dual 4-to-1 analog switch are respectively connected to the fourth input terminal of each group of channels, that is, the two output terminals are respectively connected to the input terminals 4 and 8;

[0016] The DSP chip is used to control the high and low levels of the selection signals P0 and P1 of the two channels to achieve the selected output of channels 1 to 4. Two 4-to-1 analog switches are used to realize the time-sharing acquisition of 12 analog signals. The 4-channel output signals of the two dual 4-to-1 analog switches are respectively connected to the 1-4 channel input terminals of the AD7656 analog-to-digital conversion chip, and channels 5 and 6 are reserved interfaces.

[0017] The data acquisition system of the DSP and CPLD adopts the parallel interface of the AD7656 chip, sets the PAR / SER pin of the AD7656 chip to a low level, and in 16-bit mode, sets the W / B pin of the AD7656 chip to a low level; the AD7656 is externally connected to a 2.5V reference voltage so that the amplitude of the sampling signal is between ±10V, matching the voltage range output by the signal conditioning circuit.

[0018] The AD7656 chip has three conversion start enable signals, among which CONVEST A controls the 1st / 2nd channel, CONVESTB controls the 3rd / 4th channel, and CONVEST C controls the 5th / 6th channel. When designing the CPLD circuit, the three enable signals CONVEST A / B / C are connected together. Each time the AD7656 chip converts, the synchronous sampling of all 6 channels is started. During the sampling process, the CPLD keeps CONVEST at a high level. During the sampling process, the sampling mark BUSY signal issued by the AD7656 is at a high level. After the sampling is completed, BUSY becomes a low level. The falling edge of the BUSY signal triggers the DSP chip to enter the external analog quantity acquisition and reading interrupt. The DSP enables the RD signal for the first time, and reads the data conversion result of the 1st channel of the AD7656 chip into the corresponding storage address of the DSP through the 16-bit data bus. The RD signal is enabled for the second time, and the data conversion result of the 2nd channel of the AD7656 chip is read into the corresponding storage address of the DSP through the 16-bit data bus. By analogy, the RD signal is enabled 6 times to complete the data reading of all 6 channels of the AD7656.

[0019] The beneficial effect of the present invention is that the traditional data acquisition system uses the A / D converter of the CPU chip to complete the sampling work. In practical applications, it is difficult to achieve ideal accuracy due to the influence of various aspects such as the layout and wiring of the printed circuit board, external interference, and bias error. In addition, the analog input voltage range of the A / D is 0-3.3V or 0-5V, which makes it difficult to accurately test a signal, affecting the acquisition effect. The analog-to-digital conversion chip AD7656 used in the present invention is a high-speed, low-power, 6-channel, 16-bit successive approximation (SAR) synchronous sampling analog-to-digital converter. It supports bipolar input and the input voltage range can reach ±10V; it simplifies the forward conditioning circuit, removes the ratio adjustment and level boost and processing circuit required for sampling with the A / D on the DSP chip, reduces the sampling error, and on the other hand, broadens the working voltage range, making it more flexible to use. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a block diagram of the data acquisition system of the present invention.

[0021] Figure 2 It is a control flow chart of the present invention. DETAILED DESCRIPTION

[0022] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0023] In order to improve the data acquisition system of the anti-skid brake control unit of the existing aircraft wheel brake system, the data acquisition accuracy is low, the interface circuit is complex and other problems, the present invention proposes a data acquisition system based on DSP and CPLD, which can maximize the data acquisition accuracy, support bipolar input, and the input voltage range can reach ±10V. The number of input channels can be expanded according to actual needs, with a resolution of 16 bits, simplified forward conditioning circuits, and the ratio adjustment and level boost and processing circuits required for directly using the A / D sampling on the CPU controller chip are removed, thereby reducing the sampling error. On the other hand, the operating voltage range is widened, and the use is more flexible.

[0024] The present invention proposes a data acquisition system based on DSP and CPLD. The whole system is composed of a forward acquisition circuit with a signal conditioning circuit and an A / D converter. The A / D conversion is controlled by the CPLD. After the conversion is completed, the DSP is triggered to enter an interrupt and perform a data reading operation. This design has been successfully applied to a certain type of anti-skid brake control module. Experiments have shown that the data acquisition accuracy of the BCU is greatly increased, achieving the goal of improving the analog quantity acquisition effect.

[0025] This embodiment takes an anti-skid brake control module as the target product and constructs a data acquisition system based on DSP and CPLD. The structural block diagram of the data acquisition system is shown in FIG. Figure 1A data acquisition system based on DSP and CPLD includes a signal conditioning circuit, a dual 4-to-1 analog switch, an AD7656 chip, a CPLD complex programmable logic chip and a DSP chip; wherein the signal conditioning circuit collects the external analog quantity of the input signal, and the external analog quantity enters the dual 4-to-1 analog switch after passing through the signal conditioning circuit, and the dual 4-to-1 analog switch outputs 12 voltage signals to the AD7656 chip in a time-sharing manner; the AD7656 chip is a 6-channel 16-bit analog-to-digital conversion chip, which completes the digital quantity conversion of the input voltage signal, and the digital quantity is transmitted to the DSP chip through a 16-bit data bus; the DSP and CPLD are the core control components of the system, which realize the timing control of the AD7656 chip, including the AD7656 chip state configuration, data conversion start control and read enable control.

[0026] The external analog signal is processed by the signal conditioning circuit and then input to the dual 4-to-1 analog switch. The dual 4-to-1 analog switch consists of two groups of 4-channel inputs. By controlling the high and low levels of the two channel selection signals P0 and P1, the 1-4 channels are gated and output. The present invention uses two analog switches to collect 12 analog signals. The 4 output signals of the 2-channel analog switch are respectively connected to the 1-4 channel input terminals of the AD7656 analog-to-digital conversion chip.

[0027] The data acquisition system based on DSP and CPLD has a total of 12 external analog signals as input, including 4 brake command signals, 2 wheel speed signals, 2 brake pressure signals, 2 servo valve voltage signals and 2 servo valve current signals. The external analog signals are processed by the signal conditioning circuit and input into two dual 4-to-1 analog switches respectively. The dual 4-to-1 analog switches include dual 4-to-1 analog switches 1 and dual 4-to-1 analog switches 2. Each dual 4-to-1 analog switch includes two channels, namely the first group of channels and the second group of channels. Each group of channels has 4 input terminals and 1 output terminal. The input terminal of the first group of channels of the dual 4-to-1 analog switch 1 is 1-4, the input end of the second group of channels of the dual 4-to-1 analog switch 1 is 5-8, and the interface correspondence is: 4-way brake command signal is input to the first group of 4-to-1 switches of the dual 4-to-1 analog switch 1, 2-way wheel speed signal and 2-way brake pressure signal are input to the second group of 4-to-1 switches of the dual 4-to-1 analog switch 1, 2-way servo valve voltage signal and 2-way servo valve current signal are input to the first group of 4-to-1 switches of the dual 4-to-1 analog switch 2, and the second group of 4-to-1 switches of the dual 4-to-1 analog switch 2 is a reserved interface; each dual 4-to-1 analog switch integrates two groups of channel-linked 4-to-1 analog switches, and the output logic of each 4-to-1 analog switch is:

[0028] When the level states of the selection signals P0 and P1 of the two channels in the 4-to-1 analog switch are both low, the two output terminals in the dual 4-to-1 analog switch are respectively connected to the first input terminal of each group of channels, that is, the two output terminals are respectively connected to the input terminals 1 and 5;

[0029] When the level states of the selection signals P0 and P1 of the two channels in the 4-to-1 analog switch are low and high respectively, the two output terminals in the dual 4-to-1 analog switch are respectively connected to the second input terminal of each group of channels, that is, the two output terminals are respectively connected to the input terminals 2 and 6;

[0030] When the level states of the selection signals P0 and P1 of the two channels in the 4-to-1 analog switch are high and low respectively, the two output terminals in the dual 4-to-1 analog switch are respectively connected to the third input terminal of each group of channels, that is, the two output terminals are respectively connected to the input terminals 3 and 7;

[0031] When the level states of the selection signals P0 and P1 of the two channels in the 4-to-1 analog switch are both high, the two output terminals in the dual 4-to-1 analog switch are respectively connected to the fourth input terminal of each group of channels, that is, the two output terminals are respectively connected to the input terminals 4 and 8;

[0032] The DSP chip is used to control the high and low levels of the selection signals P0 and P1 of the two channels to achieve the selected output of channels 1 to 4. Two 4-to-1 analog switches are used to realize the time-sharing acquisition of 12 analog signals. The 4-channel output signals of the two dual 4-to-1 analog switches are respectively connected to the 1-4 channel input terminals of the AD7656 analog-to-digital conversion chip. Channels 5 and 6 are reserved interfaces (which can be expanded according to the actual number of input signals of the system).

[0033] The data acquisition system of the DSP and CPLD adopts the parallel interface of the AD7656 chip, sets the PAR / SER pin of the AD7656 chip to a low level, and the 16-bit mode means setting the W / B pin of the AD7656 chip to a low level; the AD7656 is connected to an external 2.5V reference voltage, so that the amplitude of the sampling signal is between ±10V (RANGE=±4×reference voltage) (by configuring the HW / SW pin of the AD7656 chip to be low level, the REFEN / WR pin to be low level, and the RANGE pin to be low level), matching the voltage range output by the signal conditioning circuit. The AD7656 works in the parallel interface mode, and the timing of the CONVST signal, CS signal, and RD signal is designed according to the timing diagram specified in the component manual. The conversion time tCONVERT is typically 3μs, the sampling time tACQ≤550ns, and the time to read RD is ≥36ns.

[0034] The AD7656 chip has three conversion start enable signals, among which CONVEST A controls the 1st / 2nd channel, CONVESTB controls the 3rd / 4th channel, and CONVEST C controls the 5th / 6th channel. When designing the CPLD circuit, CONVEST A / B / C The three enable signals are connected together through hard wires. Each time the AD7656 chip converts, the corresponding synchronous sampling of all six channels is started. During the sampling process, the CPLD keeps CONVEST at a high level. During the sampling process, the sampling identification BUSY signal issued by the AD7656 is at a high level. After the sampling is completed, BUSY becomes a low level. The falling edge of the BUSY signal triggers the DSP chip to enter the external analog quantity acquisition and reading interrupt. The DSP enables the RD signal (falling edge enable) for the first time, and reads the data conversion result of the first channel of the AD7656 chip into the corresponding storage address of the DSP through the 16-bit data bus. The RD signal is enabled for the second time, and the data conversion result of the second channel of the AD7656 chip is read into the corresponding storage address of the DSP through the 16-bit data bus. And so on. The RD signal is enabled six times to complete the data reading of all six channels of the AD7656.

[0035] The control process of product data collection is as follows Figure 2 As shown, after power-on, the initialization of each part must be completed first. The main steps are as follows:

[0036] 1) Initialize the DSP internal status register, general GPIO port, interrupt and corresponding peripherals, configure the NMI interrupt trigger as falling edge trigger, and enable the interrupt.

[0037] 2) DSP sends an initialization signal to CPLD, which then completes the working mode setting of the AD7656 digital-to-analog conversion chip.

[0038] After initialization is completed, the channel selection of the dual 4-to-1 analog switch is set to channel 1; sampling starts and enters the sampling stage. At this time, the conversion flag BUSY signal of the AD7656 digital-to-analog conversion chip continues to be high, and the DSP can run other programs normally. When the AD7656 digital-to-analog conversion chip completes the data sampling of all 6 channels, the conversion BUSY flag will change from high to low. The falling edge triggers the DSP to enter the external analog quantity acquisition and reading interrupt. The DSP executes the analog quantity data reading operation and stores the A / D sampling results in the storage space in sequence to complete the collection of the first set of data. Subsequently, the channels of the dual 4-to-1 analog switch are selected as channels 2, 3, and 4 respectively to complete the collection of the other three sets of data.

Claims

1. A data acquisition system based on DSP and CPLD, characterized in that: The data acquisition system based on DSP and CPLD comprises a signal conditioning circuit, a dual 4-to-1 analog switch, an AD7656 chip, a CPLD complex programmable logic chip and a DSP chip; The signal conditioning circuit collects the external analog quantity of the input signal, and the external analog quantity enters the dual 4-to-1 analog switch after the signal conditioning circuit, and the dual 4-to-1 analog switch outputs the voltage signal to the AD7656 chip in a time-sharing manner; the AD7656 chip is a 6-channel 16-bit analog-to-digital conversion chip, which completes the digital quantity conversion of the input voltage signal, and the digital quantity is transmitted to the DSP chip through the 16-bit data bus; the DSP and CPLD perform timing control on the AD7656 chip, including AD7656 chip state configuration, data conversion start control and read enable control; The data acquisition system based on DSP and CPLD has a total of 12 external analog signals as input, including 4 brake command signals, 2 wheel speed signals, 2 brake pressure signals, 2 servo valve voltage signals and 2 servo valve current signals. The external analog signals are processed by the signal conditioning circuit and input into two dual 4-to-1 analog switches respectively. The dual 4-to-1 analog switches include dual 4-to-1 analog switches 1 and dual 4-to-1 analog switches 2. Each dual 4-to-1 analog switch includes two channels, namely the first group of channels and the second group of channels. Each group of channels has 4 input terminals and 1 output terminal. The input terminal of the first group of channels of the dual 4-to-1 analog switch 1 is 1-4, the input end of the second group of channels of the dual 4-to-1 analog switch 1 is 5-8, and the interface correspondence is: 4-way brake command signal is input to the first group of 4-to-1 switches of the dual 4-to-1 analog switch 1, 2-way wheel speed signal and 2-way brake pressure signal are input to the second group of 4-to-1 switches of the dual 4-to-1 analog switch 1, 2-way servo valve voltage signal and 2-way servo valve current signal are input to the first group of 4-to-1 switches of the dual 4-to-1 analog switch 2, and the second group of 4-to-1 switches of the dual 4-to-1 analog switch 2 is a reserved interface; each dual 4-to-1 analog switch integrates two groups of channel-linked 4-to-1 analog switches, and the output logic of each 4-to-1 analog switch is: When the level states of the selection signals P0 and P1 of the two channels in the 4-to-1 analog switch are both low, the two output terminals in the dual 4-to-1 analog switch are respectively connected to the first input terminal of each group of channels, that is, the two output terminals are respectively connected to the input terminals 1 and 5; When the level states of the selection signals P0 and P1 of the two channels in the 4-to-1 analog switch are low and high respectively, the two output terminals in the dual 4-to-1 analog switch are respectively connected to the second input terminal of each group of channels, that is, the two output terminals are respectively connected to the input terminals 2 and 6; When the level states of the selection signals P0 and P1 of the two channels in the 4-to-1 analog switch are high and low respectively, the two output terminals in the dual 4-to-1 analog switch are respectively connected to the third input terminal of each group of channels, that is, the two output terminals are respectively connected to the input terminals 3 and 7; When the level states of the selection signals P0 and P1 of the two channels in the 4-to-1 analog switch are both high, the two output terminals in the dual 4-to-1 analog switch are respectively connected to the fourth input terminal of each group of channels, that is, the two output terminals are respectively connected to the input terminals 4 and 8; The DSP chip is used to control the high and low levels of the selection signals P0 and P1 of the two channels to achieve the selected output of channels 1 to 4. Two 4-to-1 analog switches are used to realize the time-sharing acquisition of 12 analog signals. The 4-channel output signals of the two dual 4-to-1 analog switches are respectively connected to the 1-4 channel input terminals of the AD7656 analog-to-digital conversion chip, and channels 5 and 6 are reserved interfaces.

2. A data acquisition system based on DSP and CPLD according to claim 1, characterized in that: The data acquisition system of the DSP and CPLD adopts the parallel interface of the AD7656 chip, sets the PAR / SER pin of the AD7656 chip to a low level, and in 16-bit mode, sets the W / B pin of the AD7656 chip to a low level; the AD7656 is externally connected to a 2.5V reference voltage so that the amplitude of the sampling signal is between ±10V, matching the voltage range output by the signal conditioning circuit.

3. A data acquisition system based on DSP and CPLD according to claim 1, characterized in that: The AD7656 chip has three conversion start enable signals, among which CONVEST A controls the 1st / 2nd channel, CONVEST B controls the 3rd / 4th channel, and CONVEST C controls the 5th / 6th channel. When designing the CPLD circuit, the three enable signals CONVEST A / B / C are connected together. Each time the AD7656 chip converts, the synchronous sampling of all the corresponding 6 channels is started. During the sampling process, the CPLD keeps CONVEST at a high level. During the sampling process, the sampling mark BUSY signal issued by the AD7656 is at a high level. After the sampling is completed, BUSY becomes a low level. The falling edge of the BUSY signal triggers the DSP chip to enter the external analog quantity acquisition and reading interrupt. The DSP enables the RD signal for the first time, and reads the data conversion result of the first channel of the AD7656 chip into the corresponding storage address of the DSP through the 16-bit data bus. The RD signal is enabled for the second time, and the data conversion result of the second channel of the AD7656 chip is read into the corresponding storage address of the DSP through the 16-bit data bus. By analogy, the RD signal is enabled 6 times to complete the data reading of all 6 channels of the AD7656.

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