power amplifier

Abstract

Various embodiments of the present invention provide a power amplifier comprising: a clamping circuit (N1) configured to provide a clamping voltage from a power supply; an amplifier pair (N2) having a plurality of first input terminals coupled to the clamping circuit, a plurality of second input terminals, and an output terminal for providing an amplified signal; and a bias circuit (N3) coupled between the clamping circuit and the plurality of second input terminals of the amplifier pair and configured to adjust an input bias voltage of the amplifier pair so that an output bias voltage of the amplifier pair changes proportionally with a change in the power supply voltage.

Description

[0001] This application is a divisional application of the Chinese invention patent application with application date of June 30, 2014, application number 201410320670.1, and invention name “POWER AMPLIFIER”. Technical Field

[0002] The exemplary and non-limiting embodiments of the present invention relate generally to power amplifiers, and more particularly to a car audio power amplifier. Background Art

[0003] During the daily commute in modern cities, especially during rush hour, people often find themselves stuck in heavy traffic. To reduce carbon dioxide emissions and other pollutants when cars are stuck in traffic or waiting at traffic lights, most automakers have introduced a start-stop engine function for their cars. With this start-stop engine function, the car engine will automatically shut down when the car is stuck in a traffic jam, and then restart when the traffic jam clears and the car continues to move forward. When the car engine restarts, a large inrush current is suddenly drawn from the car battery, causing the battery voltage to drop rapidly. After the car engine restarts, the battery voltage will return to its normal value. The power supply voltage of the in-car entertainment system comes directly from the car battery, so the in-car entertainment system will experience the same voltage changes throughout the start-stop process.

[0004] Typically, when a car engine is started, the capacitors in the external circuits used to establish the quiescent operating point will discharge rapidly. This will cause the car radio system's power amplifier to malfunction, muting the car audio system's power amplifier and resulting in no sound (including transient noise from the speakers).

[0005] Today, people are constantly pursuing an increasingly comfortable driving experience, placing much higher performance demands on in-car entertainment systems than ever before. Therefore, interruptions in audio output are unacceptable, even during the active state. Current in-car sound quality standards also prohibit such interruptions.

[0006] To avoid these issues, a well-known external circuit solution is often used. This solution further incorporates a DC / DC regulator to stabilize the battery voltage during the start-stop period. However, this solution requires several external devices and bulky LC components, increasing overall cost, board size, and system complexity.

[0007] Therefore, another solution that is often used in automobiles is proposed. In this solution, the minimum operating voltage is set to half of the supply voltage Vcc (for example, half of the battery voltage. If the battery voltage is 12V, then Vcc / 2=12V / 2=6V). The typical circuit structure of this solution is Figure 1 As shown in FIG, the circuit includes a clamping circuit M1, a class AB amplifier M2 and a common mode feedback (CMFB) circuit M3. Figure 1 In the circuit shown, clamp circuit M1 is configured to provide a clamp voltage Vsvr = Vcc / 4 at the SVR (supply voltage rejection) node to Class AB amplifier M2 as its input bias voltage. A Class AB amplifier is a typical amplifier circuit structure used to drive speakers in car radio systems. It typically includes a pair of amplifiers (such as operational amplifiers) and four feedback resistors, Rf1, Rf2, Re1, and Re2, typically coupled between the outputs and inputs of the pair of amplifiers. Typically, in such amplifier circuits, the resistances of resistors Rf1 and Rf2 are set equal and equal to 20 times the resistances of resistors Re1 and Re2, i.e., Rf1 = Rf2 = 20Re1 = 20Re2. A common-mode feedback circuit M3 is provided between the outputs and inputs of the pair of amplifiers to absorb quiescent current flowing from the outputs to the inputs. This common-mode feedback maintains the DC bias of the outputs of the pair of amplifiers at Vcc / 2, and the AC gains of the outputs OUTP and OUTM of the pair of amplifiers remain equal. In this solution, the inputs of the two amplifiers are biased at one-quarter of the power supply (i.e., Vcc / 4), while the outputs of the two amplifiers are biased at half the power supply (i.e., Vcc / 2). In this way, when the power supply voltage suddenly drops from Vcc to Vcc / 2 during startup, the outputs of the amplifiers will also decrease proportionally with the drop in power supply voltage, thus ensuring that the entire amplifier circuit can still operate normally.

[0008] However, while the common-mode feedback solution can solve the start-stop problem, it also introduces a positive feedback loop, which can significantly affect the stability of the entire audio system, especially during vehicle power-up. For example, if the external load is a capacitive load such as 10nF, this circuit may cause unwanted oscillations. In practical applications, external capacitance is unavoidable. For example, if the speaker has a 2 ohm resistor, oscillations are inevitable unless the capacitance introduced by the speaker is less than 2nF, which is impractical. Summary of the Invention

[0009] An exemplary embodiment of the present invention provides a new power amplifier for a car audio system. The proposed power amplifier eliminates a common-mode feedback circuit, thereby avoiding the possibility of causing oscillation even when a large capacitive load is connected, thereby making the car audio system more stable.

[0010] A first aspect of the present invention relates to a power amplifier comprising: a clamping circuit (N1) configured to provide a clamping voltage from a power supply; an amplifier pair (N2) having a plurality of first input terminals coupled to the clamping circuit, an output terminal for providing an amplified signal, and a plurality of second input terminals; and a bias circuit (N3) coupled between the clamping circuit and the plurality of second input terminals of the amplifier pair and configured to adjust an input bias voltage of the amplifier pair so that an output bias voltage of the amplifier pair changes proportionally with a change in the power supply voltage.

[0011] A second aspect of the present invention relates to a method for adjusting the bias voltage of a power amplifier including a clamping circuit, a bias circuit, and an amplifier pair, the method comprising: providing a clamping voltage from a power supply by the clamping circuit; adjusting an input bias voltage of the amplifier pair by the bias circuit so that an output bias voltage of the amplifier pair changes proportionally with a change in the power supply voltage; and providing an amplified signal by the amplifier pair.

[0012] A third aspect of the present invention relates to a bias circuit comprising: a first buffer and a second buffer, each of which has at least one input and one output. The first buffer has an input coupled to an input node; the output of the first buffer is coupled to the first input of the second buffer via a first resistor; the input node is coupled to the second input of the second buffer; a second resistor is coupled between the output and the first input of the second buffer; and the output of the second buffer is coupled to a plurality of bias resistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The various embodiments, preferred modes of use and other objects of the present invention may be better understood by referring to the following embodiments described in conjunction with the accompanying drawings. In the drawings, like reference numerals generally refer to like elements.

[0014] Figure 1 is a schematic diagram showing a power amplifier circuit including common-mode feedback in the prior art;

[0015] Figure 2 is a block diagram showing a power amplifier circuit according to an embodiment of the present invention;

[0016] Figure 3 is a schematic diagram showing a power amplifier circuit according to an embodiment of the present invention;

[0017] Figure 4shows simulation results of an example of a power amplifier circuit according to an embodiment of the present invention; and

[0018] Figure 5 is a flow chart illustrating a method for adjusting a bias voltage of a power amplifier circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] Some preferred embodiments will be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, the present disclosure can be implemented in many ways and should not be construed as being limited to the embodiments disclosed herein. On the contrary, these embodiments are provided to provide a thorough and complete understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0020] In the following, several alternatives will be used to describe various embodiments and implementations of the present invention and its various aspects. It should be noted that, depending on specific needs and limitations, all alternatives described may be provided individually or in any possible combination (including combinations of individual functions of various alternatives).

[0021] First reference Figure 2 , which shows a block diagram of a power amplifier circuit according to an embodiment of the present invention. Figure 2 As shown in FIG, the power amplifier circuit of the proposed car audio system mainly includes three modules, namely, a clamping circuit N1, an amplifier pair (for example, a Class AB amplifier) ​​N2, and a bias circuit N3. Figure 1 Similar to that shown in .

[0022] The following will refer to Figure 3 Each circuit block N1 , N2 , N3 is described in more detail. Figure 3 FIG. 4 shows a schematic diagram of a power amplifier circuit according to an embodiment of the present invention.

[0023] like Figure 3 As shown, the clamping circuit N1 may include two resistors R1 and R2 connected in series between the power supply (Vcc) and the ground. In this embodiment, the resistance of the resistor R1 may preferably be set to 3 times that of the resistor R2, i.e., R1=3R2. In this preferred case, the voltage divided between the resistors R1 and R2 is Vcc / 4, which may be coupled to the SVR (supply voltage suppression) node, for example, via the resistor R3. The SVR node may be connected to the SVR node via a large external capacitor C SVRCoupled to ground, this large capacitor typically has a capacitance of 10 μF. Due to this large capacitance, when the power supply voltage suddenly drops from, for example, Vcc to Vcc / 2, there is no rapid discharge, so the voltage at the SVR node is clamped at approximately Vcc / 4. This clamped voltage can, in turn, be coupled to the non-inverting inputs of the two amplifiers AMP+ and AMP- of amplifier pair N2 via two bias resistors R4 and R5, respectively, to provide input bias voltages therefor.

[0024] Despite Figure 3 Two resistors R1 and R2 are shown in the figure, but a person skilled in the art should understand that the number of voltage dividing resistors connected in series between the power supply and the ground is not limited to two. Any number of resistors can be used as long as they can divide the power supply voltage as needed to obtain the desired voltage dividing value.

[0025] Amplifier pair N2 as above reference Figure 1 The circuit is configured as shown and generally includes a pair of amplifiers (i.e., a first amplifier AMP+ and a second amplifier AMP-) and four feedback resistors Rf1, Rf2, Re1, and Re2, which are generally coupled between the respective outputs and inputs of the pair of amplifiers. In one embodiment, the resistance of resistor Rf1 is preferably set to 16 times the resistance of resistor Re1, i.e., Rf1=16Re1, and the resistance of Rf2 is preferably set to 20 times the resistance of resistors Re1 and Re2, i.e., Rf2=20Re1=20Re2. However, the present invention is not limited to any specific number or value of resistors, and the number and value of the feedback resistors can be adjusted accordingly based on actual application needs and performance requirements.

[0026] In practical applications, an input signal, such as an audio signal, can be input to the first input terminal (i.e., the non-inverting input terminal) of the first amplifier AMP+ via capacitor C_in. Capacitor C_in filters the DC component of the audio signal, thereby allowing a clean signal to be input to the non-inverting input terminal of the amplifier AMP+. An AC ground (ACGND) can be coupled to the first input terminal (i.e., the non-inverting input terminal) of the second amplifier AMP- via capacitor C_acgnd. Capacitors C_in and C_acgnd are both external coupling capacitors and typically have a capacitance of 220 nF.

[0027] and Figure 1 Compared to the amplifier circuit shown, Figure 3 The power amplifier circuit according to the embodiment of the present invention shown in FIG further includes a bias circuit N3 .

[0028] In one embodiment, the bias circuit N3 may include two buffer amplifiers (or simply buffers) B1 and B2 , wherein each of the buffers B1 and B2 has at least one input terminal and one output terminal.

[0029] One input of buffer amplifier B1 is coupled to an input node, or SVR node, and its output is coupled to a first input (i.e., the inverting input) of buffer amplifier B2. In this embodiment, buffer amplifier B1 can be configured to amplify, for example, by a factor of 2, the voltage Vsvr at its input SVR node when the power amplifier circuit is operating normally (i.e., the power supply remains constant at Vcc). However, when the power supply voltage drops from Vcc to Vcc / 2, buffer amplifier B1 outputs the voltage Vsvr at its input without amplification, thereby obtaining the voltage Vsvr at its output. Whether buffer amplifier B1 amplifies its input can be switched under control of internal circuitry (not shown). For example, if the power supply voltage drops beyond a predetermined threshold, the internal circuitry can trigger buffer amplifier B1 to switch from a gain-of-two amplifier to a gain-of-unity amplifier.

[0030] Furthermore, a resistor R7 may be further coupled between the output of buffer amplifier B1 and the first input (i.e., the inverting input) of buffer amplifier B2. With this configuration, the voltage at the SVR node may be coupled to the first input of buffer amplifier B2 via buffer amplifier B1 and resistor R7.

[0031] The second input terminal (i.e., the non-inverting input terminal) of the buffer amplifier B2 can be coupled to the SVR node. A feedback resistor R8 can be coupled between the first input terminal and the output terminal Vob of the buffer amplifier B2. In this embodiment, the resistance value of the resistor R7 can be preferably set to twice the resistance value of the resistor R8, i.e., R7 = 2R8.

[0032] The output Vob of the buffer amplifier B2 can be further coupled to the inverting input terminals of the two amplifiers AMP+ and AMP- of the amplifier pair N2 through two bias resistors Rb1 and Rb2, respectively, so as to provide input bias voltages therefor.

[0033] Two series-connected bias resistors Rb1 and Rb2 are connected in parallel with feedback resistors Re1 and Re2 between the inverting input terminals of a pair of amplifiers AMP+ and AMP-. In this embodiment, the resistance of Rb1 is preferably set to half that of Rf1, i.e., Rf1 = 2Rb1, and the resistance of Rb2 is preferably set to half that of Rf2, i.e., Rf2 = 2Rb2.

[0034] In another embodiment, bias circuit N3 may further include another buffer amplifier B3 coupled between node SVR and the second input terminal (i.e., the non-inverting input terminal) of buffer amplifier B2. Buffer amplifier B3 is configured to transmit the voltage at its input, i.e., voltage Vsvr at node SVR, to the subsequent circuit, i.e., buffer amplifier B2. As an example, buffer B3 can be implemented as a unity-gain buffer amplifier, for example, by connecting the output terminal and the inverting input terminal of an operational amplifier together and coupling a signal source to the non-inverting input terminal. Ideally, the input resistance of buffer B3 is infinite, and its output resistance is zero. Thus, buffer B3 prevents the subsequent circuit B2 from unacceptably loading the preceding circuit and interfering with its desired operation.

[0035] In the above example configuration, R1 = 3R2, R4 = R5, Rf1 = 2Rb1 = 16Re1, Rf2 = 2Rb2 = 20Re1 = 20Re2, and R7 = 2R8. In this example, when the power amplifier circuit is operating normally (i.e., when the power supply voltage does not drop and remains at Vcc), the voltage Vsvr at the SVR node is Vcc / 4. Due to the inherent characteristics of amplifiers AMP+ and AMP-, the amplifier input is biased at Vcc / 4. Simultaneously, the non-inverting input of buffer amplifier B2 is at Vcc / 4, and due to the characteristics of an operational amplifier, the inverting input of buffer amplifier B2 is also at Vcc / 4. When the power supply voltage is normal, buffer amplifier B1 amplifies its input voltage by two times and outputs 2Vsvr, or Vcc / 2. Given the proportional relationship between the resistance values ​​of R7 and R8, the output Vob of buffer amplifier B2 is Vcc / 8. From this, we can obtain the bias voltages at the outputs of amplifiers AMP+ and AMP- as Vcc / 4 + (Vcc / 4 - Vcc / 8) × Rf1 / Rb1 = Vcc / 2 and Vcc / 4 + (Vcc / 4 - Vcc / 8) × Rf2 / Rb2 = Vcc / 2, respectively. In other words, when the power supply voltage is normal, the outputs OUTP and OUTM of amplifier pair N2 are both biased at Vcc / 2.

[0036] In this example, the AC gain of the first amplifier AMP+ is (Rf1 / (Rb1(Re1+Re2) / (Rb1+Re1+Re2)))=10, and the AC gain of the second amplifier AMP- is -(Rf2 / (Re1+Re2))=-10. Thus, a total AC gain of 26 dB is achieved. Those skilled in the art will appreciate that the AC gain can be varied as desired by adjusting the resistance values ​​of the feedback resistors Rf1, Rf2, Re1, and Re2, and the bias resistors Rb1 and Rb2, and that the present invention is not limited to any particular configuration.

[0037] In the above example, when the start-stop process begins and the power supply voltage drops from Vcc to Vcc' (eg, Vcc'=Vcc / 2), the large capacitor C connected at the SVR node SVR , so the voltage Vsvr at the SVR node remains at Vcc / 4, and the non-inverting input and inverting input of buffer amplifier B2 also remain at Vcc / 4. At this time, due to the drop in the power supply voltage, internal circuitry (not shown) triggers buffer B1 to switch from a 2x voltage gain amplifier to a unity gain amplifier, resulting in an output voltage approximately equal to Vsvr, or Vcc / 4. In this case, the voltage across resistor R7 is zero, and no current flows through resistors R7 and R8. As a result, the output terminal Vob of buffer amplifier B2 rises to Vcc / 4. Correspondingly, the voltage across Rb1 is also zero, and no current flows through Rb1, resulting in the DC output of the first amplifier AMP+ of amplifier pair N2 also being Vcc / 4 = Vcc' / 2. That is, the current output bias voltage of OUTP remains half of the current power supply voltage Vcc'. Similarly, the current output bias voltage of OUTM is also half of the current power supply voltage Vcc'. Therefore, the DC output of the output bias voltage of the amplifier pair N2 or the entire power amplifier circuit decreases in proportion to the decrease in the power supply voltage Vcc, thereby ensuring the correct operation of the entire power amplifier circuit.

[0038] Figure 4 The following is a simulation result illustrating the operating performance of an example of a power amplifier circuit according to an embodiment of the present invention. In this simulation, the normal power supply voltage Vcc is set to 12V and drops to 6V when the car engine is restarted. Figure 4 As can be seen from the figure, when the power supply voltage jumps from 12V to 6V (such as Figure 4 The bias voltage of the power amplifier circuit is adjusted from 6V to 3V (as shown in (a) in FIG). Figure 4 During this process, the clamping voltage Vsvr is as follows: Figure 4 As shown in (b), it remains at around 3V, and the AC gains of the two amplifiers in the power amplifier circuit are equal (as shown in Figure 4 As shown in (c) in the figure), the total AC output of the amplifier circuit is as follows: Figure 4 In addition, some key parameters of the performance evaluation of the power amplifier circuit proposed in the embodiment of the present invention, such as THD (total harmonic distortion), noise, and "pop" noise, are consistent with Figure 1 The conventional circuit shown is almost identical.

[0039] One advantage of a power amplifier circuit according to an embodiment of the present invention is that it eliminates the use of a common-mode feedback circuit. By adjusting the voltages of the bias resistor and the feedback resistor, identical feedback can be achieved for both OUTP and OUTM. Due to the elimination of the common-mode feedback circuit, the positive feedback loop no longer exists, thus preventing oscillation even when a large capacitive load is connected, thereby making the car audio system more stable.

[0040] Another advantage of the power amplifier circuit according to the embodiment of the present invention is that Figure 1 In the conventional circuit shown, AMP+ and AMP- have a 20-fold DC gain for the output of the common-mode feedback, so the mismatch of the feedback resistors Re1, Rf1, Re2, and Rf2 themselves will also be amplified by 20 times, resulting in a large offset; while the power amplifier circuit according to the embodiment of the present invention has only a 2-fold DC gain from the output Vob of the buffer B2 through the bias resistor Rb1 and the feedback resistor Rf1 or through Rb2 and Rf2 to the output of the power amplifier circuit, so that the mismatch of the resistors Rb1 and Rf1 or Rb2 and Rf2 themselves is amplified significantly less, which makes the DC offset ratio Figure 1 The conventional circuit shown is significantly reduced. The quiescent current of the power amplifier circuit is also reduced by about 4%.

[0041] Figure 5 is a flow chart illustrating a method for adjusting the bias voltage of a power amplifier circuit according to an embodiment of the present invention. Figure 3 The structure shown in FIG. 1 includes a clamp circuit N1, a bias circuit N3 and an amplifier pair N2. Figure 5 As shown in FIG, in block 501, a clamp voltage Vsvr obtained by dividing the power supply voltage is provided by clamp circuit N1. In block 502, the input bias voltage of amplifier pair N2 is adjusted by bias circuit N3 according to changes in the power supply voltage, so that the output of the amplifier pair changes proportionally with the change in the power supply voltage. In block 503, the amplified signal is output by amplifier pair N2.

[0042] The above description in conjunction with the accompanying drawings is only given as an example to illustrate the present invention. Those skilled in the art should understand that different method steps or device structures can be proposed based on the principles of the present invention described above. Although these different method steps or device structures are not explicitly described or shown here, they all embody the principles of the present invention and are included in the spirit and scope of the present invention. In addition, all the examples mentioned herein are mainly used for teaching purposes to help readers understand the principles of the present invention and the ideas contributed by the inventors to promote the development of technology in this field, and should not be interpreted as limiting the scope of the invention. In addition, all statements of the principles, aspects and embodiments of the present invention mentioned herein and their specific examples include their equivalents.

Claims

1. A power amplifier, comprising: a clamp circuit configured to provide a clamp voltage from a power supply at a power supply voltage suppression node; a bias circuit comprising a buffer circuit having a first input coupled to receive a first voltage derived from the clamp voltage and a second input coupled to receive a second voltage derived from the clamp voltage, the buffer circuit having an output that generates a bias voltage; as well as an amplifier pair having a first plurality of inputs coupled to the clamping voltage at the clamping circuit, an output for providing an amplified signal, and a second plurality of inputs; as well as wherein a bias voltage generated at the output of the buffer circuit is coupled to a second plurality of inputs of the amplifier pair to adjust the input bias voltage of the amplifier pair so that the output of the amplifier pair changes proportionally with changes in the voltage of the power supply; wherein the clamping circuit comprises two or more voltage-dividing resistors for dividing the voltage of the power supply; The voltage divided by the voltage-dividing resistor is coupled to a power supply voltage suppression node, the power supply voltage suppression node is further coupled to the first plurality of inputs of the amplifier pair through a first plurality of bias resistors, and the power supply voltage suppression node is coupled to ground through a capacitor, thereby providing the clamping voltage at the power supply voltage suppression node.

2. The power amplifier of claim 1 , wherein the bias circuit comprises: a first buffer circuit having an input coupled to the power supply voltage suppression node, the first buffer circuit being configured to operate with a variable gain, The variable gain includes a switching gain, and the switching gain includes a unity gain setting and a non-unity gain setting.

3. The power amplifier according to claim 1, wherein: The bias circuit further includes a first buffer and a second buffer, wherein each buffer has at least one input and one output, An input of the first buffer is coupled to the power supply voltage suppression node; an output of the first buffer coupled to a first input of the second buffer via a first resistor; the supply voltage suppression node is coupled to a second input of the second buffer; a second resistor coupled between the output of the second buffer and the first input; and Outputs of the second buffer are respectively coupled to the second plurality of inputs of the amplifier pair via a second plurality of bias resistors. 4 . The power amplifier of claim 3 , wherein the first buffer is configured to amplify the clamp voltage when the power supply remains unchanged, and output the clamp voltage as it is when the power supply drops. 5 . The power amplifier of claim 3 , wherein a third buffer is coupled between the power supply voltage suppression node and the second input of the second buffer.

6. The power amplifier according to claim 1, further comprising: a plurality of bias point registers configured to apply the bias voltages to the first plurality of inputs of the amplifier pair, respectively; as well as A capacitor is coupled between the power supply voltage suppression node and ground.

7. The power amplifier of claim 1, wherein the bias circuit further comprises a first buffer having an input coupled to the power supply voltage suppression node and an output coupled to the first input of the buffer circuit. 8 . The power amplifier of claim 7 , wherein the first buffer is configured to amplify the clamp voltage at a first power supply level and is further configured not to amplify the clamp voltage at a second power supply level lower than the first power supply level.

9. The power amplifier of claim 8, wherein the bias circuit further comprises a second buffer coupled between the power supply voltage suppression node and a second input of the buffer circuit. 10 . The power amplifier of claim 1 , further comprising a plurality of bias resistors configured to apply the bias voltages to the second plurality of inputs of an amplifier pair, respectively.

11. The power amplifier according to any one of claims 1-10, wherein the amplifier pair is configured as a Class AB amplifier.

12. A circuit comprising: An audio amplifier having an audio signal input and a bias signal input; as well as a bias circuit having an output coupled to a bias signal input of the audio amplifier; The bias circuit comprises: a clamp circuit configured to generate a first voltage from a power supply voltage at a power supply voltage suppression node; a first buffer circuit having an input coupled to the power supply voltage suppression node, the first buffer circuit configured to operate with a variable gain to generate a second voltage from the first voltage; and an amplifier circuit having a first input coupled to receive the first voltage and a second input configured to receive the second voltage, wherein an output of the amplifier circuit generates a bias signal for application to the bias signal input, wherein the clamping circuit comprises two or more voltage dividing resistors, The power supply voltage divided by the voltage-dividing resistor is coupled to the power supply voltage suppression node, the power supply voltage suppression node is further coupled to the first input of the amplifier circuit through a bias resistor, and the power supply voltage suppression node is coupled to ground through a capacitor.

13. The circuit of claim 12, wherein the variable gain comprises a switched gain, the switched gain comprising a unity gain setting and a non-unity gain setting.

14. The circuit of claim 13, wherein the first buffer circuit operates at the unity gain setting when the supply voltage is at a first voltage level, and the first buffer circuit operates at the non-unity gain when the supply voltage is at a second voltage level. The circuit of claim 14 , wherein the first voltage level is less than the second voltage level.

16. The circuit of claim 12, further comprising a second buffer circuit coupled between the power supply voltage suppression node and the first input of the amplifier circuit.

17. The circuit according to any one of claims 12 to 16, further comprising: A capacitor is coupled between the power supply voltage suppression node and a reference power supply node.

18. A method for adjusting the bias voltage of a power amplifier according to claim 1, comprising: providing a clamping voltage from a power supply voltage through the clamping circuit; adjusting an input bias voltage of the amplifier pair by the bias circuit so that the output of the amplifier pair changes in proportion to a change in the power supply; as well as providing an amplified output via the amplifier pair; Wherein adjusting the input bias voltage comprises: comparing a first voltage derived from the clamp voltage and a second voltage derived from the bias voltage to generate a bias voltage; applying the clamp voltage to a plurality of first inputs of the amplifier pair; and The bias voltage is applied to a plurality of second inputs of the amplifier pair.

19. The method of claim 18, wherein adjusting the input bias voltage further comprises: When the power supply is at a first power supply voltage, amplifying the clamp voltage to generate the first voltage; as well as When the power supply is at a second power supply voltage that is less than the first power supply voltage, the clamp voltage is not amplified to generate the first voltage.

20. The method of claim 18 or 19, wherein the amplifier pair is configured as a Class AB amplifier.

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