Semiconductor Devices

Abstract

Embodiments of the present disclosure relate to a semiconductor device. A memory includes a first descriptor area and a first data area corresponding to a first OS, and a second descriptor area and a second data area corresponding to a second OS. A second processor stores first transmission instruction information corresponding to transmission data stored in the second data area in the second descriptor area, and sends a first update notification of the second descriptor area to the first processor. In response to the first update notification, the first processor reads the first transmission instruction information stored in the second descriptor area, and stores the first transmission instruction information in the first descriptor area. A communication circuit controlled by the first processor performs a transmission process of transmission data stored in the second data area based on the first transmission instruction information stored in the first descriptor area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2018-137376 filed on Jul. 23, 2018 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Background Art

[0003] The present invention relates to a semiconductor device and an information processing system, and for example, the present invention relates to a semiconductor device and an information processing system in which a communication circuit is shared by a plurality of OSs (Operating Systems).

[0004] In semiconductor devices such as microcomputers, direct memory access (DMA) transfer is used to accelerate data transfer between memories or between memories and I / O devices. In recent years, descriptor type DMA transfer that ensures a descriptor area for controlling DMA transfer in addition to a data storage area as a transfer target in a memory and performs DMA transfer has been widely circulated. For example, in Japanese Unexamined Patent Application Publication No. 2009-187313, a technology related to descriptor control in descriptor type DMA transfer is disclosed.

[0005] In Japanese Unexamined Patent Application Publication No. 2015-69352, a technology related to inter-OS communication between guest OS in virtualization is disclosed in order to integrate and control a plurality of storage systems. In Japanese Unexamined Patent Application Publication No. 2015-69352, guest OS corresponds to a corresponding storage system, and a shared memory and an interrupt according to an IPI (Inter-Processor Interrupt) method are used for inter-OS communication. Summary of the invention

[0006] Here, in a semiconductor device having a plurality of processors executing different OSs from each other, it is necessary to maintain security in order for the plurality of processors to share one communication circuit. Therefore, it is considered that the first processor controls the communication circuit by using the technology according to Japanese Unexamined Patent Application Publication No. 2009-187313 and Japanese Unexamined Patent Application Publication No. 2015-69352, and the remaining processors use the communication circuit through inter-OS communication with the first processor. However, the inventors have found that there is a new problem: the processing load of the processor may increase as the amount of data and the frequency of communication increase only by attempting to invent related technology (described later) while referring to the technology of Japanese Unexamined Patent Application Publication No. 2009-187313 and Japanese Unexamined Patent Application Publication No. 2015-69352.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0008] Means of solving the problem

[0009] According to one embodiment, a semiconductor device includes: a first processor and a second processor, which execute different OS; a memory; and a communication circuit, which is controlled by the first processor. Here, the memory includes a first descriptor area and a second descriptor area corresponding to the corresponding OS and a first data area and a second data area. The second processor notifies the first processor that the communication instruction information corresponding to the second data area is stored in the second descriptor area. In response to the notification, the first processor stores the communication instruction information stored in the second descriptor area in the first descriptor area, and instructs the communication circuit to send and receive data based on the communication instruction information.

[0010] According to the above-described embodiments, in a semiconductor device including a plurality of processors that execute OSs different from each other, when the plurality of processors share one communication circuit, the processors can reduce processing loads. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram showing a hardware configuration of a semiconductor device according to Embodiment 1.

[0012] Figure 2 is a functional block diagram showing the configuration of a semiconductor device according to Embodiment 1.

[0013] Figure 3 : is a sequence diagram showing the flow of the data transmission process according to Embodiment 1.

[0014] Figure 4 : is a sequence diagram showing the flow of the data transmission process according to Embodiment 1.

[0015] Figure 5 is a sequence diagram showing the flow of a data receiving process according to Embodiment 1.

[0016] Figure 6 is a sequence diagram showing the flow of a data receiving process according to Embodiment 1.

[0017] Figure 7 : is a sequence diagram showing the flow of the data transmission process (a large number of copies of multiple descriptors) according to Embodiment 1.

[0018] Figure 8 : is a sequence diagram showing the flow of the data transmission process (a large number of copies of multiple descriptors) according to Embodiment 1.

[0019] Fig. 9: is a sequence diagram showing the flow of the data transmission process (a large number of copies of multiple descriptors) according to Embodiment 1.

[0020] Fig.10 is a functional block diagram showing the configuration of a semiconductor device according to Embodiment 2.

[0021] Fig.11 is a block diagram showing the internal configuration of a communication circuit according to Embodiment 2.

[0022] Fig.12 : is a sequence diagram showing the flow of the data receiving process according to Embodiment 2.

[0023] Fig.13 : is a sequence diagram showing the flow of the data receiving process according to Embodiment 2.

[0024] Fig.14 is a flowchart illustrating the flow of a receiving process according to Embodiment 2.

[0025] Fig.15 is a diagram illustrating an exemplary descriptor composition when communication capacity is uniformly allocated to respective OSs according to the Round Robin method according to Embodiment 3.

[0026] Fig.16 : is a diagram showing an exemplary descriptor composition of a Token Bucket method when the maximum size of the cumulative size of descriptors per unit time is set for each OS according to Embodiment 3.

[0027] Fig.17 is a functional block diagram illustrating a configuration of a semiconductor device according to the related art. DETAILED DESCRIPTION

[0028] For the purpose of explanation, the following description and drawings are appropriately omitted and simplified. In addition, the various elements of the functional blocks for performing various processes described in the drawings can be configured by CPU (central processing unit), memory and other circuits in hardware, and can be implemented by programs loaded in the memory in software. Therefore, it should be understood by those skilled in the art that these functional blocks can be implemented in various forms by separate hardware, separate software or a combination thereof, and the present invention is not limited to any of them. In the drawings, the same elements are represented by the same reference numerals, and their repeated descriptions are omitted as required.

[0029] In addition, various types of non-transitory computer-readable media can be used to store the program described above and provide the program to the computer. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (e.g., floppy disks, magnetic tapes, hard disk drives), magneto-optical recording media (e.g., magneto-optical disks), CD-ROMs (read-only memory, CD-R, CD-R / W, solid-state memory (e.g., mask ROM, PROM (programmable ROM), EPROM (erasable PROM, flash ROM, RAM (random access memory)). The program can also be supplied to the computer via various types of transient computer-readable media. Examples of transient computer-readable media include electrical signals, optical signals, and electromagnetic waves. Transient computer-readable media can provide programs to the computer via wired or wireless communication paths such as wires and optical fibers.

[0030] Here, the problem to be solved by this embodiment will be described in detail. Fig.17 is a functional diagram showing a configuration of a semiconductor device 9 according to the prior art. The semiconductor device 9 includes processors 91 and 92, a memory 93, and a communication circuit 95. It is assumed that the semiconductor device 9 is also provided with an interrupt controller as a configuration not shown. The communication circuit 95 includes a DMA controller for performing DMA transfer between the memory 93 in the semiconductor device 9 and a circuit; and a circuit for performing Ethernet communication with an external network. The communication circuit 95 corresponds to the descriptor type DMA transfer described in Japanese Unexamined Patent Application Publication No. 2009-187313.

[0031] Each of the processors 91 and 92 is operated by an OS different from each other. For example, it is assumed that the processor 91 executes the first OS and the processor 92 executes the second OS. Herein, since the communication circuit 95 is one, the processors 91 and 92 must share the communication circuit 95 so that the first OS and the second OS communicate with the outside respectively. Therefore, for example, the inventors considered the following related technologies with reference to the technologies disclosed in the above-mentioned Japanese Unexamined Patent Application Publication No. 2009-187313 and Japanese Unexamined Patent Application Publication No. 2015-69352. The first OS executed by the processor 91 manages and directly controls the communication circuit 95 as a hardware resource of the first OS. The processor 92 indirectly controls the communication circuit 95 by performing inter-OS communication with the processor 91. That is, the processors 91 and 92 cooperate to control the communication circuit 95. The details are as follows.

[0032] First, a descriptor area 133, a data area 134, and a shared area 936 are set in the memory 93. The shared area 936 is an area shared by the processors 91 and 92, that is, an area accessible to both the processors 91 and 92. The shared area 936 stores the transmission data 232 when the second OS sends data to the outside, and the transmission instruction information 213, which is a descriptor for sending the transmission data 232 to the communication circuit 95. The data area 134 and the descriptor area 133 are areas that the processor 91 can access and areas that the processor 92 cannot access. The data area 134 stores the transmission data 231 when the first OS sends data to the outside. The descriptor area 133 stores a plurality of descriptors for performing descriptor control in the descriptor type DMA transfer. Here, the descriptor includes the transmission instruction information 211 and 212 in the communication circuit 95, which are used in the process of sending data to the outside.

[0033] Here, a description will be given of a flow when the second operating system operating in the processor 92 sends data to the outside of the semiconductor device 9 .

[0034] (1) First, the processor 92 stores the transmission data 232 and the transmission instruction information 213 to be transmitted in the shared area 936 through the data access 922. Next, the processor 92 notifies the processor 91 to transmit the transmission data 232 through the IPI interrupt 931. Incidentally, the IPI interrupt 931 and the IPI interrupt 932 (described later) are to be executed by the IPI method via the interrupt controller described above.

[0035] (2) In response to the notification by the IPI interrupt 931, the processor 91 reads the transmission data 232 and the transmission instruction information 213 from the shared area 936 through the data access 913. Then, the processor 91 stores (i.e., copies) the read transmission data 232 in the data area 134 as the transmission data 231 through the data access 912. The processor 91 stores (i.e., copies) the read transmission instruction information 213 in the descriptor area 133 as the transmission instruction information 211 through the data access 911. Here, the transmission instruction information 211 is a descriptor for causing the communication circuit 95 to transmit the transmission data 231 to the outside. Thereafter, the processor 91 notifies the communication circuit 95 of the transmission instruction through the data access 914.

[0036] (3) In response to the transmission instruction from the processor 91, the communication circuit 95 reads the transmission instruction information 211 from the descriptor area 133 through the data access 941. Then, the communication circuit 95 reads the transmission data 231 from the data area 134 through the data access 942 based on the read transmission instruction information 211, and transmits the transmission data 231 to the outside through the data output 345. Thereafter, the communication circuit 95 records (adds) the transmission completion information in the transmission instruction information 211 in the descriptor area 133 through the data access 941. Then, the communication circuit 95 notifies the processor 91 of the completion through the completion interrupt 943. The completion interrupt 943 is executed via the interrupt controller described above.

[0037] (4) In response to the completion notification by the completion interrupt 943, the processor 91 reads the transmission instruction information 211 from the descriptor area 133 through the data access 911, and stores the transmission instruction information 211 in the shared area 936 through the data access 913, that is, updates or copies the transmission instruction information 213. Then, the processor 91 notifies the processor 92 of the completion of the transmission of the transmission data 232 through the IPI interrupt 932.

[0038] (5) In response to the notification of the completion of the transmission by the IPI interrupt 932, the processor 92 refers to the transmission instruction information 213 in the shared area 936 through the data access 922, and confirms the transmission result (transmission completion information).

[0039] As described above, in the case of the prior art described above, the copy process of the communication data (transmission data) between the processor 91 shared area 936 and the data area 134 occurs. For example, in the case of full-duplex Gigabit Ethernet, since the transmission and reception become 1Gbps, the data copy process of 1Gbps is loaded only by transmission. Since IPI interruption occurs in each Ethernet communication, the processing load is generated by the interrupt response process. For example, if the minimum frame size of a communication by Gigabit Ethernet is 64 bytes, 1488000 IPI interruptions occur per second. Therefore, the problem that the processing load of the processor may be high may occur. In view of the above, the embodiments for solving these problems are described below.

[0040] Example 1

[0041] The semiconductor device according to the first embodiment includes: a first processor and a second processor, which execute different operating systems from each other; a memory; and a communication circuit, which is controlled by the first processor. Here, the memory includes a first descriptor area and a first data area, which are working areas of the first OS executed by the first processor; and a second descriptor area and a second data area, which are working areas of the second OS executed by the second OS. The second processor stores the first transmission instruction information corresponding to the transmission data stored in the second data area in the second descriptor area, and sends the first update notification of the second descriptor area to the first processor. In response to the first update notification, the first processor reads the first transmission instruction information stored in the second descriptor area, and stores the first transmission instruction information in the first descriptor area. The communication circuit performs the transmission process of the transmission data stored in the second data area based on the first transmission instruction information stored in the first descriptor area. As a result, the copying process of the communication data between the data areas by the processor can be reduced, and the processing load of the processor can be reduced. In addition, a part of the communication processing in the first processor and the second processor can be made common, and the development efficiency can be improved.

[0042] Further, preferably, the first processor reads the sending completion information of the sending data stored in the first descriptor area by the communication circuit in response to the completion notification of the sending process from the communication circuit, stores the sending completion information in the second descriptor area, and sends the second update notification of the second descriptor area to the second processor. In this case, the second processor refers to the sending completion information stored in the second descriptor area in response to the second update notification. This allows the second processor to call the same sending confirmation process as the first processor, thereby further improving development efficiency.

[0043] Alternatively, the second processor may store the first receiving instruction information for storing the received data in the second data area in the second descriptor area, and send the third update notification of the second descriptor area to the first processor. In this case, in response to the third update notification, the first processor reads the first declaration instruction information stored in the second descriptor area, and stores the first receiving instruction information in the first descriptor area. Thereafter, the first processor responds to the completion notification of the receiving process of the received data from the communication circuit, reads out the received data stored in the first data area by the communication circuit, and determines the destination of the received data. When it is determined that the destination is the second OS or the second processor, the first processor stores the received data in the second data area, and reads the receiving completion information corresponding to the received data stored in the first descriptor area by the communication circuit from the first descriptor area, and stores the information in the second descriptor area. As described above, in the receiving process, similar to the sending process, the descriptor is transmitted and a part of the communication processing can be shared, and the development efficiency is improved.

[0044] Each of the first OS and the second OS may be a virtual OS. That is, the present embodiment is applicable to the virtual OS. Further, the second data area and the second descriptor area are shared areas that can be accessed by data from each of the first processor on which the first OS operates and the second processor on which the second OS operates.

[0045] Figure 1 1 is a block diagram showing a hardware configuration of a semiconductor device 1 according to a first embodiment. The semiconductor device 1 is, for example, an information processing device such as a microcontroller, an embedded system, or a computer. The semiconductor device 1 is connected to a communication network N and can communicate with the outside. The semiconductor device 1 includes processors 11 and 12, a memory 13, an interrupt controller 14, and a communication circuit 15. The processors 11 and 12, the memory 13, the interrupt controller 14, and the communication circuit 15 are connected via a data bus 16. The processors 11 and 12, the interrupt controller 14, and the communication circuit 15 are connected via an interrupt signal line 17. Since the remaining configuration of the semiconductor device 1 is well known, its description and explanation are omitted.

[0046] The memory 13 is a volatile storage device such as a random access memory (RAM). The memory 13 stores an OS 131 and an OS 132. Here, the OS 131 is a first exemplary operating system, and includes a function of controlling the communication circuit 15. Further, it is assumed that the security of the OS 131 is equal to or higher than the security of the OS 132. The OS 132 is an example of a second OS, and in the present embodiment, the communication circuit 15 is not directly controlled. That is, the OS 132 communicates with the communication circuit 15 via the OS 131. It is assumed that the OS 131 and 132 have an inter-OS communication function by means of a shared memory, and interrupts are performed via the interrupt controller 14 according to the IPI system. Either or both of the OS 131 and 132 may be a virtual OS.

[0047] Each of the processors 11 and 12 is a control device such as a CPU or a microprocessor unit. The processor 11 has a memory management unit 111. Since other physical configurations of the processor 11 are well known, illustration and detailed description thereof are omitted. The MMU 111 converts a virtual address recognized by the processor 11 and a physical address on the memory 13. The MMU 111 has a common memory protection function, a cache control function, a bus arbitration function, etc. The processor 11 communicates with the processor 12, the memory 13, the interrupt controller 14, the communication circuit 15, etc. via the data bus 16. The processor 11 sends an interrupt request to the interrupt controller 14 via the interrupt signal line 17, and receives an interrupt notification from the interrupt controller 14.

[0048] The processor 11 is an example of a first processor, and the first processor reads and executes the OS 131 stored in an external or internal storage device (not shown). Therefore, the processor 11 directly controls the communication circuit 15.

[0049] The processor 12 has an MMU 121. The function of the MMU 121 is the same as that of the MMU 111 described above. Since other physical configurations of the processor 12 are well known, illustration and detailed description thereof are omitted. The processor 12 communicates with the processor 11, the memory 13, the interrupt controller 14, the communication circuit 15, etc. via the data bus 16. The processor 12 sends an interrupt request to the interrupt controller 14 via the interrupt signal line 17, and receives an interrupt notification from the interrupt controller 14.

[0050] The processor 12 is an exemplary second processor, and reads an OS 132 stored in another external or internal storage device into the memory 13, and executes the OS 132. Thus, the processor 12 controls the communication circuit 15 via the processor 11.

[0051] The interrupt controller 14 receives interrupt requests from the processors 11 and 12 and the communication circuit 15 via the interrupt signal line 17, and sends interrupt notifications to the processors 11 and 12 and the communication circuit 15. Specifically, the interrupt controller 14 supports inter-OS communication through the IPI system.

[0052] The communication circuit 15 includes a DMA controller for performing DMA transfer between the memory 13 and the outside of the semiconductor device 1 and a circuit for performing Ethernet communication with the communication network N. The communication circuit 15 corresponds to descriptor type DMA transfer as described in Japanese Unexamined Patent Application Publication No. 2009-187313.

[0053] The communication network N is a network formed by wired or wireless communication lines.

[0054] Figure 2 is a functional diagram showing the configuration of the semiconductor device 1 according to the present embodiment 1. Figure 1 The same components are indicated by the same reference numerals. Figure 2 In FIG. 1 , the interrupt controller 14 and the OS 131 and 132 and other data in the memory 13 are omitted. The memory 13 includes a descriptor area 133, a data area 134, a descriptor area 135, and a data area 136.

[0055] The descriptor area 133 and the data area 134 are work areas of the OS 131 executed by the processor 11. That is, the descriptor area 133 and the data area 134 are structures on the virtual space of the processor 11. It is assumed that the descriptor area 133 and the data area 134 do not accept access from the processor 12. The descriptor area 133 is an exemplary first descriptor area, and is a storage area for storing one or more descriptors for causing the communication circuit 15 to send data to the outside and receive data from the outside through the OS 131. The descriptor includes a transmission instruction information used when sending and a reception instruction information used when receiving. The descriptor area 133 can store a plurality of transmission instruction information 211, 212, ... and a plurality of reception instruction information 221, 222, ... The descriptor area 133 can independently manage the transmission instruction information and the reception instruction information. Here, the transmission instruction information 211 and the like include, for example, a physical address (e.g., a start address) on the memory 13 in which the transmission data is stored, the size of the transmission data, a status area for recording the DMA transfer completion status (transmission completion information), and the like. The reception instruction information 222 and the like include, for example, a physical address (e.g., a start address) on the memory 13 for storing the reception data therein, the size of the reception data, a status area for recording the DMA transfer completion status (reception completion information), etc. As the format of the descriptor, for example, a known format described in Japanese Unexamined Patent Application Publication No. 2009-187313 and the like can be used. In addition, the descriptor area 133 can hold descriptors for the OS 131 and descriptors for the OS 132 in a mixed manner.

[0056] The data area 134 is an exemplary first data area, and is a storage area for storing transmission data 231 and reception data 241, which are objects of data transmission / reception processes between the OS 131 and the outside. In the present embodiment, the reception data 241 may be data received from the outside toward the OS 132. The data area 134 may store two or more pieces of transmission data and two or more pieces of reception data.

[0057] The descriptor area 135 and the data area 136 are work areas of the OS 132 executed by the processor 12. That is, the descriptor area 135 and the data area 136 are structures on the virtual space of the processor 12. However, it is assumed that the descriptor area 135 and the data area 136 can also be accessed from the processor 11. That is, the descriptor area 135 and the data area 136 are shared areas 130 that can be accessed by the processor 11 on which the OS 131 operates and the processor 12 on which the OS 132 operates. The descriptor area 135 is an exemplary second descriptor area, and is a storage area for storing one or more descriptors for causing the communication circuit 15 to transmit data to the outside of the OS 132 and receive data from the outside. The descriptor area 135 can store one or more transmission instruction information 213 and one or more reception instruction information 223. The descriptor area 135 can independently manage the transmission instruction information and the reception instruction information. The addresses included in the transmission instruction information 213 and the reception instruction information 223 are addresses in the data area 136 managed by the OS 132 .

[0058] The data area 136 is an exemplary second data area, and is a storage area for storing the transmission data 232 and the reception data 242, which are the objects of the data transmission / reception process between the OS 132 and the outside. The data area 136 can store two or more pieces of transmission data and two or more pieces of reception data.

[0059] The processor 11 reads data from and writes data to the descriptor area 133, the data area 134, the descriptor area 135, and the data area 136 through data accesses 311, 312, 313, and 315, respectively. In addition, the processor 11 sends a notification to and receives a notification from the communication circuit 15 through the data access 314. The processor 11 receives a completion notification from the communication circuit 15 through a completion interrupt 343. The processor 11 performs inter-OS communication with the processor 12 via the interrupt controller 14 through IPI interrupts 331 and 332.

[0060] The processor 12 reads data from and writes data to the descriptor area 135 and the data area 136 through data accesses 321 and 322, respectively. When sending and receiving data via the communication circuit 15, the processor 12 notifies the processor 11 of sending instructions or receiving instructions through the IPI interrupt 331. When the processor 12's own data is received through the communication circuit 15, the processor 12 also receives notification from the processor 11 through the IPI interrupt 332.

[0061] The communication circuit 15 reads data from and writes data to the descriptor area 133, the data area 134, and the data area 136, respectively, through the data accesses 341, 342, and 344. When receiving a transmission instruction from the processor 11 through the data access 314, the communication circuit 15 refers to the transmission instruction information 211 in the descriptor area 133, and performs a transmission process of transmitting the data 231 or 232 through the data output 345. When receiving a reception instruction from the processor 11 through the data access 314, the communication circuit 15 refers to the reception instruction information 221 in the descriptor area 133, and performs a reception process of receiving the data 241 through the data input 346.

[0062] Figure 3 and Figure 4 1 is a sequence diagram showing the flow of the data transmission process performed by the present embodiment 1. First, the processor 12 creates the transmission data 232 to be sent to the communication network N via the communication circuit 15, and stores the transmission data 232 in the data area 136 through the data access 322 (S101). Next, the processor 12 generates the transmission instruction data 213 as a descriptor for sending the transmission data 232 to the communication circuit 15 (S102). Then, the processor 12 stores the transmission instruction information 213 in the descriptor area 135 through the data access 321 (S103). Thereafter, the processor 12 notifies the processor 11 of the update of the descriptor area 135 through the IPI interrupt 331. Specifically, the processor 12 sends an update notification to the interrupt controller 14 via the interrupt signal line 17 (S104). In response to the update notification from the processor 12, the interrupt controller 14 outputs an interrupt signal to the processor 11 via the interrupt signal line 17 (S105).

[0063] Then, the processor 11 responds to the update notification by the IPI interrupt 331 (interrupt signal from the interrupt controller 14, the same below) and reads the transmission instruction information 213 from the descriptor area 135 through the data access 313. Then, the processor 11 stores the read transmission instruction information 213 in the descriptor area 133 as the transmission instruction information 211 through the data access 311 (i.e., S106). Thereafter, the processor 11 notifies the communication circuit 15 of the transmission instruction through the data access 314 (S107).

[0064] In response to the transmission instruction from the processor 11, the communication circuit 15 reads the transmission instruction information 211 from the descriptor area 133 through the data access 341. Since the read transmission instruction information 211 indicates the transmission data 232 in the data area 136, the communication circuit 15 reads the transmission data 232 from the data area 136 through the data access 344, and transmits the transmission data 232 to the communication network N through the data output 345 transmitted by DMA (S108). Thereafter, the communication circuit 15 records (adds) the transmission completion information in the transmission instruction information 211 as a result of the DMA process in the descriptor area 133 through the data access circuit 341 (S109). Then, the communication circuit 15 notifies the processor 11 of the completion through the completion interrupt 343. Specifically, the communication circuit 15 sends a completion notification to the interrupt controller 14 via the interrupt signal line 17 (S110). In response to the completion notification from the communication circuit 15, the interrupt controller 14 outputs an interrupt signal to the processor 11 via the interrupt signal line 17 (S111).

[0065] In response to the completion notification through the completion interrupt 343, the processor 11 reads the transmission instruction information 211 (transmission completion information) from the descriptor area 133 through the data access 311, and stores the transmission instruction information 211 in the descriptor area 135 through the data access 313, that is, updates or copies the transmission instruction information 213 (transmission completion information) (S112). Then, the processor 11 sends the update notification of the descriptor area 135 to the processor 12 through the IPI interrupt 332. Specifically, the processor 11 sends the update notification to the interrupt controller 14 via the interrupt signal line 17 (S113). In response to the update notification from the processor 11, the interrupt controller 14 outputs an interrupt signal to the processor 12 via the interrupt signal line 17 (S114).

[0066] Then, in response to the update notification of the IPI interrupt 332, the processor 12 reads the transmission instruction information 213 in the descriptor area 135 through the data access 321, and refers to the transmission result (transmission completion information) (S115).

[0067] As described above, by changing only a part of the transmission process to the communication network N in the OS 131 that directly controls the communication circuit 15, most of the transmission process to the communication network N in the OS 132 can be shared. That is, the transmission process to the communication network N in the OS 132 is replaced by a process of sending an update notification of the descriptor area 135 to the processor 11 through the IPI interrupt 331, rather than a transmission instruction to the communication network 15. In addition, the process of sending data to the communication network N in the OS 132 is replaced by a process of receiving a notification of updating the descriptor area 135 from the processor 11 through the IPI interrupt 332, rather than a process of receiving a completion notification from the communication circuit 15. No other process changes are required.

[0068] Figure 5 and Figure 6 1 is a sequence diagram showing the flow of the data receiving process performed by the present embodiment 1. First, the processor 12 generates the receiving instruction data 223 as a descriptor for causing the communication circuit 15 to receive data transmitted from the communication network N (S201). Then, the processor 12 stores the receiving instruction data 223 in the descriptor area 135 through the data access 321 (S202). Thereafter, the processor 12 notifies the processor 11 of the update of the descriptor area 135 through the IPI interrupt 331 (S203 and S204). The specific process is the same as the above-mentioned steps S104 and S105.

[0069] In response to the update notification by the IPI interrupt 331, the processor 11 reads the reception instruction information 223 from the descriptor area 135 through the data access 313. Then, the processor 11 stores (i.e., S205) the read reception instruction information 223 in the descriptor area 133 as the reception instruction information 221 through the data access. However, since the address included in the reception instruction information 223 is an address in the data area 136, when storing the reception instruction information 221, the processor 11 may change the address to an address in the data area 134. Thereafter, the processor 11 notifies the communication circuit 15 of the reception instruction indicating that the reception of the Ethernet packet is completed through the data access 314 (S206).

[0070] In response to the reception instruction from the processor 11, the communication circuit 15 refers to the reception instruction information 221 in the descriptor area 133 through the data access 341, and receives data from the communication network N through the data input 346. After receiving the data, the communication circuit 15 stores the reception data 241 in the data area 134 by the data access unit 342 based on the reception instruction data 221 (S207). Then, the communication circuit 15 records (adds) the reception completion information as a result of the DMA process in the reception instruction information 221 in the descriptor area 133 through the data access circuit 341 (S208). Then, the communication circuit 15 notifies the processor 11 of the completion notification through the completion interrupt 343 (S209 and S210).

[0071] In response to the completion notification by the completion interrupt 343, the processor 11 reads data from the received data 241 in the data area 134 through the data access 342, and if the received data 241 is data for the OS 132 or the processor 12, the processor 11 stores (i.e., copies (S211)) the data in the data area 136 as the received data 242 through the data access 315. In Ethernet communication, the destination of the communication data is determined by the destination address included in the header of the frame data as the received data. Then, the processor 11 reads the received instruction information corresponding to the copied data from the received instruction information 221 in the descriptor area 133 through the data access 311, and stores (i.e., copies (S212)) the received instruction information in the descriptor area 135 as the received instruction information 223 through the data access 313. However, since the address included in the received instruction information 221 is an address in the data area 134, when storing the received instruction information 223, the processor 11 can change the address to the address in the data area 135. Then, the processor 11 sends an update notification of the descriptor area 135 to the processor 12 in response to the IPI interrupt 332 ( S213 and S214 ).

[0072] Then, in response to the update notification by the IPI interrupt 332, the processor 12 reads the reception instruction information 223 in the descriptor area 135 through the data access 321, and refers to the reception result (reception completion information) (S215). Then, the processor 12 acquires the reception data 242 from the data area 136 through the data access 322, and executes S216 as appropriate.

[0073] As described above, by only changing a part of the reception process of the communication network N in the OS 131 that directly controls the communication circuit 15, most of the reception process of the communication network N in the OS 132 can be shared. That is, the reception process of the communication network N in the OS 132 is replaced by a transmission process of an update notification to the descriptor area 135 of the processor 11 through the IPI interrupt 331, rather than a transmission instruction to the communication network 15. Further, the reception process to the communication network N in the OS 132 is replaced by a reception process of an update notification from the descriptor area 135 of the processor 11 through the IPI interrupt 332, rather than a reception process of a completion notification from the communication circuit 15. No other process changes are required.

[0074] In the related art described above, the processor 91 copies the send data 232 in the virtual space (shared area 936) of the processor 92 to its own virtual space (data area 134) through inter-OS communication. However, in the present embodiment, the copying process of the send data associated with inter-OS communication can be reduced. If the effect is minimal, that is, even if the size of the send data is minimal, the effect can be obtained. That is, even when the minimum frame size of the send data is 64 bytes and the descriptor size is 8 bytes, the copying process of the send data can be reduced to 8 / (64+8)*100=11.1%. In addition, the data can be sent while the send data 232 remains in the data area 136 of another space not managed by the OS 131.

[0075] In addition, in the prior art, it is necessary to implement processing that is significantly the same as the communication processing on the processor 91 side and the communication processing on the processor 92 side. However, in the present embodiment, as described above, since the descriptor structure is also used on the processor 12 side, it can be implemented by processing that is largely common to the processing on the processor 11 side. Therefore, development efficiency is improved.

[0076] Further, in the present embodiment, the processor 11 can improve security by checking whether the address indicated by the descriptor indicates an address in the data area 136 when copying the descriptor such as step S106 or S205 .

[0077] Another embodiment of embodiment 1

[0078] Here, another embodiment of the present embodiment is described. In another embodiment, a plurality of descriptors are copied together. That is, preferably, the second processor stores two or more first transmission instruction information corresponding to each transmission data in two or more transmission data stored in the second data area in the second descriptor area, and when two or more first transmission instruction information are stored in the second descriptor area, sends the first update notification. In this case, in response to the first update notification, the first processor stores each first transmission instruction information in the first descriptor area according to the storage order of two or more first transmission instruction information stored in the second descriptor area. Then, the communication circuit performs the transmission process of the transmission data corresponding to each first transmission instruction information stored in the second data area according to the storage order of two or more first transmission instruction information stored in the first descriptor area. In this way, two or more communication instruction information can be collected to reduce the frequency of IPI communication, and the processing load of the processor can be further reduced.

[0079] Figure 7 , Figure 8 and Fig. 9 1 is a sequence diagram showing the flow of the data transmission process (common copying of a plurality of descriptors) according to the present embodiment 1. The same applies to the data reception process, and the same effect can be obtained, so the illustration and detailed description are omitted.

[0080] First, the processor 12 creates the first transmission data 232a to be sent to the communication network N via the communication circuit 15, and stores the transmission data 232a in the data area 136 through the data access 322 in the same manner as in step S101 (S101a). Next, the processor 12 generates the transmission instruction data 213a as a descriptor for sending the transmission data 232a to the communication circuit 15 in the same manner as in step S102 (S102a). Then, the processor 12 stores the transmission instruction information 213a in the descriptor area 135 through the data access 321 in the same manner as in step S103 (S103a). Thereafter, the second case (transmission data 232b, transmission instruction information 213b) and subsequent cases are similarly executed until the nth case (transmission data 232n, transmission instruction information 213n) (S101n, S102n and S103n). That is, at this time, n pieces of transmission data are stored in the data area 136 , and n pieces of transmission instruction information are stored in the descriptor area 135 in the order of a to n.

[0081] Subsequently, the processor 12 notifies the processor 11 of the update of the descriptor area 135 through the IPI interrupt 331 (S104 and S105). In response to the update notification by the IPI interrupt 331, the processor 11 reads the n pieces of transmission instruction information 213a to 213n from the descriptor area 135 through the data access 313. Then, the processor 11 stores (i.e., copies (S106x)) the read n pieces of transmission instruction information 213a to 213n in the descriptor area 133 as n pieces of transmission instruction information 211a to 211n according to the storage order in the descriptor area 135 through the data access 311. Thereafter, the processor 11 notifies the communication circuit 15 of the transmission instruction through the data access 314 (S107).

[0082] In response to the transmission instruction from the processor 11, the communication circuit 15 transmits the transmission data in the data area 136 according to the order of the n transmission instruction information 211a to 211n in the storage descriptor area 133. More specifically, the communication circuit 15 reads out the transmission data 232a stored in the first data area 136 through the data access 344 based on the transmission instruction information 211a in the first data area stored in the descriptor area 133. Then, the communication circuit 15 transmits the read transmission data 232 to the communication network N through the data output circuit 345 (S108a). Thereafter, the communication circuit 15 records the transmission completion information a in the transmission instruction information 211a in the descriptor area 133 (S109a), and notifies the processor 11 of the completion through the completion interrupt 343 (S110a and S111a). Likewise, the second case and subsequent cases are executed until the nth case (sending data 232n, sending instruction data 211n) (S108n, S109n, S110n and S111n).

[0083] In response to the nth completion notification by the completion interrupt 343, the processor 11 reads the n pieces of transmission instruction information 211a to 211n (transmission completion information 211a to 211n) from the descriptor area 133 through the data access 311, and stores them in the descriptor area 135 through the data access 313 (S112x). Then, in response to the IPI interrupt 332, the processor 11 transmits an update notification of the descriptor area 135 to the processor 12 (S113 and S114).

[0084] Then, in response to the update notification of the IPI interrupt 332, the processor 12 reads out the n pieces of transmission instruction information 213a to 213n in the descriptor area 135 through the data access 321, and refers to the n pieces of transmission results (transmission completion information a to n) (S115x).

[0085] In the prior art described above, for each Ethernet frame, a set of inter-OS communication of IPI interrupts 931 and 932 occurs. For example, when there is a request to send three Ethernet frames, three IPIs are exchanged, that is, a total of six IPIs are generated. On the other hand, in other embodiments of the present embodiment described above, when there are three requests to send three Ethernet frames, three descriptors are copied at a time, so that the inter-OS communication can be reduced to two IPI interrupts 331 and 332. If one communication is the minimum frame size of 64 bytes in Gigabit Ethernet, 1488000 communications occur per second. If the response processing of an interrupt only requires a processing time of 1us (microseconds), the prior art requires a processing time of 1488000*2*1us=2.976s. However, since the processing time exceeds 1 second, the processing cannot catch up. On the other hand, in other embodiments of the present embodiment described above, the processing time can be reduced to a processing time of 2.976s / 3=0.992s, and the processing can be performed. Incidentally, three Ethernet frames are grouped together as an example, and the processing time can be further reduced by increasing the number of descriptors to be copied at a time.

[0086] Example 2

[0087] Embodiment 2 is another embodiment of embodiment 1 or an improvement of embodiment 1. In the first embodiment, the processor 11 copies the received data addressed to the processor 12 from the data area 134 to the data area 136, and there is room for reducing the processing load of the processor. In Ethernet communication, the destination of the communication data is determined by the destination address included in the header of the frame data. The frame data needs to be analyzed. However, although the processor can analyze the header of the frame data after storing it in the memory, during DMA transmission, the processor cannot determine and allocate the data area of ​​the storage destination before storage. Therefore, in order to distribute the data area of ​​the storage destination of the received data from the communication network N according to the destination, it is conceivable that the communication circuit determines the destination when receiving the data.

[0088] Therefore, the semiconductor device according to the second embodiment is improved to the first embodiment, and the communication circuit stores the received data in the second data area, stores the reception completion information in the first descriptor area, and sends a completion notification of the reception process to the first processor when the destination of the received data indicates the second operating system. As a result, the copy processing of the received data can be reduced, and the processing load of the processor can be further reduced.

[0089] Further, preferably, the first descriptor area includes a first sub-area corresponding to the first data area and a second sub-area corresponding to the second data area. In this case, the first processor stores the first received instruction information in the second sub-area in response to the third update notification. The communication circuit can retain the first communication address information corresponding to the first OS and the second communication address information corresponding to the second OS, determine whether each of the first communication address information and the second communication address information is included in the destination of the received data, and when it is determined that the second communication address information is included in the destination, store the received data in the second data area. In this way, by dividing the first descriptor area into two sub-areas and managing the instruction information separately, the storage destination can be specified according to the address information for each OS, and multicast can be handled.

[0090] Further, the communication circuit may include a first classifier accessible to the first data area and the first sub-area, and a second classifier accessible to the second data area and the second sub-area. In this case, the communication circuit inputs the received data to declare the first classifier and the second classifier. Specifically, when it is determined that the second communication address information is included in the destination, the second classifier specifies the second data area as the storage destination based on the first receiving instruction information stored in the second sub-area, and stores the received data in the second data area. As a result, the storage destination can be specified according to the address information of each OS, and distribution becomes efficient.

[0091] It should be noted that Embodiment 2 is not premised on Embodiment 1 described above, and may have a single configuration. In this instance, the semiconductor device according to the second embodiment includes: a first processor and a second processor, executing operating systems different from each other; a memory; and a communication circuit, which is controlled by the first processor. The memory includes: a first descriptor area and a first data area, the first descriptor area and the first data area are working areas of the first OS executed by the first processor; and a second descriptor area and a second data area, the second descriptor area and the second data area are working areas of the second OS executed by the second processor. Here, the second processor stores the first receiving instruction information for storing the received data in the second data area in the second descriptor area, and sends the third update notification of the second descriptor area to the first processor. In response to the third update notification, the first processor reads the receiving instruction information stored in the second descriptor area, and stores the receiving instruction information in the first descriptor area. Here, the first descriptor area includes a first sub-area corresponding to the first data area and a second sub-area corresponding to the second data area. The first processor stores the first receiving instruction information read from the second descriptor area in the second sub-area in response to the third update notification. The communication circuit maintains first communication address information corresponding to the first OS or the first processor and second communication address information corresponding to the second OS and the second processor. The communication circuit determines whether each of the first communication address information and the second communication address information is included in the destination of the received data, and when it is determined that the second communication address information is included in the destination, the received data is stored in the second data area. Even in this way, the processing load of the processor can be reduced by reducing the copy processing of the received data compared to the prior art. Further, similar to the first embodiment, the development efficiency can be improved.

[0092] Here, since the hardware configuration of the second embodiment is different from Figure 1 The hardware configuration is the same as that of , so its illustration and description are omitted. Next, Fig.10 1 is a functional diagram showing the configuration of a semiconductor device 1a according to the present second embodiment. The semiconductor device 1a is obtained by changing the configuration of a portion of the semiconductor device 1 described above. That is, in the semiconductor device 1a, the descriptor area 133 in the memory 13 of the semiconductor device 1 is replaced with a descriptor area 133a including sub-areas 1331 and 1332. In the semiconductor device 1a, the processors 11 and 12 and the communication circuit 15 of the semiconductor device 1 are replaced with processors 11a and 12a and a communication circuit 15a. Further, the descriptor area 135 is a shared area 130a that can be accessed by each of the processor 11a operated by the OS 131 and the processor 12a operated by the OS 132. Figure 2The same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

[0093] Sub-area 1331 is a descriptor area corresponding to data area 134 managed by OS 131, and is an exemplary first sub-area. Sub-area 1332 is a descriptor area corresponding to data area 136 managed by OS 132, and is an exemplary second sub-area. Therefore, in the second embodiment, descriptors for OS 131 and descriptors for OS 132 are managed independently without being mixed. Sub-area 1331 stores transmission instruction information 211 and reception instruction information 221. That is, transmission instruction information 211 and reception instruction information 221 are processed by OS 131. Sub-area 1332 stores transmission instruction information 212 and reception instruction information 222, and corresponds to transmission instruction information 213 and reception instruction information 223 in descriptor area 135. Unlike the first embodiment, data area 136 does not accept access from processor 11a.

[0094] The processor 11a reads data from and writes data to the sub-areas 1331 and 1332 respectively through data accesses 3111 and 3112. Specifically, the processor 11a copies descriptors between the descriptor area 135 and the sub-area 1332.

[0095] When the destination of the received data from the communication network N indicates the OS 132 or the processor 12a, the communication circuit 15a directly stores the received data 242 in the data area 136, stores the reception completion information in the descriptor area 133a, and sends a completion notification of the reception process to the processor 11a. Further, the communication circuit 15a maintains the first communication address information corresponding to the OS 131 or the processor 11a and the second communication address information corresponding to the OS 132 or the processor 12a, determines whether the destination of the received data includes the first communication address information and the second communication address information, and stores the received data in the data area 136 when it is determined that the destination includes the second communication address information.

[0096] Fig.11 1 is a functional block diagram showing the internal configuration of the communication circuit 15a according to the second embodiment. The communication circuit 15a includes classifiers 41 and 42, memory access units 43 and 44, and a control unit 45. However, the communication circuit 15a may have other configurations except two classifiers. That is, the communication circuit 15a is equipped with at least a plurality of receiving DMA channels, and each classifier serves as each receiving DMA channel. Therefore, the number of classifiers may be three or more.

[0097] The classifier 41 can be accessed by the data area 134 and the sub-area 1331. The classifier 42 can be accessed by the data area 136 and the sub-area 1332. The communication circuit 15a inputs the reception data received through the data input 346 from the communication network N to each of the classifiers 41 and 42.

[0098] The classifier 41 includes a storage unit 411 and a determination unit 412. The storage unit 411 stores in advance communication address information 413 indicating the OS 131 or the processor 11a. The communication address information 413 is, for example but not limited to, a belonging VLAN ID 4131 to which it belongs, and a MAC address 4132. The determination unit 412 determines whether the communication address information 413 is included in the destination of the input reception data, and when it is determined that the communication address information 413 is included, outputs the reception data and the determination result to the memory access unit 43 according to the need of receiving the determination result. On the other hand, when the communication address information 413 indicating the OS 131 or the processor 11a is not included in the destination address, the determination unit 412 discards the reception data, determines that the reception determination result is not needed, and outputs the determination result to the memory access unit 43.

[0099] The memory access unit 43 processes DMA transfer. Specifically, the memory access unit 43 can access the sub-area 1331 through the data access 3411, and can access the data area 134 through the data access 342. In response to the transmission instruction from the control unit 45, the memory access unit 43 refers to the sub-area 1331, and transmits the transmission data in the data area 134 to the communication network N through the data output 345. When the determination result of the classifier 41 indicates that reception is required, the memory access unit 43 refers to the sub-area 1331, and stores the reception data in the data area 134.

[0100] The classifier 42 includes a storage unit 421 and a determination unit 422. The storage unit 421 stores in advance communication address information 423 indicating the OS 132 or the processor 12a. The communication address information 423 is, for example but not limited to, a belonging VLAN ID 4231 to which it belongs, and a MAC address 4232. The determination unit 422 determines whether the communication address information 423 is included in the destination of the input reception data, and when it is determined that the communication address information 423 is included, outputs the reception data and the determination result to the memory access unit 44 according to the reception need. On the other hand, when the communication address information 423 indicating the OS 132 or the processor 12a is not included in the destination address, the determination unit 422 discards the reception data, determines that the reception determination result is not needed, and outputs the determination result to the memory access unit 44.

[0101] The memory access unit 44 processes DMA transfer. Specifically, the memory access unit 44 can access the sub-area 1332 through the data access 3412, and can access the data area 136 through the data access 344. In response to a transmission instruction from the control unit 45, the memory access unit 44 refers to the sub-area 1332, and transmits the transmission data in the data area 136 to the communication network N through the data output 345. When the determination result from the classifier 42 indicates that reception is required, the memory access unit 44 refers to the sub-area 1332, and stores the reception data in the data area 136.

[0102] The control unit 45 receives the transmission instruction and the reception instruction from the processor 11a through the data access 314, and transmits a completion notification through the completion interrupt 343. The control unit 45 commands the memory access units 43 and 44 in response to the transmission instruction and the reception instruction.

[0103] Fig.12 and Fig.13 is a sequence diagram showing the flow of the data receiving process according to the second embodiment. Figure 5 and Figure 6 First, the processor 11a reads out the reception instruction information 223 from the descriptor area 135 through the data access 313 in response to the update notification from the processor 12a through the IPI interrupt 331. Then, the processor 11a stores (i.e., S205a) the read reception instruction information 223 in the sub-area 1332 as the reception instruction information 222 through the data access 311. At this time, the processor 11a sets the address in the reception instruction information 223 as the reception instruction information 222 as it is without changing the address.

[0104] In response to the reception instruction from the processor 11 a ( S206 ), the communication circuit 15 a refers to the reception instruction information 221 and 222 in the sub-areas 1331 and 1332 through the data accesses 3411 and 3412 , and receives ( S207 a ) data from the communication network N through the data input 346 .

[0105] Fig.14 : is a flowchart showing the flow of the receiving process according to the second embodiment. Note that Fig.14 The same process is shown regardless of the combination of the classifier 41 and the memory access unit 43 or the combination of the classifier 42 and the memory access unit 44. In the following description, the combination of the classifier 42 and the memory access unit 44 is described.

[0106] First, the classifier 42 receives the received communication frame as received data (S301). Next, the determination unit 422 determines whether the Q-Tag VLAN is added to the header of the received communication frame (S302). Here, "Q-Tag VLAN" is defined in IEEE Std 802.1Q (registered trademark)-2014, IEEE Standard for Local and metropolitan area networks-Bridges and Bridged Networks. If step 302 is no, the process proceeds to step S304. In addition, if step S302 is yes, the determination unit 422 determines whether the Q-Tag VLAN matches the belonging VLAN ID (S303). Specifically, the determination unit 422 reads the belonging VLAN ID 4231 from the storage unit 421, and determines whether the Q-Tag VLAN matches the belonging VLAN ID 4231. If it is determined in step S303 that they are consistent with each other, the process proceeds to step S304.

[0107] Next, the determination unit 422 determines whether the destination address of the received communication frame is a broadcast / multicast address (S304). Specifically, when the 8th bit of the destination address is 1, the determination unit 422 determines that the destination address is a broadcast / multicast address, and proceeds to step S306. On the other hand, when step S304 in the step is no, the determination unit 422 determines whether the destination address is its own MAC address (S305). Specifically, the determination unit 422 reads the MAC address 4232 from the storage unit 421, and determines whether the destination address matches the MAC address 4232. If it is determined in step S305 that they are consistent with each other, the process proceeds to step S306.

[0108] If the determination result is YES in step S304 or step S305 , the determination unit 422 outputs the determination result as a reception request together with the reception communication frame to the connected memory access unit 44 ( S306 ).

[0109] Since the reception determination result is required, the memory access unit 44 reads the reception instruction information 222 from the sub-area 1332 as the connected descriptor area through the data access 3412, and identifies the storage destination as the address in the data area 136 (S307). Then, the memory access unit 44 stores the received communication frame as the received data 242 in the data area 136 as the designated storage destination through the data access unit 344 (S308). Thereafter, the memory access unit 44 stores the reception completion information in the reception instruction information 222 in the sub-area 1332 through the data access 3412 (S309, Fig.12Step S208a).

[0110] On the other hand, if the determination result of step S303 or step S305 is NO, the determination unit 422 discards the received communication frame (S310). Then, the determination unit 422 outputs the determination result that reception is not required to the connected memory access unit 44 (S311).

[0111] Back to Fig.12 The communication circuit 15a notifies the processor 11 of the completion through the completion interrupt 343 (S209 and S210).

[0112] In response to the completion notification of the completion interrupt 343, the processor 11a reads the reception instruction information 222 (reception completion information) from the sub-area 1332 through the data access 3112 (see Fig.10 and Fig.13 ), and stores the reception instruction information 222 in the descriptor area 135 through the data access 313, that is, updates or copies the reception instruction information 223 (reception completion information) (S211a). At this time, the copy processing of the received data does not occur. Thereafter, as described above, the processors 11a and 12a execute steps S213 to S216 in the same manner.

[0113] As described above, in the first embodiment ( Figure 2 ), the processor 11 stores the received data in the data area 134 managed by the processor 12, and copies the received data to the shared area 136 that the processor 12 can access through the inter-OS communication. On the other hand, in the second embodiment, the copying process of the received data associated with the inter-OS communication can be reduced. Therefore, the processing load of the processor can be further reduced compared to the first embodiment. Further, even compared to the first embodiment, it can be said that the processing load of the processor can be reduced by only eliminating the copying process of the received data of the receiving process.

[0114] Example 3

[0115] Embodiment 3 is an improved example of the above-mentioned embodiment 1. In the first embodiment, as described above, the processor 11 reads the transmission instruction information 213 from the descriptor area 135 in response to the update notification of the IPI interrupt 331 from the processor 12, and stores the transmission instruction information 213 in the descriptor area 133. At this time, the processor 11 can also generate a descriptor and store the descriptor in the descriptor area 133. In this case, as described above, the descriptor of the corresponding OS is integrated in the descriptor area 133.

[0116] Here, once a data transmission request for the communication network N is generated, each of the OSs 131 and 132 continuously generates a plurality of descriptors and continuously stores the descriptors in the descriptor area. Therefore, the storage timing of the transmission instruction information peculiar to the OS 131 and the transmission instruction information of the OS 132 conflicts with each other. If arbitration is not performed for the storage timing, the storage of the descriptor of one of the OSs may be delayed, and QoS (Quality of Service) may not be guaranteed. A similar problem may occur in receiving instruction information.

[0117] Therefore, in the third embodiment, by changing the process of copying descriptors in OS 131 executed by processor 11 in the first embodiment, the number of descriptors, data size, etc. stored in each OS are adjusted, and QoS control is achieved by controlling the communication capacity of each OS.

[0118] That is, in response to the first update notification, the first processor controls the order in which the first transmission instruction information stored in the second descriptor area and the second transmission instruction information corresponding to the transmission data stored in the first data area are stored in the first descriptor area based on the ratio of the communication capacity preset for the first OS corresponding to the second transmission instruction information and the second OS corresponding to the first transmission instruction information. In this way, when descriptors of multiple OSes are mixed in one descriptor area, QoS control can be achieved by controlling the communication capacity of each OS.

[0119] Further, the first processor can use a ratio obtained by allocating the sizes or numbers of the first transmission instruction information and the second transmission instruction information per unit time as a ratio of preset communication capacities of the first OS and the second OS. As a result, QoS control can be implemented more effectively.

[0120] The semiconductor device according to the third embodiment is obtained by changing the copying process of the descriptor in the OS 131 executed by the processor 11 in the first embodiment. Therefore, the hardware configuration and the functional block diagram are the same, and thus the illustration and description thereof are omitted.

[0121] Here, the following embodiments 3-1 and 3-2 can be cited as examples of methods for allocating communication capacities of respective OSs. However, the allocation method is not limited to these.

[0122] Example 3-1: Polling method

[0123] Embodiment 3-1 assumes that the communication capacity is uniformly allocated in advance to the OS 131 between the OS 131 side and the OS 132 side. Then, the processor 11 reads out a plurality of pieces of transmission instruction information 213 alternately from the descriptor area 135 in order and stores the pieces of transmission instruction information in the descriptor area 133, and alternately stores the pieces of transmission instruction information on the OS 131 side in the descriptor area 133. At this time, the processor 11 controls the amount of data to be transmitted by each transmission instruction information so as to have the same size. Fig.15 1 is a diagram illustrating a composite example of descriptors when the communication capacity of the present embodiment 3 is equally allocated for each OS (polling method).

[0124] Example 3-2: Token Bucket Method

[0125] Embodiment 3-2 assumes that the cumulative upper limit of the cumulative size per unit time has been set separately for each of OS 131 and OS 132 in advance for OS 131. Then, processor 11 becomes a token bucket by controlling the descriptors of OS 131 and OS 132 to switch every hour. For example, processor 11 calculates the ratio of the communication capacity between OSs in advance so as to meet the upper limit value of the cumulative size, and calculates the size of the descriptor that can be allocated per unit time. When integrating the descriptors, processor 11 divides and stores the descriptors according to the calculated value, and switches the target OS per time unit.

[0126] Fig.16 : is a diagram showing an exemplary token bucket method of synthesizing descriptors when each of the upper limit OSs of the cumulative size of descriptors per unit time is set according to the present embodiment 3. Fig.16 In the example, the transmission rate on the processor 11c side (shaded part) is assigned to 2Mbps (250 bytes / ms), and the transmission rate on the processor 12c side (dashed line part) is assigned to 4Mbps (500 bytes / ms). At this time, 1Mbps = (1000000 / 8) / 1000 = 125 bytes per millisecond. In this way, QoS control becomes possible.

[0127] Here, when the OS 131 operating in the processor 11 is a secure OS, even if an abnormal Ethernet frame transmission request occurs from another OS 132, the descriptor is copied only within the ratio of the communication capacity set in the corresponding OS, as described above. As a result, excessive frame transmission requests can be prevented. Specifically, if the OS 132 needs to send an abnormal number of Ethernet frames, a malicious application may be running or out of control. Therefore, the third embodiment is effective as a functional safety control for suppressing adverse effects on external systems. In addition, by using a secure OS for the OS 131 operated by the processor 11, failures of another OS 132 can be suppressed, thereby suppressing illegal operations and improving the robustness of the system.

[0128] In the embodiments described above, the case where the processor and the OS are one-to-one is described, but the embodiments are not limited thereto, and each embodiment can be applied even if the ratio between the number of processors and the number of OS is different. In addition, a hypervisor can be inserted in inter-OS communication. The communication circuit is not limited to Ethernet communication hardware.

[0129] In the embodiments described above, a single semiconductor device has been described, but these embodiments may also be applied to an information processing system. In this case, the information processing system may have the following configuration. That is, the information processing system includes: a first processor and a second processor, executing different OS (operating systems); a memory; and a communication circuit, which is controlled by the first processor, wherein the memory includes: a first descriptor area and a first data area, the first descriptor area and the first data area are working areas of the first OS executed by the first processor; and a second descriptor area and a second data area, the second descriptor area and the second data area are working areas of the second OS executed by the second processor, wherein the second processor stores the first sending instruction information corresponding to the sending data stored in the second data area in the second descriptor area, and sends the first update notification of the second descriptor area to the first processor, wherein the first processor reads the first sending instruction information stored in the second descriptor area, stores the first sending instruction information in the first descriptor area, and stores the first sending instruction in the first descriptor area. The communication circuit performs the sending process of the sending data stored in the second data area based on the first sending instruction information stored in the first descriptor area. As a result, the same effect as the first embodiment can be obtained.

[0130] Although the invention made by the inventors has been specifically described based on the embodiments, the present invention is not limited to the embodiments that have been described, and it is apparent that various modifications can be made without departing from the gist of the present invention.

Claims

1. A semiconductor device, comprising: A first processor and a second processor, wherein the first processor and the second processor are used to execute different operating systems OS; Memory; as well as a communication circuit, controlled by the first processor, The memory comprises: a first descriptor area and a first data area, the first descriptor area and the first data area being work areas of a first OS executed by the first processor; as well as a second descriptor area and a second data area, the second descriptor area and the second data area being work areas of a second OS executed by the second processor, wherein the second processor stores first receiving instruction information for receiving data in the second descriptor area, and sends a third update notification of the second descriptor area to the first processor, The first descriptor area includes a first sub-area corresponding to the first data area and a second sub-area corresponding to the second data area, wherein in response to the third update notification, the first processor stores the first received instruction information read from the second descriptor in the second sub-area, wherein the communication circuit 1) holds first communication address information corresponding to the first OS or the first processor and second communication address information corresponding to the second OS or the second processor, 2) determines whether each of the first communication address information and the second communication address information is included in the destination of the received data, 3) stores the received data in the second data area when it is determined that the second communication address information is included in the destination, and 4) notifies the first processor of a completion notification, and The first processor updates the first received instruction information stored in the second descriptor area, and sends a fourth update notification of the second descriptor to the second processor.

2. The semiconductor device according to claim 1, wherein The communication circuit includes a first classifier accessible to the first data area and the first sub-area, and a second classifier accessible to the second data area and the second sub-area, the communication circuit inputting the received data into each of the first classifier and the second classifier, and The second classifier identifies the second data area as the destination based on the first reception instruction information stored in the second sub-area, and stores the reception data in the second data area when determining that the second communication address information is included in the destination.

3. The semiconductor device according to claim 1, wherein The second descriptor area is a shared area capable of accessing data from each of the first processor operating the first OS and the second processor operating the second OS.

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