A deterministic test-per-clock test device for dynamic reconfiguration of scan chains

Abstract

The present invention discloses a deterministic test-per-clock test device for dynamic reconfiguration of a scan chain. The present invention comprises: a selector, a mode controller, a response analyzer and a dynamically reconfigured scan chain group; the test-per-clock test device is a test-per-clock block test device based on dynamic reconfiguration of the scan chain, wherein the scan unit structure in the scan chain is divided into an SFD and a DFD structure, the scan chain type is divided into an SFD scan chain and a DFD scan chain, and the test mode of the scan chain is divided into a shift test mode and a response compression test mode. During circuit testing, the scan chain is dynamically reconfigured by the mode controller, and the test data is input into the corresponding test mode scan chain through the selector, thereby realizing block testing of the circuit. The present invention simplifies the test generation of sequential circuits into the test generation of combinational circuits, and can optimize the wiring overhead and control complexity, providing an effective solution to the problems of excessive test storage, excessive test application time, and excessive test power consumption in ultra-large-scale circuit testing.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a deterministic test-per-clock testing technology for digital integrated circuits, in particular to a deterministic test-per-clock testing device for dynamic reconfiguration of scan chains. Background Art

[0002] Traditional fixed-type tests and delay tests generally use the test-per-scan mode, that is, during testing, the test vector is serially shifted in from the scan chain. After the test vector is applied, the captured test response is serially shifted out of the scan chain, and the next test vector is serially shifted in. Each scan cycle generates a test vector. Therefore, the test application time of test-per-scan is the product of the length of the scan chain in the circuit and the number of test vectors. In fact, the test application (launch) time is only the number of test vectors, and most of the test time is consumed in scan shifting. With the increase in circuit scale, the inefficient test-per-scan technology has become no longer suitable.

[0003] Test-per-clock testing is gaining more and more attention. It applies vectors and captures responses in parallel. A test vector is generated in each test clock cycle, and its response is captured by the response analyzer (RA). Therefore, compared with the test-per-scan mode, the test-per-clock mode has a strong advantage in test application time. However, since each test clock needs to generate test vectors and capture responses, the area overhead and test power consumption of its test structure are higher than those of the conventional test-per-scan structure. The optimization of test structure and test power consumption has always been a hot topic in the research of test-per-clock testing. The BILBO (built-in logic block observer) test structure transforms the trigger so that it can switch between normal mode, shift mode, pseudo-random mode and MISR (multiple input shift register) response compression mode. CBILBO transforms the trigger into double flip-flop mode. In the CBILBO structure, TPG and RA are independent, and pseudo-random vector generation and response compression can be performed simultaneously. Due to the existence of anti-pseudo-random faults, it is difficult for the fault detection of pseudo-random test methods to achieve satisfactory coverage in a short time. Hu Chen et al. proposed a test-per-clock method for controlling the jump of LFSR in the paper "A built-in self-test structure based on controlled LFSR and its test vector generation", which effectively improved the test efficiency. Zhou Bin et al. proposed a test method based on 2-bit twisting ring counter (TRC) in the paper "A Low Power Test-per-Clock BIST Scheme through Selectively Activating Multi Two-Bit TRCs", which effectively reduced the test power consumption of test-per-clock and improved the fault coverage by selectively activating the twisting ring counter.

[0004] However, the above method is only for combinational circuit testing. In the test-per-clock test of the scan sequential circuit, since the response of the pseudo-primary output (PPO) inside the circuit needs to be processed at each test clock, the design of the response analyzer for the test-per-clock test of the scan sequential circuit is much more complicated than the test-per-scan test. Bardell et al. modified the scan chain in the patent "US4513418" and used the compression processing result of the test response as the next test generation, so that it has the functions of vector generation and response compression at the same time. Son et al. proposed a degenerate MISR to replace the response compression in the paper "E-BIST: enhanced test-per-clock BIST architecture", simplifying the structure of Bardell. Krasniewski et al. proposed a circular self-test path (CSTP) method in the paper "Circular self-testpath: a low-cost BIST technique", which transforms the sequential unit in the circuit into a CSTP unit and connects them in series into a circular chain. The circular chain can be used as a test vector generator and a test response analyzer at the same time, so it has the advantages of small area overhead and relatively simple control logic. In view of the defect that the above-mentioned (quasi) pseudo-random test is difficult to meet the fault coverage in a limited time, Wen Ke et al. implemented a deterministic CSTP method by adding jump logic in the paper "Deterministic Circular SelfTest Path". When multiple consecutive test vectors cannot detect new faults, they jump to another determined vector through jump logic to continue running. However, due to the insertion of additional hardware, the introduction of too much delay will be detrimental to delay testing. Novák et al. proposed a deterministic test-per-clock test structure in the paper "Test-per-Clock Testing of the Circuits with Scan", which effectively reduced the test application time and test data storage. However, when the circuit is in test mode, the functional trigger no longer receives the circuit response, but is received in parallel by the additionally designed space compressor and MISR. Although the space compressor reduces the number of inputs of the MISR, since it is composed of an XOR network, the multi-layer XOR gate will deteriorate the delay of response capture and cannot adapt to high-frequency testing. In addition, the space compressor makes the adaptability of the test structure single. Any structural changes of the circuit (such as late-stage engineering change order, ECO) and changes in the test program (such as changing the test set) will lead to a decrease in fault coverage.Rajski proposed a scan chain dynamic reconstruction method in the patent "United States Patent9714981". In this method, part of the scan chain applies test stimulus, part of the scan anchor chain performs response capture, and the remaining triggers are used as functional units, thereby effectively reducing the power consumption of traditional test-per-clock testing and the hardware overhead of the response analyzer. The disadvantages are complex control and high wiring overhead. At the same time, since it is based on the test generation of sequential circuits, compared with the full scan design circuit, the test generation is much more complicated, and some faults may even be untestable in a limited test cycle.

[0005] Summary: In terms of test-per-clock testing, although the test-per-clock test device based on (quasi) pseudo-random test-per-clock is simple and easy to implement, its test efficiency is not high. The deterministic test-per-clock test device based on the traditional scan chain structure has a large test structure hardware overhead and the test power consumption is too high. The deterministic test-per-clock test device based on the traditional scan chain dynamic reconfiguration structure has complex test generation and large wiring overhead. Summary of the invention

[0006] The purpose of the present invention is to address the deficiencies in the prior art and to provide a deterministic test-per-clock test device for dynamic reconfiguration of a scan chain, which can complete high-quality and low-cost detection of fixed-type faults and delay faults with low test application time, low test storage overhead and hardware logic overhead, and low test power consumption.

[0007] The technical solution adopted by the present invention to solve the technical problem is as follows:

[0008] The present invention includes a selector, a mode controller, a response analyzer and a dynamically reconfigured scan chain group; the test-per-clock test device is a test-per-clock block test device based on dynamic reconfiguration of the scan chain, the scan unit structure in the scan chain is divided into SFD and DFD structures, so the scan chain type is divided into SFD scan chain and DFD scan chain, and the test mode of the scan chain is divided into a shift test mode (S) scan chain and a response compression mode (C) scan chain.

[0009] The SFD scan chain is implemented by connecting SFD scan units in series;

[0010] The DFD scanning chain is realized by connecting DFD scanning units in series;

[0011] During testing, each scan chain has two optional working modes, namely, shift test mode (S) and response compression mode (C); the scan chain in the shift test mode (S) constitutes a shift register, and the test data is loaded into each shift register through a selector, and a shift test vector is generated in each test clock cycle; at the same time, the scan chain in the response compression mode (C) constitutes a response compressor, which receives and processes the test responses stimulated by the shift test mode (S) scan chain in parallel; when the test cycle ends, each scan chain reconfigures the mode through the mode controller and enters the next test cycle.

[0012] The DFD scanning unit is implemented by two triggers, and can simultaneously perform a shift test mode (S) and a response compression mode (C);

[0013] The working modes of the DFD scanning unit and the SFD scanning unit are as follows:

[0014] When the signal value of the control signal M1M2 is "11", the DFD scanning unit and the SFD scanning unit work in the shift test mode, the scan-in receives the shift test data from the previous scanning unit, and applies the test vector to the circuit through the Q terminal; at the same time, the FF2 trigger of the DFD scanning unit can also perform response compression at the same time;

[0015] When the signal value of the control signal M1M2 is "10", the DFD scanning unit and the SFD scanning unit work in the response compression mode (C), perform response compression, and the output Q end is blocked;

[0016] When the signal value of the control signal M1M2 is "01", the DFD scanning unit and the SFD scanning unit operate in the normal function mode.

[0017] The determination of the scan chain will not transmit the test response generated by the application of the test stimulus to any scan unit on the same scan chain to the unit of the scan chain;

[0018] The scanning unit type is determined according to the requirements, and the sequential circuit test generation is simplified to the combinational logic level test generation, while reducing the wiring overhead and the number of test mode switching times; the specific implementation process is:

[0019] The determination of scan chains, i.e. the grouping of scan units, is implemented based on graph coloring theory. Unrelated scan units are found and grouped into the same scan chain, so that the test response generated by any scan unit in the same scan chain when applying test stimulus will not be transmitted to the unit in the scan chain, but will be received and processed by other scan chains.

[0020] Determination of the scanning unit type. There are two types of scanning units, namely DFD scanning unit and SFD scanning unit. The scanning unit type is determined according to the following rules:

[0021] ① During testing, when a trigger needs to act as both a test stimulus trigger and a test response trigger, the trigger is transformed into a DFD scanning unit;

[0022] ② In order to optimize the wiring overhead and control complexity, the trigger can be transformed into a DFD scanning unit; when the wiring overhead of a scanning unit exceeds the budget, it can be transformed into a DFD scanning unit and included in the DFD scan chain to reduce the wiring overhead; on the other hand, when the number of units on a scan chain is lower than the set threshold, it can be transformed into a DFD scanning unit, thereby reducing the number of test mode switching;

[0023] ③Other triggers are transformed into SFD scanning units.

[0024] The scan chain test mode determination must comply with the following rules:

[0025] ① When a test vector is applied, as long as there is a certain position of the vector on the scan chain, the scan chain is in shift test mode (S);

[0026] ② When the test vector is applied, the fault response must be captured by at least one scan unit, and the scan chain where the scan unit is located is in response compression mode (C);

[0027] ③When the test vector is applied, the irrelevant scan chain is set to the response compression mode (C) to block the input of the irrelevant circuit.

[0028] The beneficial effects of the present invention are as follows:

[0029] In the present invention, the multi-scan chain structure adopted greatly reduces the length of the shift register compared with the traditional single scan chain structure, which will effectively improve the test efficiency; on the other hand, compared with the traditional method in which the scan unit is all implemented by double flip-flop (DFD) design, the present invention introduces a single flip-flop (SFD) design, which effectively reduces the hardware cost of the response analyzer; compared with the traditional scan chain reconfiguration test device, the DFD unit design proposed in the present invention can not only simplify the test generation of the sequential circuit to the test generation of the combinational logic circuit, but also optimize the wiring overhead and optimize the control complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a structural diagram of the scan chain reconfiguration block test device of the present invention;

[0031] Figure 2-a This is a structural diagram of the DFD scanning unit of the present invention;

[0032] Figure 2-b This is a structural diagram of the SFD scanning unit of the present invention;

[0033] Figure 3 It is the working mode diagram of the DFD and SFD units of the present invention;

[0034] Figure 4 This is an example diagram of grouping of scanning units of the present invention; DETAILED DESCRIPTION

[0035] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0036] like Figure 1-4 As shown, a deterministic test-per-clock test device based on dynamic reconfiguration of scan chains includes: a test-per-clock block test device based on dynamic reconfiguration of scan chains, implementation of SFD (single flip-flop design) and DFD (double flip-flop design) scan units, determination of scan chain and scan unit types, and determination of scan chain test modes.

[0037] The test-per-clock block test device based on dynamic reconfiguration of scan chains is as follows:

[0038] Block test device based on scan chain reconfiguration Figure 1 As shown, it includes a memory 101, a selector 102, a dynamically reconfigured scan chain group 103, a mode controller 104, and a response analyzer 105. During testing, the test data stored in the memory 101 is loaded into the corresponding scan chain through the selector 102. There are two forms of scan chains, one is to use SFD (single flip-flop design) scan units in series, and the other is to use DFD (double flip-flop design) scan units in series. During testing, each scan chain has two optional working modes, namely, shift test mode (S) and response compression mode (C). The scan chain in S mode constitutes a shift register, and the test data is loaded into each shift register through the selector 102, and a shift test vector is generated for each test. At the same time, the scan chain in C mode constitutes a response compressor, which receives and processes the test response stimulated by the S mode scan chain in parallel. When the test cycle is over, each scan chain reconfigures the mode through the mode controller 104 and enters the next test cycle. At the same time, the response analyzer 105 receives the outputs of each scan chain in parallel to perform response compression.

[0039] The implementation of SFD (single flip-flop design) and DFD (double flip-flop design) scanning units is as follows:

[0040] The implementation of SFD and DFD scanning unit structures are as follows: Figure 2-a and Figure 2-b As shown, the DFD scanning unit includes a multiplexer 201, an XOR gate 202, a first flip-flop (FF1) 203, a second flip-flop (FF2) 204, a first AND gate 205 and a second AND gate 206;

[0041] The two input terminals of the multiplexer 201 are connected to the scan-in terminal and the D terminal respectively; the scan-in terminal receives the shift test data from the scan-out terminal of the previous DFD scanning unit; the D terminal is the input terminal of the original functional circuit trigger; the output terminal of the multiplexer 201 is connected to the input terminal of the first trigger (FF1) 203; the output terminal of the first trigger (FF1) 203 is connected to an input terminal of the first AND gate 205, the other input terminal of the first AND gate 205 is connected to the signal M2, the output terminal of the first AND gate 205 is the Q terminal, and the test vector is applied to the circuit through the Q terminal; the output terminal scan_out of the first trigger (FF1) 203 is simultaneously connected to the next DFD scanning unit The two input terminals of the XOR gate 202 are connected to the res-in terminal and the D terminal respectively; the res-in terminal receives the circuit response data from the res-out terminal of the previous DFD scanning unit; the output terminal of the XOR gate 202 is connected to the input terminal of the second trigger (FF2) 204, the output terminal of the second trigger (FF2) 204 is connected to an input terminal of the second AND gate 206, the other input terminal of the second AND gate 206 is connected to the signal M1, the output terminal of the second AND gate 206 is the res_out terminal, and is connected to the res_in terminal of the next DFD scanning unit through the res_out terminal; the signal M1 is also connected to the selection signal terminal of the multiplexer 201.

[0042] The SFD unit includes a second XOR gate 211 , a second multiplexer 212 , a third multiplexer 213 , a third flip-flop 214 , and a third AND gate 215 .

[0043] The two input terminals of the second XOR gate 211 are connected to the scan-in terminal and the D terminal respectively; the scan-in terminal receives the shift test data from the scan-out terminal of the previous SFD scanning unit; the output terminal of the second XOR gate 211 is connected to an input terminal of the third multiplexer 213; the two input terminals of the second multiplexer 212 are connected to the scan-in terminal and the D terminal respectively; the output terminal of the second multiplexer 212 is connected to the other input terminal of the third multiplexer 213; the output terminal of the third multiplexer 213 is connected to the input terminal of the third trigger 214, and the output terminal of the third trigger 214 is the scan_out terminal, which is respectively connected to the scan-in terminal of the next SFD scanning unit and an input terminal of the second AND gate 215, and the other input terminal of the second AND gate 215 is connected to the signal M2. The selection signal terminal of the second multiplexer 212 is connected to the signal M1, and the selection signal terminal of the third multiplexer 213 is connected to the signal M2.

[0044] The biggest difference between the DFD unit and the SFD unit is that it uses two triggers to implement and can perform shift testing and response compression at the same time.

[0045] The working modes of DFD unit and SFD unit are as follows Figure 3 As shown in the figure: When the signal value of M1M2 is "11", the SFD and DFD units work in the shift test mode, scan-in receives the shift test data from the previous scan unit, and applies the test vector to the circuit through the Q terminal. Unlike the SFD unit, the FF2 trigger of the DFD unit can also perform response compression at the same time. When the signal value of M1M2 is "10", the SFD and DFD units work in the response mode, perform response compression, and the output Q terminal is blocked. When the signal value of M1M2 is "01", the SFD and DFD units work in the normal function mode.

[0046] Since the clock signal of each trigger can be provided by the system clock, the proposed test device can be applied to full-speed test-per-clock testing, and when the scan chain is in response mode, both SFD and DFD adopt Q-end blocking technology, at which time the irrelevant circuit blocks will be in a stable state, thus effectively reducing the test power consumption. The shift test adopted in the test device just meets the LOS (latch-on-shift) test mechanism (the latter vector is obtained by shifting the former vector), and since the test stimulus (vector) loading and response capture in the circuit are performed by triggers on different scan chains respectively, this scheme effectively gets rid of the implementation problem of scan-enable signal in the traditional LOS method.

[0047] The scan chain and scan unit type are determined by:

[0048] The determination of the scan chain, that is, the grouping of scan units, can be implemented based on graph coloring theory. The basic idea is to find out unrelated scan units and group them into the same scan chain, so that the test response generated by the test stimulus applied to any scan unit on the same scan chain will not be transmitted to the scan chain unit, but will be received and processed by other scan chains. Figure 4 An example circuit is given in (a). Figure 4 (b) shows the corresponding directed graph of the circuit, where each vertex corresponds to a scan unit (flip-flop unit), and the directed edge between vertex A and B indicates that there is a combinational logic path from A (drive) to B (receive). Figure 4 (c) shows the optimized undirected graph, and the grouping problem of scanning units can be transformed into a vertex coloring problem. Figure 4 As shown in (c), the scan chain of the example circuit can be organized as follows: FF1 and FF3 can be located in the same scan chain, and FF2 and FF4 are located in different scan chains.

[0049] Scanning unit type determination. There are two types of scanning units, namely DFD units and SFD units. The type determination follows the following rules:

[0050] ① During testing, when a trigger needs to act as both a test stimulus trigger and a test response trigger, the trigger is transformed into a DFD scanning unit. Figure 4 In the FF4 trigger, when testing the fault at the fault point f, the trigger FF4 must be used as both a test stimulus and a test response. Therefore, the trigger FF4 should be transformed into a DFD unit so that it can perform both test stimulus generation and test response compression. It is worth noting that in the patent "United States Patent 9714981", since there is no scanning unit that can perform both stimulus generation and response compression at the same time, when detecting the fault at point f, FF4 can only be used as a functional trigger, and the fault is activated through multiple cycles of control assignments at other input terminals. Some faults may be untestable in a limited test cycle;

[0051] ② If it is necessary to consider optimizing the wiring overhead and control complexity, the trigger can be transformed into a DFD scan unit. For example, when the wiring overhead of implementing a scan unit is too high, it can be transformed into a DFD unit and included in the DFD scan chain to reduce the wiring overhead. On the other hand, when the number of units on a scan chain is small, such as Figure 4 FF2 can be transformed into a DFD scanning unit and included in the same scan chain with FF4, thereby reducing the number of test mode switching times;

[0052] ③Other triggers are transformed into SFD scanning units.

[0053] From the above rules, we can see that the DFD scanning unit design increases the hardware overhead compared to the SFD, but it can effectively reduce the test generation complexity and test generation cycle, and simplify the sequential circuit test generation to the combinational logic level test generation. At the same time, the DFD scanning unit is not restricted by position, and the routing overhead and the number of test mode switching times can be effectively reduced by converting the DFD design.

[0054] The scan chain test mode is determined by:

[0055] During testing, the scan chain can be in two modes, namely, shift test mode (S) and response compression mode (C). The mode determination follows the following rules:

[0056] ① When a test vector is applied, as long as there is a certain position of the vector on the scan chain, the scan chain is in shift test mode (S);

[0057] ② When the test vector is applied, the fault response must be captured by at least one scan unit, and the scan chain where the scan unit is located is in response compression mode (C);

[0058] ③When the test vector is applied, the irrelevant scan chain is set to the response compression mode (C) to block the input of the irrelevant circuit.

[0059] The above embodiment is an implementation method of the method of the present invention, which is a deterministic test-per-clock test device based on dynamic reconfiguration of the scan chain, but the implementation method of the present invention is not limited to the said embodiment. Any other changes, modifications, substitutions, combinations, and simplifications that deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. A deterministic test-per-clock test apparatus for dynamic reconfiguration of a scan chain, comprising: A selector, a mode controller, a response analyzer, and a dynamically reconfigured scan chain group; characterized in that: the test-per-clock test device is a test-per-clock block test device based on dynamic reconfiguration of the scan chain, the scan unit structure in the scan chain is divided into SFD and DFD structures, the scan chain type is divided into SFD scan chain and DFD scan chain, and the test mode of the scan chain is divided into a shift test mode (S) scan chain and a response compression mode (C) scan chain; The test-per-clock test device is a test-per-clock block test device based on dynamic reconfiguration of scan chains; The SFD scan chain is implemented by connecting SFD scan units in series; The DFD scanning chain is realized by connecting DFD scanning units in series; During the test, each scan chain has two optional working modes, namely, shift test mode (S) and response compression mode (C); the scan chain in the shift test mode (S) constitutes a shift register, and the test data is loaded into each shift register through the selector, and a shift test vector is generated in each test clock cycle; at the same time, the scan chain in the response compression mode (C) constitutes a response compressor, which receives and processes the test response stimulated by the scan chain in the shift test mode (S) in parallel; when the test cycle ends, each scan chain reconfigures the mode through the mode controller and enters the next test cycle; The DFD scanning unit is implemented by two triggers, and can simultaneously perform a shift test mode (S) and a response compression mode (C); The working modes of the DFD scanning unit and the SFD scanning unit are as follows: When the signal value of the control signal M1M2 is "11", the DFD scanning unit and the SFD scanning unit work in the shift test mode, the scan-in receives the shift test data from the previous scanning unit, and applies the test vector to the circuit through the Q terminal; at the same time, the FF2 trigger in the DFD scanning unit can also perform response compression at the same time; When the signal value of the control signal M1M2 is "10", the DFD scanning unit and the SFD scanning unit work in the response compression mode (C), perform response compression, and the output Q end is blocked; When the signal value of the control signal M1M2 is "01", the DFD scanning unit and the SFD scanning unit operate in the normal function mode.

2. A deterministic test-per-clock test device for dynamic reconfiguration of scan chains as claimed in claim 1, characterized in that: The determination of the scan chain will not transmit the test response generated by the application of the test stimulus to any scan unit on the same scan chain to the unit of the scan chain; The scanning unit type is determined according to the requirements, and the sequential circuit test generation is simplified to the combinational logic level test generation, while reducing the wiring overhead and the number of test mode switching times; the specific implementation process is: The determination of scan chains, i.e. the grouping of scan units, is implemented based on graph coloring theory. Unrelated scan units are found and grouped into the same scan chain, so that the test response generated by any scan unit in the same scan chain when applying test stimulus will not be transmitted to the unit in the scan chain, but will be received and processed by other scan chains. Determination of the scanning unit type. There are two types of scanning units, namely DFD scanning unit and SFD scanning unit. The scanning unit type is determined according to the following rules: ① During testing, when a trigger needs to act as both a test stimulus trigger and a test response trigger, the trigger is transformed into a DFD scanning unit; ② In order to optimize the wiring overhead and control complexity, the trigger can be transformed into a DFD scanning unit; when the wiring overhead of a scanning unit exceeds the budget, it can be transformed into a DFD scanning unit and included in the DFD scan chain to reduce the wiring overhead; on the other hand, when the number of units on a scan chain is lower than the set threshold, it can be transformed into a DFD scanning unit, thereby reducing the number of test mode switching; ③Other triggers are transformed into SFD scanning units.

3. A deterministic test-per-clock test device for dynamic reconfiguration of a scan chain as claimed in claim 1 or 2, characterized in that: The scan chain test mode determination must comply with the following rules: ① When a test vector is applied, as long as there is a certain position of the vector on the scan chain, the scan chain is in shift test mode (S); ② When the test vector is applied, the fault response must be captured by at least one scan unit, and the scan chain where the scan unit is located is in response compression mode (C); ③When the test vector is applied, the irrelevant scan chain is set to the response compression mode (C) to block the input of the irrelevant circuit.

4. The deterministic test-per-clock test device for dynamic reconfiguration of scan chains according to claim 1, characterized in that: The DFD scanning unit includes a multiplexer 201, an XOR gate 202, a first flip-flop (FF1) 203, a second flip-flop (FF2) 204, a first AND gate 205 and a second AND gate 206; The two input terminals of the multiplexer 201 are connected to the scan-in terminal and the D terminal respectively; the scan-in terminal receives the shift test data from the scan-out terminal of the previous DFD scanning unit; the D terminal is the input terminal of the original functional circuit trigger; the output terminal of the multiplexer 201 is connected to the input terminal of the first trigger (FF1) 203; the output terminal of the first trigger (FF1) 203 is connected to an input terminal of the first AND gate 205, the other input terminal of the first AND gate 205 is connected to the signal M2, the output terminal of the first AND gate 205 is the Q terminal, and the test vector is applied to the circuit through the Q terminal; the output terminal scan_out of the first trigger (FF1) 203 is simultaneously connected to the next DFD scanning unit The two input terminals of the XOR gate 202 are connected to the res-in terminal and the D terminal respectively; the res-in terminal receives the circuit response data from the res-out terminal of the previous DFD scanning unit; the output terminal of the XOR gate 202 is connected to the input terminal of the second trigger (FF2) 204, the output terminal of the second trigger (FF2) 204 is connected to an input terminal of the second AND gate 206, the other input terminal of the second AND gate 206 is connected to the signal M1, the output terminal of the second AND gate 206 is the res_out terminal, and is connected to the res_in terminal of the next DFD scanning unit through the res_out terminal; the signal M1 is also connected to the selection signal terminal of the multiplexer 201.

5. The deterministic test-per-clock test device for dynamic reconfiguration of scan chains according to claim 1, characterized in that: The SFD unit includes a second XOR gate 211, a second multiplexer 212, a third multiplexer 213, a third flip-flop 214, and a third AND gate 215; The two input terminals of the second XOR gate 211 are connected to the scan-in terminal and the D terminal respectively; the scan-in terminal receives the shift test data from the scan-out terminal of the previous SFD scanning unit; the output terminal of the second XOR gate 211 is connected to an input terminal of the third multiplexer 213; the two input terminals of the second multiplexer 212 are connected to the scan-in terminal and the D terminal respectively; the output terminal of the second multiplexer 212 is connected to the other input terminal of the third multiplexer 213; the output terminal of the third multiplexer 213 is connected to the input terminal of the third trigger 214, and the output terminal of the third trigger 214 is the scan_out terminal, which is respectively connected to the scan-in terminal of the next SFD scanning unit and an input terminal of the second AND gate 215, and the other input terminal of the second AND gate 215 is connected to the signal M2; the selection signal terminal of the second multiplexer 212 is connected to the signal M1, and the selection signal terminal of the third multiplexer 213 is connected to the signal M2.

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