A chip packaging structure and packaging method thereof

Abstract

The present invention discloses a chip packaging structure and a packaging method thereof, belonging to the field of semiconductor packaging technology. A dielectric layer I (310) is arranged on the front of a supporting substrate (100), and a portion of the upper surface of the dielectric layer I (310) sequentially covers a bump bottom metal layer I (410), a dielectric layer II (320), a bump bottom metal II (420), a dielectric layer III (330), a bump bottom metal III (440) and a dielectric layer IV (340); at the same time, an antenna circuit chip (510) is arranged in the center of the dielectric layer I (310), and the bump bottom metal III (440) selectively connects the antenna circuit chip (510) and the bump bottom metal II (420). The packaging method of the present invention reduces the area of ​​the circuit board occupied by the antenna, improves the integration performance of the antenna packaging structure and the antenna efficiency, and reduces the power consumption of the antenna packaging structure.

Description

Technical Field

[0001] The present invention relates to a chip packaging structure and a packaging method thereof, in particular to a wafer-level chip packaging structure with an integrated antenna and a packaging method thereof, and belongs to the technical field of semiconductor packaging. Background Art

[0002] Due to the advancement of science and technology, various high-tech electronic products have been developed to facilitate people's lives, including various electronic devices such as notebook computers, mobile phones, tablet computers (PAD), etc. With the popularization of these high-tech electronic products and the increase in people's needs, in addition to the substantial increase in the functions and applications configured in these high-tech products, the function of wireless communication has been added, especially to meet people's needs for mobility. The development of wireless communication technology requires RF systems to be smaller and more powerful. The traditional method installs chip-level antennas together with RF transceivers on the PCB circuit board. The space occupied by the antenna hinders the miniaturization of the system, and the transmission line number of this packaging method is long, the efficiency is poor, and the power consumption is high. For example, the traditional PCB packaging has too much loss under 5G millimeter wave transmission, and the antenna is directly made to be connected to the surface of the circuit board. Figure 1 This approach will cause the antenna to occupy additional circuit board area, which has poor integration. In addition, there is no protection around the antenna circuit chip, which can easily cause the chip to break and wear, reducing product reliability. Summary of the invention

[0003] The purpose of the present invention is to overcome the above-mentioned shortcomings and provide a chip packaging structure and a packaging method thereof to improve the integration of the circuit board and reduce the circuit board area. The antenna circuit chip is protected by an encapsulation layer around it, thereby improving the reliability of the antenna packaging structure.

[0004] The object of the present invention is achieved in that:

[0005] The present invention discloses a chip packaging structure, which comprises an antenna circuit chip, a dielectric layer I, a dielectric layer II, a dielectric layer III, a dielectric layer IV, a bottom bump metal layer I, a bottom bump metal II, a bottom bump metal III and an encapsulation layer, wherein the upper surface of the antenna circuit chip is provided with a plurality of chip electrodes of the antenna circuit chip monomer;

[0006] A discontinuous bottom bump metal layer I is disposed on the upper surface of the dielectric layer I, the dielectric layer II covers the bottom bump metal layer I, and a plurality of dielectric layer II openings I are provided to expose a portion of the bottom bump metal layer I, forming an input / output terminal of the bottom bump metal layer I, and the bottom bump metal II is disposed at the input / output terminal of the bottom bump metal layer I;

[0007] The antenna circuit chip includes active components and passive components, which are arranged in the chip area I in the center of the dielectric layer II and fixedly connected to the dielectric layer II through an adhesive film or an adhesive, and the chip electrode of the antenna circuit chip monomer faces upward;

[0008] The encapsulation material covers the dielectric layer II and encapsulates the antenna circuit chip, the chip electrode of the antenna circuit chip monomer and the bump bottom metal II to form an encapsulation layer;

[0009] The upper surface of the encapsulation layer is flush with the upper surface of the metal II at the bottom of the bump and the upper surface of the chip electrode of the antenna circuit chip monomer;

[0010] The dielectric layer III covers the upper surface of the encapsulation layer, and is provided with a dielectric layer III opening I and a dielectric layer III opening II, wherein the dielectric layer III opening I exposes a portion of the bump bottom metal II to form an input / output terminal of the bump bottom metal II, and the dielectric layer III opening II exposes a chip electrode of an antenna circuit chip monomer to form an input / output terminal of the chip electrode of the antenna circuit chip monomer;

[0011] The surface of the dielectric layer III is covered with a plurality of discontinuous bottom bump metals III, and the outermost layer of the bottom bump metal III is provided with an input / output terminal of the bottom bump metal III; the bottom bump metal III selectively connects the chip electrode and the bottom bump metal II of the antenna circuit chip monomer on the same side;

[0012] The dielectric layer IV covers all the bump bottom metal III, and an opening I of the dielectric layer IV is provided to expose a part of the bump bottom metal III, thereby forming an input / output terminal of the bump bottom metal III.

[0013] Optionally, the active component is a power management circuit, a transmitting circuit or a receiving circuit.

[0014] Optionally, the passive component is one or more of a resistor, a capacitor and an inductor.

[0015] Optionally, the bump bottom metal II includes a metal seed layer II and a rewiring metal layer II in sequence from bottom to top.

[0016] Optionally, the material of the encapsulation layer includes but is not limited to one of polyimide, silica gel and epoxy resin.

[0017] Optionally, a solder ball is provided at the input / output end of the metal III at the bottom of the bump.

[0018] Optionally, the cross-sectional shape of the metal II at the bottom of the bump is circular or rectangular.

[0019] The present invention provides a packaging method for a chip packaging structure, the packaging method comprising the following steps:

[0020] Step 1, providing a supporting substrate, providing a separation layer on the upper surface of the supporting substrate, and providing a dielectric layer I on the upper surface of the separation layer by using a photolithography process;

[0021] Step 2: depositing a metal seed layer I on the upper surface of the dielectric layer I by sputtering or chemical plating, and then forming a patterned rewiring metal layer I by a rewiring process and removing the ineffective metal seed layer I by etching to form a bump bottom metal layer I;

[0022] Step 3, using a photolithography process to cover the dielectric layer II on the bottom metal layer I of the bump and to open an opening I in the dielectric layer II, so as to form an input / output terminal of the bottom metal layer I of the bump;

[0023] Step 4: depositing a metal seed layer II on the upper surface of the dielectric layer II by sputtering or chemical plating, and then forming a patterned rewiring metal layer II by a rewiring process, and removing the invalid metal seed layer II by etching to form a bump bottom metal II and a chip region I, wherein the chip region I is located in the center of the bump bottom metal II;

[0024] Step 5, the antenna circuit chip monomer is attached to the chip area I on the dielectric layer II in a certain arrangement order, and the antenna circuit chip monomer is adhered to the dielectric layer II through an adhesive film or an adhesive; the chip electrode of the antenna circuit chip monomer faces upward;

[0025] Step 6: In a vacuum environment, an encapsulation layer is formed on the dielectric layer II by injection molding an encapsulation material or attaching an encapsulation film, and the encapsulation layer completely covers the antenna circuit chip monomer and the metal II at the bottom of the bump to form an encapsulation body protected by the encapsulation material;

[0026] Step 7: Thinning the upper surface of the encapsulation layer by physical grinding to expose the metal II at the bottom of the bump and the chip electrode of the antenna circuit chip monomer;

[0027] Step eight, using a photolithography process to set a dielectric layer III on the encapsulation layer and open an opening I in the dielectric layer III to expose the input / output end of the metal II at the bottom of the bump, the opening II in the dielectric layer III to expose the input / output end of the chip electrode of the antenna circuit chip monomer, and the opening III in the dielectric layer III to set a dicing road;

[0028] Step nine, depositing a metal seed layer III on the surface of the dielectric layer III by sputtering or chemical plating, and again using a rewiring process to form a discontinuous rewiring metal layer III, and corroding and removing the invalid metal seed layer III to form a bump bottom metal III, which includes a metal seed layer III and a rewiring metal layer III from bottom to top. The bump bottom metal III selectively connects the chip electrode of the antenna circuit chip monomer on the same side and the bump bottom metal II according to design requirements. The bump bottom metal III input / output terminal is provided on the outermost layer of the bump bottom metal III;

[0029] Step 10, using a photolithography process to set a dielectric layer IV on the metal III at the bottom of the bump and open an opening I in the dielectric layer IV to expose the input / output terminal of the metal III at the bottom of the bump, and set a scribe line in the opening II of the dielectric layer IV, which overlaps with the scribe line of the opening III of the dielectric layer III;

[0030] Step 11, setting a solder ball at the input / output end of the metal III at the bottom of the bump;

[0031] Step twelve, separating the dielectric layer I from the supporting substrate by laser irradiation;

[0032] Step thirteen: cutting the antenna circuit chip packaging structure completed by the wafer-level process along the scribe line to form a packaging unit covered by the packaging layer.

[0033] Optionally, the supporting substrate is one of a glass substrate, a metal substrate and a ceramic substrate.

[0034] Optionally, the separation layer is a polymer layer with a light-to-heat conversion function, and a slurry of the polymer layer is coated on the upper surface of the supporting substrate by a spin coating process, and then cured and formed by an ultraviolet curing or thermal curing process.

[0035] Beneficial Effects

[0036] 1. The present invention provides a chip packaging structure and a packaging method thereof, which improves the integration of antenna circuit boards and antenna efficiency, reduces the packaging area of ​​circuit boards, and reduces the power consumption of antenna packaging structures;

[0037] 2. The antenna circuit chip is completely covered by the packaging layer, which reduces the breakage and wear of the antenna circuit chip and improves the reliability of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A cross-sectional schematic diagram of a packaging structure of an existing antenna circuit chip;

[0039] Figure 2 A schematic diagram of the relationship between a bump bottom metal III, a chip electrode of an antenna circuit chip unit, and a bump bottom metal II of a chip packaging structure of the present invention;

[0040] Figure 3 for Figure 2 AA cross-sectional diagram of ;

[0041] Figures 4A-4N It is a schematic diagram of the process flow of the packaging method of the above embodiment of the present invention;

[0042] in:

[0043] Supporting substrate 100

[0044] Separation layer 210

[0045] Dielectric layer I310

[0046] Bump bottom metal layer I 410

[0047] Dielectric layer II 320

[0048] Bump bottom metal II 420

[0049] Antenna circuit chip 510

[0050] Chip electrode 430 of the antenna circuit chip unit

[0051] Adhesive film or adhesive 610

[0052] Encapsulation layer 710

[0053] Dielectric layer III330

[0054] Dielectric layer IV340

[0055] Bump bottom metal III 440

[0056] Solder ball 800. DETAILED DESCRIPTION

[0057] The specific implementation method of the present invention is described in detail below with reference to the accompanying drawings.

[0058] Example

[0059] The present invention provides a chip packaging structure, such as Figure 2 and Figure 3 As shown, Figure 3 for Figure 2 AA cross-section diagram of .

[0060] The packaging structure includes an antenna circuit chip 510, a dielectric layer I 310, a dielectric layer II 320, a dielectric layer III 330, a dielectric layer IV 340, a bottom bump metal layer I 410, a bottom bump metal II 420, a bottom bump metal III 440 and an encapsulation layer 710. The antenna circuit chip 510 includes active components and passive components, wherein the active components are power management circuits, transmitting circuits or receiving circuits, and the passive components are one or more of resistors, capacitors and inductors.

[0061] A plurality of chip electrodes 430 of the antenna circuit chip unit are disposed on the upper surface of the antenna circuit chip 510 . Figure 2 The chip electrodes 430 of a single antenna circuit chip with a 2*2 array are shown as an example.

[0062] A discontinuous bottom bump metal layer I410 is disposed on the upper surface of the dielectric layer I310. The dielectric layer I310 is made of a low-temperature cured polyimide resin or a high-temperature cured polymer material. The bottom bump metal layer I410 includes a metal seed layer I and a rewiring metal layer I in order from bottom to top (the metal seed layer I and the rewiring metal layer I are not shown in the figure).

[0063] The dielectric layer II 320 covers the bottom bump metal layer I 410, and a number of dielectric layer II openings I 321 are provided to expose a portion of the bottom bump metal layer I 410, forming the input / output terminal of the bottom bump metal layer I 410. In the figure, the input / output terminal of the bottom bump metal layer I 410 is only shown as one on each side. The actual packaged product can be provided with multiple input / output terminals of the bottom bump metal layer I 410 as required. The material of the bottom bump metal layer I 410 is preferably copper with good electrical conductivity. The material of the dielectric layer II 320 is a low-temperature cured polyimide resin, or a high-temperature cured polymer material.

[0064] The antenna circuit chip 510 is disposed in the central chip region I of the dielectric layer II 320 and is fixedly connected to the dielectric layer II 320 via an adhesive film or adhesive 610, with the chip electrode 430 of the antenna circuit chip facing upward. The thickness of the adhesive film or adhesive 610 is 10 microns to 100 microns.

[0065] The bottom bump metal II 420 provided at the input / output end of the bottom bump metal layer I 410 serves as an antenna, and the bottom bump metal II 420 includes a metal seed layer II and a rewiring metal layer II from bottom to top (the metal seed layer II and the rewiring metal layer II are not shown in the figure). The material of the bottom bump metal II 420 is preferably copper with good electrical conductivity. The cross-sectional shape of the bottom bump metal II 420 is not limited. Generally, the cross-sectional shape of the bottom bump metal II 420 is circular or rectangular.

[0066] The encapsulation material covers the dielectric layer II 320 and encapsulates the antenna circuit chip 510, the chip electrode 430 of the antenna circuit chip unit and the bottom bump metal II 420 to form an encapsulation layer 710. The material of the encapsulation layer 710 includes but is not limited to one of polyimide, silica gel and epoxy resin.

[0067] The upper surface of the encapsulation layer 710 is flush with the upper surface of the under bump metal II 420 and the upper surface of the chip electrode 430 of the antenna circuit chip unit.

[0068] The dielectric layer III 330 covers the upper surface of the encapsulation layer 710, and the dielectric layer III opening I 331 is opened to expose part of the bottom bump metal II 420, forming the input / output end of the bottom bump metal II 420, and the dielectric layer III opening II 332 exposes the chip electrode 430 of the antenna circuit chip monomer, forming the input / output end of the chip electrode 430 of the antenna circuit chip monomer. The dielectric layer III 330 is made of a low-temperature curing polyimide resin.

[0069] The surface of the dielectric layer III 330 is covered with a plurality of discontinuous bottom bump metals III 440, which include a metal seed layer III and a rewiring metal layer III from bottom to top (the metal seed layer III and the rewiring metal layer III are not shown in the figure), and an input / output terminal of the bottom bump metal III 440 is provided at the outermost layer of the bottom bump metal III 440; the bottom bump metal III 440 selectively connects the chip electrode 430 of the antenna circuit chip monomer on the same side and a plurality of bottom bump metals II 420, such as Figure 2 As shown, the chip electrode 430 of the antenna circuit chip unit is selectively connected to a bottom bump metal II 42 on the same side through the bottom bump metal III 440. The material of the bottom bump metal III 440 is preferably copper with good electrical conductivity.

[0070] The dielectric layer IV340 covers all the bottom metal of the bump III440, and the dielectric layer IV opening I341 is opened to expose part of the bottom metal of the bump III440, forming the input / output end of the bottom metal of the bump III440. The material of the dielectric layer IV340 is a low-temperature cured polyimide resin. Solder balls 800 are set at the input / output end of the bottom metal of the bump III440. The solder balls 800 are arranged in an array. A packaging structure is formed in which the bottom metal of the bump I410 with antenna function, the bottom metal of the bump II420 and the antenna circuit chip 510 are integrated in the package body to realize the system-level wireless function, reducing the area of ​​the circuit board occupied by the antenna and reducing the packaging area of ​​the circuit board. The encapsulation layer 710 completely covers the antenna circuit chip 510, reduces the fragmentation and wear of the antenna circuit chip 510, improves the reliability of the product, improves the integration performance of the antenna packaging structure and the antenna efficiency, and reduces the power consumption of the antenna packaging structure.

[0071] The packaging method of the chip packaging structure of the present invention comprises the following steps:

[0072] Step 1, see Figure 4A and Figure 4B A supporting substrate 100 is provided, and the supporting substrate 100 is one of a glass substrate, a metal substrate and a ceramic substrate. A separation layer 210 is provided on the upper surface of the supporting substrate 100, and a dielectric layer I 310 is provided on the upper surface of the separation layer 210 by using a photolithography process.

[0073] The separation layer 210 is a polymer layer with a photothermal conversion function. The slurry of the polymer layer is coated on the upper surface of the supporting substrate 100 by a spin coating process, and then cured and formed by an ultraviolet curing or thermal curing process. By irradiating the polymer layer with a laser, the dielectric layer I310 can be separated from the supporting substrate 100.

[0074] Step 2, see Figure 4C , a metal seed layer I is deposited on the upper surface of the dielectric layer I 310 by sputtering or chemical plating, and then a patterned rewiring metal layer I is formed by a rewiring process and the ineffective metal seed layer I is removed by etching to form a bump bottom metal layer I 410.

[0075] Step 3, see Figure 4D , and then using a photolithography process to cover the dielectric layer II 320 on the bottom bump metal layer I 410 and open the dielectric layer II opening I 321 to form the input / output terminal of the bottom bump metal layer I 410;

[0076] Step 4, see Figure 4E , then use sputtering or chemical plating to deposit a metal seed layer II on the upper surface of the dielectric layer II 320, and then use a rewiring process to form a patterned rewiring metal layer II, and then corrode and remove the invalid metal seed layer II to form a bump bottom metal II 420 and a chip area I, and the chip area I is in the center of the bump bottom metal II 420.

[0077] Step 5, see Figure 4F , the antenna circuit chip monomer is attached to the chip area I on the dielectric layer II 320 in a certain arrangement order, and the antenna circuit chip monomer is adhered to the dielectric layer II 320 through an adhesive film or adhesive 610; the chip electrode 430 of the antenna circuit chip monomer faces upward.

[0078] Step 6, see Figure 4G In a vacuum environment, an encapsulation layer 710 is formed on the dielectric layer II 320 by injection molding an encapsulation material or attaching an encapsulation film, and the encapsulation layer 710 completely covers the antenna circuit chip monomer and the bump bottom metal II 420 to form an encapsulation body protected by the encapsulation material;

[0079] Step 7, see Figure 4H , the upper surface of the encapsulation layer 710 is thinned by physical grinding to expose the bump bottom metal II 420 and the chip electrode 430 of the antenna circuit chip monomer;

[0080] Step 8, see Fig. 4I, and then using a photolithography process to set a dielectric layer III 330 on the encapsulation layer 710 and open a dielectric layer III opening I 331 to expose the input / output end of the bump bottom metal II 420, a dielectric layer III opening II 332 to expose the input / output end of the chip electrode 430 of the antenna circuit chip monomer, and a dielectric layer III opening III 333 to set a dicing road;

[0081] Step 9, see Figure 4J , a metal seed layer III is deposited on the surface of the dielectric layer III 330 by sputtering or chemical plating, a discontinuous rewiring metal layer III is formed by rewiring process, and the invalid metal seed layer III is removed by etching to form a bump bottom metal

[0082] The bottom bump metal III440 includes a metal seed layer III and a rewiring metal layer III from bottom to top. The bottom bump metal III440 selectively connects the chip electrode 430 of the antenna circuit chip monomer on the same side and the bottom bump metal II420 according to design requirements. The bottom bump metal III440 input / output terminal is provided at the outermost layer of the bottom bump metal III440.

[0083] Step 10, see Figure 4K , a dielectric layer IV 340 is disposed on the bump bottom metal III 440 by using a photolithography process again, and an opening I 341 of the dielectric layer IV is opened to expose the input / output terminal of the bump bottom metal III 440 , and a scribe line is disposed in the opening II 342 of the dielectric layer IV, and overlaps with the scribe line of the opening III 333 of the dielectric layer III;

[0084] Step 11, see Figure 4L , setting a solder ball 800 at the input / output end of the metal III 440 at the bottom of the bump;

[0085] Step 12, see Figure 4M , the dielectric layer I 310 is separated from the supporting substrate 100 by laser irradiation.

[0086] Step 13, see Figure 4N The antenna circuit chip packaging structure completed by the wafer-level process is cut along the scribe line to form a packaging unit covered by the encapsulation layer.

[0087] The specific implementation methods described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of protection of the present invention.

Claims

1. A chip packaging structure, characterized in that: It comprises an antenna circuit chip (510), a dielectric layer I (310), a dielectric layer II (320), a dielectric layer III (330), a dielectric layer IV (340), a bump bottom metal layer I (410), a bump bottom metal II (420), a bump bottom metal III (440) and an encapsulation layer (710); the upper surface of the antenna circuit chip (510) is provided with a plurality of chip electrodes (430) of the antenna circuit chip monomer; A discontinuous bump bottom metal layer I (410) is disposed on the upper surface of the dielectric layer I (310), the dielectric layer II (320) covers the bump bottom metal layer I (410), and a plurality of dielectric layer II openings I (321) are provided to expose a portion of the bump bottom metal layer I (410), thereby forming an input / output end of the bump bottom metal layer I (410), the bump bottom metal II (420) is disposed at the input / output end of the bump bottom metal layer I (410), and the bump bottom metal II (420) serves as an antenna; The antenna circuit chip (510) comprises an active component and a passive component, which is arranged in a chip region I in the center of the dielectric layer II (320) and is fixedly connected to the dielectric layer II (320) via an adhesive film or an adhesive (610), and the chip electrode (430) of the antenna circuit chip monomer faces upward; The encapsulation material covers the dielectric layer II (320) and encapsulates the antenna circuit chip (510), the chip electrode (430) of the antenna circuit chip unit and the bump bottom metal II (420), forming an encapsulation layer (710); The upper surface of the encapsulation layer (710) is flush with the upper surface of the metal II (420) at the bottom of the bump and the upper surface of the chip electrode (430) of the antenna circuit chip monomer; The dielectric layer III (330) covers the upper surface of the encapsulation layer (710), and has a dielectric layer III opening I (331) and a dielectric layer III opening II (332), wherein the dielectric layer III opening I (331) exposes a portion of the bump bottom metal II (420) to form an input / output end of the bump bottom metal II (420), and the dielectric layer III opening II (332) exposes the chip electrode (430) of the antenna circuit chip monomer to form an input / output end of the chip electrode (430) of the antenna circuit chip monomer; The surface of the dielectric layer III (330) is covered with a plurality of discontinuous bump bottom metals III (440), and the bump bottom metal III (440) is provided with an input / output terminal of the bump bottom metal III (440) on the outermost layer; the bump bottom metal III (440) selectively contacts and electrically connects the chip electrode (430) and the bump bottom metal II (420) of the antenna circuit chip monomer on the same side; The dielectric layer IV (340) covers all the bump bottom metal III (440), and an opening I (341) is formed in the dielectric layer IV to expose a portion of the bump bottom metal III (440), thereby forming an input / output terminal of the bump bottom metal III (440).

2. The packaging structure according to claim 1, characterized in that: The active component is a power management circuit, a transmitting circuit or a receiving circuit.

3. The packaging structure according to claim 1, characterized in that: The passive component is one or more of a resistor, a capacitor and an inductor.

4. The packaging structure according to claim 1, characterized in that: The bump bottom metal II (420) includes a metal seed layer II and a rewiring metal layer II in order from bottom to top.

5. The packaging structure according to claim 1 or 4, characterized in that: The cross-sectional shape of the bump bottom metal II (420) is circular or rectangular.

6. The packaging structure according to claim 1, characterized in that: The material of the encapsulation layer (710) includes any one of polyimide, silica gel and epoxy resin.

7. The packaging structure according to claim 1, characterized in that: A solder ball (800) is provided at the input / output end of the bump bottom metal III (440).

8. A packaging method for a chip packaging structure, characterized in that: The packaging method comprises the following steps: Step 1: providing a support substrate (100), providing a separation layer (210) on the upper surface of the support substrate (100), and providing a dielectric layer I (310) on the upper surface of the separation layer (210) using a photolithography process; Step 2, depositing a metal seed layer I on the upper surface of the dielectric layer I (310) by sputtering or chemical plating, and then forming a patterned rewiring metal layer I by a rewiring process and etching away the ineffective metal seed layer I to form a bump bottom metal layer I (410); Step 3, using a photolithography process to cover the dielectric layer II (320) on the bump bottom metal layer I (410) and to open an opening I (321) in the dielectric layer II to form an input / output terminal of the bump bottom metal layer I (410); Step 4: depositing a metal seed layer II on the upper surface of the dielectric layer II (320) by sputtering or chemical plating, and then forming a patterned rewiring metal layer II by a rewiring process, and removing the invalid metal seed layer II by etching to form a bump bottom metal II (420) and a chip region I, wherein the chip region I is located at the center of the bump bottom metal II (420), and the bump bottom metal II (420) serves as an antenna; Step 5, attaching the antenna circuit chip monomer to the chip area I on the dielectric layer II (320) in a certain arrangement order, and the antenna circuit chip monomer is adhered to the dielectric layer II (320) through an adhesive film or adhesive (610); the chip electrode (430) of the antenna circuit chip monomer faces upward; Step 6: In a vacuum environment, an encapsulation layer (710) is formed on the dielectric layer II (320) by injection molding an encapsulation material or attaching an encapsulation film, wherein the encapsulation layer (710) completely covers the antenna circuit chip monomer and the bump bottom metal II (420), forming an encapsulation body protected by the encapsulation material; Step 7, thinning the upper surface of the encapsulation layer (710) by physical grinding to expose the bump bottom metal II (420) and the chip electrode (430) of the antenna circuit chip unit; Step eight, using a photolithography process to set a dielectric layer III (330) on the encapsulation layer (710) and to open an opening I (331) in the dielectric layer III to expose the input / output end of the metal II (420) at the bottom of the bump, an opening II (332) in the dielectric layer III to expose the input / output end of the chip electrode (430) of the antenna circuit chip monomer, and an opening III (333) in the dielectric layer III to set a dicing path; Step nine, depositing a metal seed layer III on the surface of the dielectric layer III (330) by sputtering or chemical plating, and forming a discontinuous rewiring metal layer III by rewiring process, and removing the invalid metal seed layer III by etching to form a bump bottom metal III (440), wherein the bump bottom metal III (440) includes a metal seed layer III and a rewiring metal layer III from bottom to top, and the bump bottom metal III (440) selectively contacts and electrically connects the chip electrode (430) and the bump bottom metal II (420) of the antenna circuit chip monomer on the same side according to design requirements, and a bump bottom metal III (440) input / output terminal is provided on the outermost layer of the bump bottom metal III (440); Step 10, using a photolithography process to set a dielectric layer IV (340) on the bump bottom metal III (440) and open a dielectric layer IV opening I (341) to expose the bump bottom metal III (440) input / output terminal, and set a scribe line in the dielectric layer IV opening II (342) and overlap with the scribe line of the dielectric layer III opening III (333); Step 11, setting a solder ball (800) at the input / output end of the metal III (440) at the bottom of the bump; Step twelve, separating the dielectric layer I (310) from the supporting substrate (100) by laser irradiation; Step thirteen: cutting the antenna circuit chip packaging structure completed by the wafer-level process along the scribe line to form a packaging unit covered by the packaging layer.

9. The packaging method according to claim 8, characterized in that: The supporting substrate (100) is one of a glass substrate, a metal substrate and a ceramic substrate.

10. The packaging method according to claim 8, characterized in that: The separation layer (210) is a polymer layer having a light-to-heat conversion function. The slurry of the polymer layer is coated on the upper surface of the supporting substrate (100) by a spin coating process, and then cured and formed by an ultraviolet curing or thermal curing process.

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