Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device is provided, comprising at least one interconnect structure, including: a substrate, the substrate having an upper surface and a lower surface opposite to the upper surface; a first insulating dielectric layer located on the lower surface of the substrate; a second insulating dielectric layer located on the upper surface of the substrate; a first connection pad, arranged in the first insulating dielectric layer; a metal connector, penetrating a first portion of the first insulating dielectric layer, the substrate and a second portion of the second insulating dielectric layer to connect the first connection pad, a surrounding hole formed around the metal connector and penetrating the substrate; a lining dielectric layer, formed in the surrounding hole, the film thickness of the lining dielectric layer is less than half of the gap from the first surface to the second surface of the surrounding hole to form an air gap; a lining cover, formed on the lining dielectric layer to hermetically seal the air gap, the air gap surrounds the metal connector; and a second connection pad, arranged in the second insulating dielectric layer and located on the lining cover, the second connection pad connecting the metal connector.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a semiconductor device and a preparation method thereof. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher integration in order to achieve faster computing speeds, larger data storage capacity and more functions. The higher the integration of semiconductor chips, the smaller the feature size of semiconductor devices.

[0003] Three-dimensional integrated circuits are made using advanced chip stacking technology, which is to stack chips with different functions into integrated circuits with a three-dimensional structure. Compared with integrated circuits with a two-dimensional structure, the stacking technology of three-dimensional integrated circuits can not only shorten the signal transmission path of three-dimensional integrated circuits, but also speed up the operation of three-dimensional integrated circuits; in short, the stacking technology of three-dimensional integrated circuits has the following advantages: meeting the needs of semiconductor devices for higher performance, smaller size, lower power consumption and more functions.

[0004] To realize the stacking technology of three-dimensional integrated circuits, through silicon via technology (TSV: Trough Silicon Via) is a new generation of technology that enables stacked chips to be interconnected, and is one of the current hot key technologies. TSV technology makes the signal transmission path between chips in integrated circuits shorter, so the three-dimensional integrated circuits run faster, have lower parasitic effects and power consumption, are smaller in size and lighter in weight, and there is no limit on the number of stacked chips.

[0005] However, the semiconductor devices formed by the prior art have problems such as poor RC delay and poor reliability. Summary of the invention

[0006] In order to overcome the above defects, the present invention provides a semiconductor device and a method for preparing the same.

[0007] The present invention provides a semiconductor device, comprising at least one interconnect structure, the interconnect structure comprising: a substrate, the substrate having an upper surface and a lower surface opposite to the upper surface; a first insulating dielectric layer located on the lower surface of the substrate; a second insulating dielectric layer located on the upper surface of the substrate; a first connection pad, arranged in the first insulating dielectric layer; a metal connector, penetrating the second portion of the first insulating dielectric layer, the substrate and the first portion of the second insulating dielectric layer to connect the first connection pad, a surrounding hole formed around the metal connector, the surrounding hole at least exposing the first surface of the metal connector, the second surface and the bottom surface of the substrate; a lining dielectric layer, formed in the surrounding hole and covering the first surface, the second surface and the bottom surface, the film thickness of the lining dielectric layer is less than half of the gap from the first surface to the second surface of the surrounding hole to form an air gap; a lining cover, formed on the lining dielectric layer to hermetically seal the air gap, the air gap surrounds the metal connector; and a second connection pad, arranged in the second insulating dielectric layer and located on the lining cover, the second connection pad connecting the metal connector.

[0008] According to an embodiment of the present invention, the substrate includes one or more of silicon, germanium, silicon germanium, silicon carbide and gallium arsenide.

[0009] According to another embodiment of the present invention, the first insulating dielectric layer and the second insulating dielectric layer include one or more of silicon nitride, silicon dioxide and silicon oxynitride.

[0010] According to another embodiment of the present invention, the first connection pad, the metal connection member and the second connection pad include one or more of tungsten, copper, aluminum, silver, platinum and alloys thereof.

[0011] According to another embodiment of the present invention, the surrounding hole penetrates the second portion of the first insulating dielectric layer, the substrate, and the first portion of the second insulating dielectric layer.

[0012] According to another embodiment of the present invention, a vertical distance from the first surface to the second surface is 0.1-5 μm.

[0013] Another aspect of the present invention provides a method for preparing a semiconductor device, comprising: providing a semiconductor substrate, wherein a first insulating dielectric layer is disposed on the lower surface of the substrate, a first connection pad is disposed in the first insulating dielectric layer, and a second insulating dielectric layer is disposed on the upper surface of the substrate opposite to the lower surface; arranging a metal connector in the substrate, wherein the metal connector penetrates the second portion of the first insulating dielectric layer, the substrate, and the first portion of the second insulating dielectric layer to connect the first connection pad; forming a surrounding hole around the metal connector, wherein the surrounding hole at least exposes the first surface of the metal connector, exposes the second surface of the metal connector, and exposes the second surface of the metal connector. The second surface and bottom surface of the substrate; and forming an inner lining dielectric layer in the surrounding hole, the inner lining dielectric layer covers the first surface, the second surface and the bottom surface, and the film thickness of the inner lining dielectric layer is less than half of the gap from the first surface to the second surface of the surrounding hole to form an air gap; forming an inner lining cover on the inner lining dielectric layer to form an isolation member to hermetically seal the air gap, and the isolation member surrounds the metal connector; and arranging a second connecting pad in the second insulating dielectric layer, the second connecting pad is located on the inner lining cover, and the second connecting pad is connected to the metal connector.

[0014] According to one embodiment of the present invention, the provision of the metal connector includes: etching the first portion of the second insulating dielectric layer, the substrate and the second portion of the first insulating dielectric layer with a mask to form a hole exposing the surface of the first connection pad; and filling the hole with metal deposition to form the metal connector.

[0015] According to another embodiment of the present invention, the metal is deposited by sputtering or electroplating.

[0016] According to another embodiment of the present invention, the forming of the surrounding hole includes: etching the first portion of the second insulating dielectric layer, the substrate and the second portion of the first insulating dielectric layer with a mask to form a surrounding hole surrounding the metal connector, wherein the surrounding hole exposes the surface of the first connection pad.

[0017] According to another embodiment of the present invention, a vertical distance from the first surface to the second surface is 0.1-5 μm.

[0018] According to another embodiment of the present invention, the liner dielectric layer is formed by atomic layer deposition.

[0019] According to another embodiment of the present invention, the liner cap is formed by depositing an insulating dielectric material to encapsulate the first surface, the second surface and the bottom surface to form a liner dielectric layer around the upper end of the hole.

[0020] According to another embodiment of the present invention, the liner cap is formed by plasma enhanced vapor deposition of the insulating dielectric material.

[0021] According to another embodiment of the present invention, the isolation member includes one or more of silicon nitride, silicon dioxide and silicon oxynitride.

[0022] Another aspect of the present invention provides a method for preparing a semiconductor device, comprising: providing a semiconductor substrate, a first insulating dielectric layer being arranged on the lower surface of the substrate, a first connection pad being arranged in the first insulating dielectric layer, and a second insulating dielectric layer being arranged on the upper surface of the substrate opposite to the lower surface; arranging a metal connector in the substrate, the metal connector penetrating the second portion of the first insulating dielectric layer, the substrate and the first portion of the second insulating dielectric layer to connect the first connection pad; forming a surrounding hole around the metal connector, the surrounding hole at least exposing the first surface of the metal connector, the second surface of the substrate and the bottom surface; and forming a dielectric layer in the surrounding hole, which has covered the first surface, the second surface and the bottom surface, and continues to grow the dielectric layer to seal the surrounding hole to form an isolation member encapsulated with an air gap inside, the isolation member surrounding the metal connector; and arranging a second connection pad in the second insulating dielectric layer, the second connection pad being located on the liner cover, the second connection pad connecting the metal connector.

[0023] The interconnect structure of the semiconductor device includes an air gap, which can effectively reduce the parasitic capacitance in the semiconductor device, reduce the RC delay effect, and improve the operating speed and reliability of the semiconductor device. In addition, the air gap in the semiconductor device prepared by the method of the present invention is uniform, which improves the reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

[0025] Figure 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0026] Figures 2A to 2M is a schematic cross-sectional view illustrating a process of manufacturing a semiconductor device according to an embodiment of the present invention.

[0027] Figures 3A to 3K is a schematic cross-sectional view illustrating a process of manufacturing a semiconductor device according to another embodiment of the present invention.

[0028] Figures 4A to 4J is a schematic cross-sectional view illustrating a process of manufacturing a semiconductor device according to still another embodiment of the present invention.

[0029] The reference numerals are described as follows:

[0030] 1: Substrate

[0031] 21: First insulating dielectric layer

[0032] 211: The first part of the first insulating dielectric layer

[0033] 212: The second part of the first insulating dielectric layer

[0034] 22: Second insulating dielectric layer

[0035] 221: The first part of the second insulating dielectric layer

[0036] 222: The second part of the second insulating dielectric layer

[0037] 223: The third insulating dielectric layer

[0038] 224: Dielectric layer

[0039] 23: Groove

[0040] 3: Metal conductor

[0041] 31: First connection pad

[0042] 32: Metal connectors

[0043] 33: Second connection pad

[0044] 4: Isolation parts

[0045] 41: Lining dielectric layer

[0046] 42: Liner cover

[0047] 5: Air gap

[0048] 61: First mask layer

[0049] 62: Second mask layer

[0050] 71: Through hole

[0051] 72: Surround hole

[0052] 721: First Surface

[0053] 722: Second Surface

[0054] 723: Bottom DETAILED DESCRIPTION

[0055] The term "semiconductor device" herein generally refers to a solid-state device comprising one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, and diodes, among others. In addition, the term "semiconductor device" may refer to a finished device or to an assembly or other structure at various processing stages before becoming a finished device. Depending on the context in which the term "substrate" is used, the term may refer to a wafer-level substrate or to a singulated die-level substrate. Those skilled in the relevant art will recognize that suitable steps of the methods described herein may be performed at the wafer level or at the die level. In addition, unless otherwise indicated by the context, the structures disclosed herein may be formed using conventional semiconductor manufacturing techniques. The material may be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, and / or other suitable techniques. Similarly, the material may be removed, for example, using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques.

[0056] The terms "upper" and "lower" in this article are only relative concepts or references to the normal use of the product, and should not be considered restrictive. "First", "second", "third" and other similar terms do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0057] First, if Figure 1 As shown, the semiconductor device includes at least one interconnection structure, and two interconnection structures are used as examples to explain the concept of the present invention. The interconnection structure includes a substrate 1, a first insulating dielectric layer 21, a second insulating dielectric layer 22, a metal conductor 3 and an isolation member 4. The first insulating dielectric layer 21 and the second insulating dielectric layer 22 are respectively stacked on two opposite surfaces of the substrate 1. The metal conductor 3 includes a first connection pad 31 arranged in the first insulating dielectric layer 21, a second connection pad 33 arranged in the second insulating dielectric layer 22, and a metal connector 32 that penetrates the substrate 1 and connects the first connection pad 31 and the second connection pad 33. The isolation member 4 is formed of an insulating dielectric material, surrounds the metal connector 32, and an air gap 5 is sealed in the isolation member 4. The semiconductor device can also be combined with other layers, for example but not limited to being stacked on another substrate 1.

[0058] The substrate 1 may be any suitable semiconductor material, such as silicon, germanium, silicon germanium, silicon carbide, and gallium arsenide.

[0059] The first insulating dielectric layer 21 and the second insulating dielectric layer 22 may be, but are not limited to, SiO 2 , SiN, SiON, etc. The first insulating dielectric layer 21 may include a first portion 211 and a second portion 212 stacked.

[0060] The first connection pad 31 of the metal conductor 3 is arranged between the first part 211 and the second part 212 of the first insulating dielectric layer 21. The second connection pad 33 is arranged in the second insulating dielectric layer 22. The metal connector 32 penetrates the substrate 1 to connect the first connection pad 31 and the second connection pad 33. The metal of the metal conductor 3 can be selected from tungsten, copper, aluminum, silver, platinum or their alloys. The first connection pad 31, the metal connector 32 and the second connection pad 33 can be the same metal or different metals.

[0061] The isolation member 4 is formed of an insulating dielectric material, such as SiO 2 , SiN, SiON, etc.

[0062] The interconnect structure of the semiconductor device includes an air gap, which can effectively reduce the parasitic capacitance in the semiconductor device, reduce the RC delay effect, and improve the operating speed and reliability of the semiconductor device.

[0063] The semiconductor device of the present invention can be formed in various ways, for example Figures 2A to 2M As shown in the figure. Figure 2A As shown, a patterned first mask layer 61 is formed on the surface of the first portion 221 of the second insulating dielectric layer of the stacked structure including the first portion 221 of the second insulating dielectric layer, the substrate 1 and the first insulating dielectric layer 22 including the first connection pad 31. The first mask layer 61 may be a photoresist layer.

[0064] like Figure 2B As shown, the first portion 221 of the second insulating dielectric layer, the substrate 1 and the first insulating dielectric layer 21 are etched using the first mask layer 61 as a mask to form a through hole 71 exposing the first connection pad 31. The exposed first connection pad 31 may be a surface exposed or a portion of the first connection pad 31 may be etched. The figure shows a case of etching a portion, but this is not limited to this. Those skilled in the art may make a reasonable choice according to actual process conditions. After forming the through hole 71, the first mask layer 61 is removed.

[0065] Afterwards, the metal is filled into the through hole 71. Figure 2C As shown, metal such as Cu is filled into the through hole 71 by sputtering or electroplating, and the surface of the first part 221 of the second insulating dielectric layer is also covered with a metal layer. Then, for example, the metal layer covering the surface of the first part 221 of the second insulating dielectric layer is removed by chemical mechanical polishing (CMP), exposing the surface of the first part 221 of the second insulating dielectric layer (such as Figure 2D The metal filled in the through hole 71 forms the metal connector 32 of the metal conductor 3. The metal connector 32 is connected to the first connection pad 31.

[0066] Then, if Figure 2EAs shown, a patterned second mask layer 62 is formed on the surface of the first portion 221 of the second insulating dielectric layer. The second mask layer 62 may also be a photoresist layer.

[0067] like Figure 2F As shown, the first portion 221 of the second insulating dielectric layer, the substrate 1 and the first insulating dielectric layer 21 are etched with the second mask layer 62 as a mask to form a surrounding hole 72 surrounding the metal connector 32, and the surrounding hole 72 exposes the surface of the first connection pad 31. The surrounding hole 72 exposes the outer surface of the metal connector 32, that is, the first surface 721. The surrounding hole 72 exposes the side wall that penetrates the second portion 212 of the first insulating dielectric layer, the substrate 1 and the first portion 221 of the second insulating dielectric layer, that is, the second surface 722. The surface of the first connection pad 31 and / or the surface of the first insulating dielectric layer exposed at the bottom of the surrounding hole 72 is called the bottom surface 723. The cross-section of the surrounding hole 72 can be circular, polygonal, etc. The cross-section of the metal connector 32 can be circular, polygonal, etc. The vertical distance from the first surface 721 of the metal connector 32 to the second surface 722 of the substrate can be 0.1-5μm.

[0068] like Figure 2G As shown, a liner dielectric layer 41 is formed to cover the first surface 721, the second surface 722 and the bottom surface 723. The liner dielectric layer 41 may be SiN or the like, and may be formed by atomic layer deposition or the like.

[0069] Afterwards, the sealing surrounding hole 72 forms an isolating member 4 surrounding the metal connector 32, and an air gap 5 is encapsulated in the isolating member 4. The surface of the isolating member 4 is flush with the surface of the first portion 221 of the second insulating dielectric layer and the surface of the metal connector 32. Figure 2H As shown, an insulating dielectric material is first deposited on the surface of the first part 221 of the second insulating dielectric layer by plasma enhanced gas phase to form a third insulating dielectric layer 223, wherein the upper end of the surrounding hole 72 is filled with an insulating dielectric material. Then, the insulating dielectric material whose height exceeds the surface of the first part 221 of the first insulating dielectric layer can be removed by chemical mechanical polishing to expose the surface of the first part 221 of the second insulating dielectric layer and the metal connector 32. The lining cover 42 formed by the insulating dielectric material filled at the upper end of the surrounding hole 72 seals the surrounding hole 72 on which the lining dielectric layer 41 is deposited on the first surface 721, the second surface 722 and the bottom surface 723 to form an isolation member 4 including an air gap 5. The third insulating dielectric layer 223 can be formed of the same or different material as the lining dielectric layer 41. The same material is used as an example in the figure, but it is not intended to be limited to the same material. The surface of the isolation member 4 is flush with the surface of the first part 211 of the first insulating dielectric layer and the surface of the metal connector 32 (such as Fig.2I shown).

[0070] like Figure 2J As shown, the second part 222 of the second insulating dielectric layer is deposited on the upper surface of the first part 221 of the second insulating dielectric layer, the metal connector 32 and the isolation member 4 to cover the surface of the first part 221 of the second insulating dielectric layer, the surface of the isolation member 4 and the surface of the metal connector 32. The second part 222 of the second insulating dielectric layer can be formed of the same material as the first part 221 of the second insulating dielectric layer, or can be formed of a different material.

[0071] like Figure 2K As shown, a groove 23 is formed on the second portion 222 of the second insulating dielectric layer to expose the surface of the isolation member 4 and the surface of the metal connection member 32 .

[0072] Finally, metal is filled into the groove 23 to form a second connection pad 33. The second connection pad 33 is connected to the metal connection member 32. The second connection pad 33, the metal connection member 32 and the first connection pad 31 constitute a metal conductor 3. Figure 2L As shown, the metal is filled into the groove 23, and the groove 23 may be filled with a metal such as Cu by sputtering or electroplating, and the surface of the second portion 212 of the first insulating dielectric layer is also covered with a metal layer. Then, for example, the metal layer covering the surface of the second portion 222 of the second insulating dielectric layer is removed by chemical mechanical polishing, exposing the second portion 222 of the second insulating dielectric layer and the surface of the first connection pad 31 (as shown in FIG. Figure 2M The first part 221 of the second insulating dielectric layer and the second part 222 of the second insulating dielectric layer constitute the second insulating dielectric layer 22 of the semiconductor device (as shown in FIG. Figure 1 shown).

[0073] Figures 3A-3K FIG. 2 shows a process of forming a semiconductor device of the present invention in another embodiment of the present invention. Figures 3A-3H The process shown is similar to Figures 2A-2H The process shown is the same and will not be repeated here.

[0074] like Fig. 3I As shown, a portion of the third insulating dielectric layer 223 and the liner dielectric layer 41 are removed by etching or other means to form a groove 23 to expose the surface of the isolation member 4 and the surface of the metal connector 32 .

[0075] Finally, metal is filled into the groove 23 to form a second connection pad 33. The second connection pad 33 is connected to the metal connector 32. The first connection pad 31, the metal connector 32 and the second connection pad 33 constitute the metal conductor 3. The method of filling the metal into the groove 23 can be as follows: Figure 3JAs shown, the groove 23 is filled with a metal such as Cu by sputtering or electroplating, and the surface of the third insulating dielectric layer 223 is also covered with a metal layer. Then, for example, the metal layer covering the surface of the third insulating dielectric layer 223 is removed by chemical mechanical polishing to expose the surface of the third insulating dielectric layer 223 and the second connection pad 33 (as shown in FIG. Figure 3K The third insulating dielectric layer 223, the liner dielectric layer 41 and the first portion 221 of the second insulating dielectric layer constitute the second insulating dielectric layer 22 of the semiconductor device (as shown in FIG. Figure 1 shown).

[0076] Figures 4A-4J FIG. 2 shows a process of forming a semiconductor device of the present invention in another embodiment of the present invention. Figures 4A-4F The process shown is similar to Figures 2A-2F The process shown is the same and will not be repeated here.

[0077] like Figure 4G As shown, a dielectric layer 224 is formed to cover the first surface 721, the second surface 722 and the bottom surface 723. The lining dielectric layer 224 can be SiN or the like, and the dielectric layer 224 can be formed by atomic layer deposition or the like. Afterwards, the surrounding hole 72 with the dielectric layer is formed by continuing to grow to seal the first surface 721, the second surface 722 and the bottom surface 723. The insulating dielectric material filled at the upper end of the surrounding hole 72 forms a lining cap 42 to form an isolation member 4, and an air gap 5 is formed inside the isolation member 4.

[0078] like Figure 4H As shown, a portion of the dielectric layer 224 is removed by etching or other means to form a groove 23 to expose the surface of the isolation member 4 and the surface of the metal connection member 32 .

[0079] Finally, metal is filled into the groove 23 to form a second connection pad 33. The second connection pad 33 is connected to the metal connector 32. The first connection pad 31, the metal connector 32 and the second connection pad 33 constitute the metal conductor 3. The method of filling the metal into the groove 23 can be as follows: Fig. 4I As shown, the groove 23 is filled with a metal such as Cu by sputtering or electroplating, and the surface of the dielectric layer 224 is also covered with a metal layer. Then, for example, the metal layer covering the surface of the dielectric layer 224 is removed by chemical mechanical polishing to expose the surface of the dielectric layer 224 and the second connection pad 33 (as shown in FIG. Figure 4J The dielectric layer 224 and the first portion 221 of the second insulating dielectric layer form the second insulating dielectric layer 22 of the semiconductor device (as shown in FIG. Figure 1 shown).

[0080] The air gap in the semiconductor device prepared by the method of the present invention is uniform, thereby improving the reliability of the semiconductor device.

[0081] Of course, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A semiconductor device comprising at least one interconnect structure, characterized in that: The interconnect structure comprises: a substrate having an upper surface and a lower surface opposite to the upper surface; a first insulating dielectric layer located on the lower surface of the substrate; a second insulating dielectric layer located on the upper surface of the substrate; A first connection pad, disposed in the first insulating medium layer; a metal connector, penetrating the second portion of the first insulating dielectric layer, the substrate, and the first portion of the second insulating dielectric layer to connect the first connection pad, wherein a surrounding hole is formed around the metal connector, and the surrounding hole at least exposes the first surface of the metal connector and the second surface and bottom surface of the substrate; a lining dielectric layer formed in the surrounding hole and covering the first surface, the second surface and the bottom surface, wherein a film thickness of the lining dielectric layer is less than half of a gap from the first surface to the second surface of the surrounding hole to form an air gap; a liner cover formed on the liner dielectric layer to hermetically seal the air gap, the air gap surrounding the metal connector; and The second connection pad is arranged in the second insulating medium layer and located on the liner cover, and the second connection pad is connected to the metal connector.

2. The semiconductor device according to claim 1, wherein: The substrate includes one or more of silicon, germanium, silicon germanium, silicon carbide and gallium arsenide.

3. The semiconductor device according to claim 1, wherein: The first insulating dielectric layer and the second insulating dielectric layer include one or more of silicon nitride, silicon dioxide and silicon oxynitride.

4. The semiconductor device according to claim 1, wherein: The first connection pad, the metal connection piece and the second connection pad include one or more of tungsten, copper, aluminum, silver, platinum and alloys thereof.

5. The semiconductor device according to claim 1, wherein: The surrounding hole penetrates the second portion of the first insulating dielectric layer, the substrate, and the first portion of the second insulating dielectric layer.

6. The semiconductor device according to claim 1, wherein: The vertical distance from the first surface to the second surface is 0.1-5 μm.

7. A method for preparing a semiconductor device, characterized in that: include: Providing a semiconductor substrate, wherein a first insulating dielectric layer is disposed on a lower surface of the substrate, a first connection pad is disposed in the first insulating dielectric layer, and a second insulating dielectric layer is disposed on an upper surface of the substrate opposite to the lower surface; Disposing a metal connector in the substrate, wherein the metal connector penetrates the second portion of the first insulating dielectric layer, the substrate, and the first portion of the second insulating dielectric layer to connect the first connection pad; Forming a surrounding hole around the metal connector, wherein the surrounding hole at least exposes the first surface of the metal connector and exposes the second surface and the bottom surface of the substrate; as well as forming a lining dielectric layer in the surrounding hole, the lining dielectric layer covering the first surface, the second surface and the bottom surface, and the film thickness of the lining dielectric layer being less than half of the gap from the first surface to the second surface of the surrounding hole, so as to form an air gap; forming a liner cover on the liner dielectric layer to hermetically seal the air gap to form an isolator, wherein the isolator surrounds the metal connector; as well as A second connection pad is disposed in the second insulating medium layer, the second connection pad is located on the liner cover, and the second connection pad is connected to the metal connector.

8. The method according to claim 7, characterized in that The metal connector is provided including: Etching the first portion of the second insulating dielectric layer, the substrate, and the second portion of the first insulating dielectric layer using a mask to form a hole exposing a surface of the first connection pad; The metal connector is formed by depositing metal to fill the hole.

9. The method according to claim 8, characterized in that The metal is deposited by sputtering or electroplating.

10. The method according to claim 7, characterized in that The forming of the surrounding hole comprises: etching the first part of the second insulating dielectric layer, the substrate and the second part of the first insulating dielectric layer with a mask to form a surrounding hole surrounding the metal connector, wherein the surrounding hole exposes the surface of the first connection pad.

11. The method according to claim 7, characterized in that The vertical distance from the first surface to the second surface is 0.1-5 μm.

12. The method according to claim 7, characterized in that The liner dielectric layer is formed by atomic layer deposition.

13. The method according to claim 7, characterized in that The liner cap is formed by depositing an insulating dielectric material to encapsulate the first surface, the second surface and the bottom surface to form a liner dielectric layer around the upper end of the hole.

14. The method according to claim 13, characterized in that The liner cap is formed by plasma enhanced vapor deposition of the insulating dielectric material.

15. The method according to claim 7, characterized in that The isolation member includes one or more of silicon nitride, silicon dioxide and silicon oxynitride.

16. A method for preparing a semiconductor device, characterized in that: include: Providing a semiconductor substrate, wherein a first insulating dielectric layer is disposed on a lower surface of the substrate, a first connection pad is disposed in the first insulating dielectric layer, and a second insulating dielectric layer is disposed on an upper surface of the substrate opposite to the lower surface; Disposing a metal connector in the substrate, wherein the metal connector penetrates the second portion of the first insulating dielectric layer, the substrate, and the first portion of the second insulating dielectric layer to connect the first connection pad; Forming a surrounding hole around the metal connector, wherein the surrounding hole at least exposes the first surface of the metal connector and exposes the second surface and the bottom surface of the substrate; as well as forming a dielectric layer in the surrounding hole to cover the first surface, the second surface and the bottom surface, and continuing to grow the dielectric layer to seal the surrounding hole to form an isolation member encapsulating an air gap therein, wherein the isolation member surrounds the metal connector; and A second connection pad is disposed in the second insulating medium layer, the second connection pad is located on the liner cover, and the second connection pad is connected to the metal connector.

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