Matrix multiplexer output circuit based on single chip microcomputer control

Abstract

The present invention discloses a matrix type multiplexer output circuit based on single chip control, which includes the BJT logic XOR circuit for realizing single control dual output temperature or mode selection, the parallel resistor arrangement circuit for realizing multiple temperature or mode resistor value layout, the MOSFET cycle scanning circuit for realizing cycle scanning matrix output, and the ADC detection circuit for improving household appliances for various environmental data collection and intelligent control. The present invention is based on the BJT logic XOR circuit to realize the dual output type selection of single I / O control, reducing the single chip IO port control resources of dual output; based on the parallel resistor arrangement circuit, multiple temperature or mode resistor value layout is realized, based on the MOSFET cycle scanning circuit, a cycle scanning matrix output selection circuit is realized, and a shared cycle scanning ADC detection circuit is used to reduce the single chip ADC port required data, the circuit has a long working life, high precision, and stable output electrical signals.

Description

Technical Field

[0001] The present invention belongs to the technical field of kitchen appliance electric control panels, and in particular relates to a matrix type multiplexer output circuit based on single chip microcomputer control. Background Art

[0002] The widespread application of multi-channel temperature control / mode sensor resistors in household appliances in the market has greatly improved the collection and intelligent control of various environmental data for household appliances. The application of matrix multi-channel selection output circuits generally adopts the following methods:

[0003] 1. Use a dedicated multiplexer output chip similar to 74LS153, but it has the disadvantages of high chip cost, few matrix arrangement output types, and the need to occupy too many ADC port resources of the microcontroller.

[0004] 2. A matrix output circuit similar to a mechanical button is used, but it has the disadvantages of high button cost, short mechanical life, low reliability, and its detection signal is limited by mechanical contact, resulting in large jitter of the microcontroller ADC electrical signal.

[0005] In the past, R&D personnel or enterprises ignored the innovative improvement of this part of the application due to sticking to the old ways and the limitation of technology improvement, which directly led to the objective phenomena such as low product reliability, high development process cost and declining brand quality. Summary of the invention

[0006] In order to solve the above problems, the present invention provides a matrix multiplexer output circuit based on single chip control, which provides a low-cost, low-resource and optimal performance conversion medium circuit for the resistance values ​​of multiple temperature control / mode sensors by sharing a high-precision ADC detection port.

[0007] The technical solution adopted by the present invention is:

[0008] A matrix multiplexer output circuit based on single-chip microcomputer control comprises a BJT logic XOR circuit, a parallel resistor arrangement circuit, a MOSFET cyclic scanning circuit and a cyclic scanning ADC detection circuit connected in sequence, wherein the BJT logic XOR circuit is used to realize a single-control dual-output temperature or mode selection circuit, the parallel resistor arrangement circuit is used to realize a resistor value layout of multiple temperatures or modes, the MOSFET cyclic scanning circuit is used to realize a cyclic scanning matrix output, and the cyclic scanning ADC detection circuit is used to enhance the ability of household appliances to collect and intelligently control various types of environmental data.

[0009] Preferably, the temperature or mode selection in the logical XOR circuit of the BJT is a temperature selection resistor detection output or a mode selection resistor detection output, respectively.

[0010] Preferably, the multiple temperatures or modes of the parallel resistor arrangement circuit are respectively multiple temperatures or multiple mode signals detected by a temperature sensor.

[0011] Preferably, the BJT logic XOR circuit includes a first transistor switch QB1, a second transistor switch QB2, and a third transistor switch QB3, the input terminal RD_BIN_NTC signal is connected to the base of the first transistor switch QB1 and the base of the third transistor switch QB3, the emitter of the first transistor switch QB1 is connected to the emitter of the second transistor switch QB2 and the emitter of the third transistor switch QB3 and connected in parallel to the power supply VDD-UC, and the collector of the first transistor switch QB1 is connected in series with a resistor R_RD_NTC and a capacitor C8 and then outputs a signal RD_NTC;

[0012] The collector of the third transistor switch QB3 is connected to the base of the second transistor switch QB2 and connected in series with a resistor R7 and then grounded; the collector of the second transistor switch QB2 is connected in series with a resistor R_RD_BIN and in parallel with a resistor C7 and then outputs a signal RD_BIN.

[0013] Preferably, the circuit structure of the first transistor switch QB1 is the same as the circuit structure of the second transistor switch QB2 and the circuit structure of the third transistor switch QB3. The circuit structure of the first transistor switch QB1 includes a transistor QB, a resistor RA and a resistor RB. The emitter of the transistor QB is connected in series with the resistor RB and then connected to the base of the transistor QB. The base of the transistor QB is connected in series with the resistor RA.

[0014] Preferably, the parallel resistor arrangement circuit includes parallel resistors R_NTC1~R_NTCn and parallel resistors R_BIN1~R_BINn, the resistor R_BIN1 is connected in series with the first diode D1, the resistor R_NTC1 is connected in series with the n+1th diode Dn+1, and then the signals BIN_NTC_1 are output in parallel, the resistor R_BINn is connected in series with the nth diode Dn, the resistor R_NTCn is connected in series with the 2nth diode D2n, and then the signals BIN_NTC_n are output in parallel, where n∈N*, n≥2.

[0015] Preferably, the cyclic scanning circuit of the MOSFET includes a first saturated conduction switch Q1 to an nth saturated conduction switch Qn, the drain of the first saturated conduction switch Q1 is connected in parallel with a capacitor C2, and a single-chip drive signal IO_BIN_NTC_1 is connected in parallel with a resistor R1 and then connected to the gate of the first saturated conduction switch Q1, and the resistor R1 is grounded; the drain of the nth saturated conduction switch Qn is connected in parallel with a capacitor Cn+1, and a single-chip drive signal IO_BIN_NTC_n is connected in parallel with a resistor Rn and then connected to the gate of the nth saturated conduction switch Qn, and the resistor Rn is grounded.

[0016] Preferably, the first saturated conduction switch Q1 to the nth saturated conduction switch Qn are all MOSFET field effect transistors.

[0017] Preferably, the cyclic scanning ADC detection circuit includes a resistor RS_MUX, a capacitor C1 and a resistor RP_MUX, the resistor RP_MUX and the resistor RS_MUX are connected in parallel to the source of the first saturated conduction switch Q1 to the source of the nth saturated conduction switch Qn, the other end of the resistor RS_MUX is connected in parallel with the capacitor C1 to output the signal AD_BIN_NTC_1to n, and the other end of the capacitor C1 is grounded.

[0018] Preferably, the input terminal RD_BIN_NTC signal is a single IO control signal output by a single chip microcomputer.

[0019] Compared with the prior art, the present invention abandons the dedicated multi-channel selection output chip circuit, reduces the hardware cost in the design process, abandons the mechanical button-type matrix output circuit, reduces the jitter of the single-chip microcomputer ADC electrical signal, realizes a dual-output type selection circuit controlled by a single I / O based on the BJT logical XOR circuit, reduces the single-chip microcomputer IO port control resources of the dual-channel output, and expands the MOSFET cycle scanning circuit by 2 times; based on the combined parallel resistor arrangement circuit, realizes a variety of temperature or mode resistor value layouts, and greatly improves the ability of household appliances to utilize various types of environmental data collection and intelligent control; based on the MOSFET cycle scanning circuit, realizes a cycle scanning matrix output selection circuit, shares a common cycle scanning ADC detection circuit, reduces the single-chip microcomputer ADC port required data, and the circuit has a long working life, high precision, and stable output electrical signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The circuit diagram of a matrix multiplexer output circuit based on single chip microcomputer control provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0022] Embodiment 1 of the present invention provides a matrix multiplexer output circuit based on single chip microcomputer control, such as Figure 1As shown, it includes a BJT logic XOR circuit 1, a parallel resistor arrangement circuit 2, a MOSFET cyclic scanning circuit 3 and a cyclic scanning ADC detection circuit 4 connected in sequence, wherein the BJT logic XOR circuit 1 is used to realize temperature or mode selection of single control dual output, the parallel resistor arrangement circuit 2 is used to realize the resistance value layout of multiple temperatures or modes, the MOSFET cyclic scanning circuit 3 is used to realize cyclic scanning matrix output, and the cyclic scanning ADC detection circuit 4 is used to enhance the ability of household appliances to collect and intelligently control various environmental data.

[0023] In this way, by adopting the above structure, the present invention realizes a dual output type selection circuit controlled by a single I / O based on a BJT logical XOR circuit, thereby reducing the IO port control resources of a single-chip microcomputer with dual outputs; based on a parallel resistor arrangement circuit, a layout of resistor values ​​of various temperatures or modes is realized; based on a MOSFET cyclic scanning circuit, a cyclic scanning matrix output selection circuit is realized; a shared cyclic scanning ADC detection circuit is used to reduce the data required for the ADC port of the single-chip microcomputer, with high accuracy and stable output electrical signals.

[0024] The BJT logic XOR circuit 1 includes a first transistor switch QB1, a second transistor switch QB2, and a third transistor switch QB3, the input terminal RD_BIN_NTC signal is connected to the base of the first transistor switch QB1 and the base of the third transistor switch QB3, the emitter of the first transistor switch QB1 is connected to the emitter of the second transistor switch QB2 and the emitter of the third transistor switch QB3 and connected to the power supply VDD-UC, the collector of the first transistor switch QB1 is connected in series with a resistor R_RD_NTC and a capacitor C8 in parallel, and then outputs a signal RD_NTC;

[0025] The collector of the third transistor switch QB3 is connected to the base of the second transistor switch QB2, and is connected in series with a resistor R7 and then grounded; the collector of the second transistor switch QB2 is connected in series with a resistor R_RD_BIN and a parallel resistor C7 and then outputs a signal RD_BIN. The temperature or mode selection in the BJT logic XOR circuit 1 is a temperature selection resistor detection output or a mode selection resistor detection output. The input terminal RD_BIN_NTC signal is a single IO control signal output by the single chip microcomputer.

[0026] The circuit structure of the first transistor switch QB1 is the same as the circuit structure of the second transistor switch QB2 and the circuit structure of the third transistor switch QB3. The circuit structure of the first transistor switch QB1 includes a transistor QB, a resistor RA and a resistor RB. The emitter of the transistor QB is connected in series with the resistor RB and then connected to the base of the transistor QB. The base of the transistor QB is connected in series with the resistor RA.

[0027] Among them, R_RD_NTC / R_RD_BIN are the loop current limiting resistors for temperature selection or mode selection respectively; R7 is the bias resistor; RD_BIN or RD_NTC is the output signal of the selection circuit; thus, the dual-channel RD_BIN / RD_NTC XOR output controlled by the single-channel RD_BIN_NTC is obtained. Its working process is as follows:

[0028] When RD_BIN_NTC is high, the resistor sense output is selected for mode:

[0029] The first transistor switch QB1 or the third transistor switch QB3 is turned off; due to the effect of the bias resistor R7, the second transistor switch QB2 is saturated and turned on; at this time, the loop output signal RD_BIN of the mode selection is a high level VRD_BIN≈VDD_UC. R_RD_BIN is a current limiting resistor to prevent the failure of R_BIN1~R_BINn of the parallel resistor arrangement circuit, over-temperature (resistance value decreases to 0), etc., thereby protecting the normal operation of the circuit and preventing the second transistor switch QB2 from being damaged by over-current.

[0030] When RD_BIN_NTC is low, the resistor sense output is selected for temperature:

[0031] The first transistor switch QB1 or the third transistor switch QB3 is saturated and turned on; the second transistor switch QB2 is turned off; at this time, the temperature selection loop output signal RD_NTC is a high level VRD_NTC≈VDD_UC. R_RD_NTC is a current limiting resistor to prevent the failure of R_NTC1~R_NTCn of the parallel resistor arrangement circuit, over-temperature (resistance value decreases to 0), etc., thereby protecting the normal operation of the circuit and preventing the first transistor switch QB1 from being damaged by over-current.

[0032] Its truth table is as follows:

[0033] RD_BIN_NTC RD_BIN RD_NTC 1 1 0 0 0 1

[0034] The parallel resistor arrangement circuit 2 includes parallel resistors R_NTC1 to R_NTCn and parallel resistors R_BIN1 to R_BINn, wherein the resistor R_BIN1 is connected in series with the first diode D1, the resistor R_NTC1 is connected in series with the n+1th diode Dn+1, and then the signals BIN_NTC_1 are output in parallel, and the resistor R_BINn is connected in series with the nth diode Dn, the resistor R_NTCn is connected in series with the 2nth diode D2n, and then the signals BIN_NTC_n are output in parallel, wherein n∈N*, n≥2. The various temperatures or modes of the parallel resistor arrangement circuit 2 are the various temperatures or various mode signals detected by the temperature sensor.

[0035] The parallel resistor arrangement circuit of R_NTC1 to R_NTCn is set according to the temperature selection type of the household appliance used. When RD_BIN_NTC is at a high level, the parallel resistor array is turned on to provide a mode selection resistance difference matrix recognition output for the subsequent MOSFET cyclic scanning circuit and cyclic scanning ADC detection circuit.

[0036] According to the applied household appliance whole machine mode selection type, set the parallel resistor arrangement circuit of R_BIN1~R_BINn. When RD_BIN_NTC is at a low level, turn on the parallel resistor array to provide a temperature selection resistance difference matrix recognition output for the subsequent MOSFET cyclic scanning circuit and cyclic scanning ADC detection circuit.

[0037] The anti-reverse diodes D1~D10 are used to prevent the conduction of micro-current caused by reverse voltage when one of the resistors R_NTC1~R_NTCn / R_BIN1~R_BINn is turned on and the others are turned off, thereby preventing the correctness of subsequent ADC values ​​from being affected.

[0038] Specifically, when the parallel resistor arrangement circuit 2 includes parallel resistors R_NTC1~R_NTC5 and parallel resistors R_BIN1~R_BIN5, the resistor R_BIN1 is connected in series with the first diode D1, the resistor R_NTC1 is connected in series with the sixth diode D6, and then the signal BIN_NTC_1 is output in parallel, the resistor R_BIN2 is connected in series with the second diode D2, the resistor R_NTC2 is connected in series with the seventh diode D7, and then the signal BIN_NTC_2 is output in parallel, the resistor R_BIN3 is connected in series with the third diode D3, the resistor R_NTC3 is connected in series with the eighth diode D8, and then the signal BIN_NTC_3 is output in parallel, the resistor R_BIN4 is connected in series with the fourth diode D4, the resistor R_NTC4 is connected in series with the ninth diode D9, and then the signal BIN_NTC_4 is output in parallel, the resistor R_BIN5 is connected in series with the fifth diode D5, the resistor R_NTC5 is connected in series with the tenth diode D10, and then the signal BIN_NTC_5 is output in parallel.

[0039] The MOSFET cyclic scanning circuit 3 includes a first saturation conduction switch Q1 to an nth saturation conduction switch Qn, the drain of the first saturation conduction switch Q1 is connected in parallel with a capacitor C2, a single-chip drive signal IO_BIN_NTC_1 is connected in parallel with a resistor R1 and then connected to the gate of the first saturation conduction switch Q1, and the resistor R1 is grounded; the drain of the nth saturation conduction switch Qn is connected in parallel with a capacitor Cn+1, a single-chip drive signal IO_BIN_NTC_n is connected in parallel with a resistor Rn and then connected to the gate of the nth saturation conduction switch Qn, and the resistor Rn is grounded. The first saturation conduction switch Q1 to the nth saturation conduction switch Qn are all MOSFET field effect tubes.

[0040] Specifically, when the cyclic scanning circuit 3 of the MOSFET includes a first saturated conduction switch Q1, a second saturated conduction switch Q2, a third saturated conduction switch Q3, a fourth saturated conduction switch Q4 and a fifth saturated conduction switch Q5, the drain of the first saturated conduction switch Q1 is connected in parallel with a capacitor C2, and the microcontroller drive signal IO_BIN_NTC_1 is connected in parallel with a resistor R1, and the gate of the first saturated conduction switch Q1 is connected, and the resistor R1 is grounded; the drain of the first saturated conduction switch Q2 is connected in parallel with a capacitor C2, and the microcontroller drive signal IO_BIN_NTC_1 is connected in parallel with a resistor R1, and the gate of the first saturated conduction switch Q1 is connected, and the resistor R1 is grounded; the drain of the second saturated conduction switch Q2 is connected in parallel with a capacitor C3, and the microcontroller drive signal IO_BIN _NTC_2 is connected to the gate of the second saturation conduction switch Q2 in parallel with the resistor R2, and the resistor R2 is grounded; the drain of the third saturation conduction switch Q3 is connected to the gate of the first saturation conduction switch Q3 in parallel with the capacitor C4, and the microcontroller drive signal IO_BIN_NTC_3 is connected to the gate of the first saturation conduction switch Q3 in parallel with the resistor R3, and the resistor R3 is grounded; the drain of the first saturation conduction switch Q4 is connected to the gate of the first saturation conduction switch Q4 in parallel with the capacitor C5, and the microcontroller drive signal IO_BIN_NTC_4 is connected to the gate of the first saturation conduction switch Q4 in parallel with the resistor R4, and the resistor R4 is grounded; the drain of the first saturation conduction switch Q5 is connected to the gate of the first saturation conduction switch Q5 in parallel with the capacitor C6, and the microcontroller drive signal IO_BIN_NTC_5 is connected to the gate of the first saturation conduction switch Q5 in parallel with the resistor R5, and the resistor R4 is grounded. The first saturation conduction switch Q1, the second saturation conduction switch Q2, the third saturation conduction switch Q3, the fourth saturation conduction switch Q4 and the fifth saturation conduction switch Q5 are all MOSFET field effect tubes.

[0041] Among them, R1~R5 are the driving bias resistors of the saturated switches Q1~Q5, and the temperature / mode resistance matrix detection output is obtained by combining the output truth table of the BJT logic XOR circuit. The working process is as follows (here only IO_BIN_NTC1 is taken as an example, the rest are the same)

[0042] When IO_BIN_NTC1 is at a high level, the saturated conduction switch Q1 is saturated and turned on, and the R_BIN1 or R_NTC1 of the parallel resistor arrangement circuit is turned on and output to the cyclic scanning ADC detection circuit.

[0043] When IO_BIN_NTC1 is at a low level, the saturated conduction switch Q1 is turned off, R_BIN1 or R_NTC1 of the parallel resistor arrangement circuit is not conducting, and the signal of the cyclic scanning ADC detection circuit is 0.

[0044] The cyclic scanning ADC detection circuit 4 includes a resistor RS_MUX, a capacitor C1 and a resistor RP_MUX. The resistor RP_MUX and the resistor RS_MUX are connected in parallel to connect the source of the first saturated conduction switch Q1 to the source of the nth saturated conduction switch Qn. The other end of the resistor RS_MUX is connected in parallel with the capacitor C1 to output the signal AD_BIN_NTC_1to n. The other end of the capacitor C1 is grounded.

[0045] Specifically, the cyclic scanning ADC detection circuit 4 includes a resistor RS_MUX, a capacitor C1 and a resistor RP_MUX. The resistor RP_MUX and the resistor RS_MUX are connected in parallel to the source of the first saturated conduction switch Q1, the source of the second saturated conduction switch Q2, the source of the third saturated conduction switch Q3, the source of the fourth saturated conduction switch Q4, and the source of the fifth saturated conduction switch Q5. The other end of the resistor RS_MUX is connected in parallel with the capacitor C1 and then outputs the signal AD_BIN_NTC_1to n. The other end of the capacitor C1 is grounded.

[0046] The resistor RS_MUX (10K) + capacitor C1 form a low-pass filter to eliminate interference signals and ensure the stable output of the output signal AD_BIN_NTC_x; the resistor RP_MUX (3.3K) is a voltage divider resistor; through the microcontroller logic algorithm and according to the value of the current ADC data acquisition signal, it is used to improve the ability of household appliances to utilize various environmental data collection and intelligent control.

[0047] Combined with the above working process, the final truth table of the present invention is as follows:

[0048]

[0049] The present invention abandons the dedicated multi-channel selection output chip circuit, reduces the hardware cost in the design process, abandons the mechanical button type matrix output circuit, reduces the single-chip microcomputer ADC electrical signal jitter, realizes the dual output type selection circuit of single I / O control based on the BJT logic XOR circuit, reduces the single-chip microcomputer IO port control resources of dual-channel output, and expands the MOSFET cycle scanning circuit by 2 times; based on the combined parallel resistor arrangement circuit of resistor + anti-reverse diode, realizes the layout of multiple temperature or mode resistor values, and greatly improves the ability of household appliances to utilize various environmental data collection and intelligent control; based on the MOSFET cycle scanning circuit, realizes the cycle scanning matrix output selection circuit, shares the cycle scanning ADC detection, reduces the single-chip microcomputer ADC port demand data, theoretical calculation and single-chip microcomputer algorithm refinement support, the circuit has a long working life, high precision, and stable output electrical signals.

[0050] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A matrix multiplexer output circuit based on single chip microcomputer control, characterized in that: The invention comprises a BJT logic XOR circuit (1), a parallel resistor arrangement circuit (2), a MOSFET cyclic scanning circuit (3) and a cyclic scanning ADC detection circuit (4) which are connected in sequence. The BJT logic XOR circuit (1) is used to realize the temperature or mode selection of single control dual output, the parallel resistor arrangement circuit (2) is used to realize the resistance value layout of multiple temperatures or modes, the MOSFET cyclic scanning circuit (3) is used to realize cyclic scanning matrix output, and the cyclic scanning ADC detection circuit (4) is used to enhance the ability of household appliances to collect various environmental data and intelligently control them. (1) includes a first transistor switch QB1, a second transistor switch QB2, and a third transistor switch QB3, wherein the input terminal RD_BIN_NTC signal is connected to the base of the first transistor switch QB1 and the base of the third transistor switch QB3, the emitter of the first transistor switch QB1 is connected to the emitter of the second transistor switch QB2 and the emitter of the third transistor switch QB3 and is connected in parallel to a power supply VDD-UC, the collector of the first transistor switch QB1 is connected in series with a resistor R_RD_NTC and a capacitor C8 and then outputs a signal RD_NTC; the collector of the third transistor switch QB3 is connected to the emitter of the second transistor switch QB2 and the emitter of the third transistor switch QB3 and is connected in parallel to a power supply VDD-UC, the collector of the first transistor switch QB1 is connected in series with a resistor R_RD_NTC and a capacitor C8 and then outputs a signal RD_NTC; the collector of the third transistor switch QB3 is connected to the emitter of the second transistor switch QB2 and the emitter of the third transistor switch QB3 and is connected in parallel to a power supply VDD-UC; The base of the transistor switch QB2 is connected in series with a resistor R7 and then grounded; the collector of the second transistor switch QB2 is connected in series with a resistor R_RD_BIN and in parallel with a resistor C7 and then outputs a signal RD_BIN; the parallel resistor arrangement circuit (2) comprises parallel resistors R_NTC1 to R_NTCn and parallel resistors R_BIN1 to R_BINn, the resistor R_BIN1 is connected in series with a first diode D1, the resistor R_NTC1 is connected in series with an n+1th diode Dn+1 and then outputs a signal BIN_NTC_1 in parallel, the resistor R_BINn is connected in series with an nth diode Dn, the resistor R_NTCn is connected in series with a 2nth diode D2n and then outputs a signal BIN_NTC_1 in parallel Output signal BIN_NTC_n, wherein n∈N*, n≥2; the cyclic scanning circuit (3) of the MOSFET comprises a first saturation conduction switch Q1 to an nth saturation conduction switch Qn, the drain of the first saturation conduction switch Q1 is connected in parallel with a capacitor C2, the single chip drive signal IO_BIN_NTC_1 is connected in parallel with a resistor R1 and then connected to the gate of the first saturation conduction switch Q1, the resistor R1 is grounded; the drain of the nth saturation conduction switch Qn is connected in parallel with a capacitor Cn+1, the single chip drive signal IO_BIN_NTC_n is connected in parallel with a resistor Rn and then connected to the gate of the nth saturation conduction switch Qn, the resistor Rn is grounded;The cyclic scanning ADC detection circuit (4) comprises a resistor RS_MUX, a capacitor C1 and a resistor RP_MUX, wherein the resistor RP_MUX and the resistor RS_MUX are connected in parallel to connect the source of the first saturation conduction switch Q1 to the source of the nth saturation conduction switch Qn, and the other end of the resistor RS_MUX is connected in parallel to the capacitor C1 to output a signal AD_BIN_NTC_1ton, and the other end of the capacitor C1 is grounded. ; 2. The matrix multiplexer output circuit based on single chip microcomputer control according to claim 1, characterized in that: The temperature or mode selection in the BJT logic XOR circuit (1) is respectively a temperature selection resistor detection output or a mode selection resistor detection output.

3. The matrix multiplexer output circuit based on single chip microcomputer control according to claim 2, characterized in that: The multiple temperatures or modes of the parallel resistor arrangement circuit (2) are respectively multiple temperatures or multiple mode signals detected by a temperature sensor.

4. The matrix multiplexer output circuit based on single chip microcomputer control according to claim 1, characterized in that: The circuit structure of the first transistor switch QB1 is the same as the circuit structure of the second transistor switch QB2 and the circuit structure of the third transistor switch QB3. The circuit structure of the first transistor switch QB1 includes a transistor QB, a resistor RA and a resistor RB. The emitter of the transistor QB is connected in series with the resistor RB and then connected to the base of the transistor QB. The base of the transistor QB is connected in series with the resistor RA.

5. The matrix multiplexer output circuit based on single chip microcomputer control according to claim 1, characterized in that: The first saturated conduction switch Q1 to the nth saturated conduction switch Qn are all MOSFET field effect transistors.

6. The matrix multiplexer output circuit based on single chip microcomputer control according to any one of claims 4 to 5, characterized in that: The input terminal RD_BIN_NTC signal is a single IO control signal output by the single chip microcomputer.

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