Method and device for generating through hole layer layout

Abstract

The present invention discloses a method and device for generating a through-hole layer layout, the method comprising: receiving an original through-hole layer layout, the original through-hole layer layout comprising more than two original through-holes; determining the candidate positions of the additional through-holes corresponding to each original through-hole on the original through-hole layer layout according to a pre-set feasible guide pattern, wherein the feasible guide pattern is a pattern corresponding to a through-hole combination; selecting the final position of the additional through-hole in the candidate position according to the manufacturing cost of the feasible guide pattern; inserting the additional through-hole at the final position; splitting all through-holes on the through-hole layer layout after the additional through-holes are inserted onto more than two mask plates to obtain the final through-hole layer layout. The method and device for generating a through-hole layer layout provided by the present invention take the manufacturing cost into consideration when inserting the additional through-holes, thereby reducing the manufacturing cost of the pattern.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a method and device for generating a through-hole layer layout. Background Art

[0002] As Moore's Law continues to approach the physical limit, the manufacturing process of integrated circuits and the reliability of circuits are facing great challenges. Photolithography, as the most critical step in integrated circuit manufacturing, is the process step of transferring the pattern on the mask to the wafer. The continuous reduction of the feature size of integrated circuits makes traditional photolithography methods increasingly unable to meet the requirements of graphic resolution. If traditional photolithography continues to be applied to the manufacture of circuits at small nodes, various bad points will appear in the circuits on the silicon wafer, and these bad points are very likely to cause the circuit to fail. In order to solve the above problems, various photolithography resolution enhancement technologies have emerged.

[0003] At present, the commonly used lithography resolution enhancement technologies mainly include multiple pattern exposure, nanoimprinting, extreme ultraviolet lithography, and directed self-assembly of block copolymers. Multiple pattern exposure is to split the patterns that cannot be distinguished by single-layer exposure lithography into two or even more different masks to increase the pattern resolution in the lithography stage. However, this method greatly increases the cost of circuit manufacturing, and in the complex pattern manufacturing process, the alignment accuracy of the two exposure patterns is also challenged. Nanoimprinting and extreme ultraviolet lithography also have some problems that need to be solved, such as materials and equipment. The directed self-assembly of block copolymers utilizes the characteristics of block copolymers that can spontaneously form ordered structures under the action of various fields, which greatly improves the pattern resolution under single-layer exposure. At the same time, due to its advantages such as high throughput and good alignment accuracy, it has received great attention from scientific researchers.

[0004] The via layer is a key layer in integrated circuit manufacturing. Its function is to connect the metal wires of the upper and lower layers. At sub-14nm and smaller process nodes, the size of the vias and the distance between the vias are getting smaller and smaller, even smaller than the limit of traditional lithography resolution. Such small via size and spacing, coupled with factors such as lithography proximity effect, cause the vias to be disconnected during the manufacturing process, causing circuit failure. Redundant vias are a typical technology that helps to manufacture the via layer and improves the reliability of the circuit. In the manufacture of circuits at small nodes, due to the decreasing wiring resources and space, the insertion of redundant vias becomes not so simple. Usually, the evaluation indicator for inserting redundant vias is the insertion rate of redundant vias. The higher the insertion rate, the lower the probability of failure of the circuit during the manufacturing process.

[0005] Due to the inherent characteristics of block copolymers and process limitations, Directed Self-Assembly (DSA) lithography using graphepitaxial method is more suitable for manufacturing through-hole patterns. In the process, a guide template is first prepared using traditional photolithography technology, and the block copolymer is filled into it. Through various field effects, two or more through-hole structures are formed in one template. The hole spacing between the through-holes is determined by the natural period of the block copolymer. The through-hole pattern is then transferred to the substrate using selective etching technology, thus achieving a graphic resolution enhancement effect. In the traditional DSA process combined with redundant through-hole insertion in circuit manufacturing, the impact on process manufacturing is not considered when inserting redundant through-holes, which increases the cost of the process manufacturing stage. Summary of the invention

[0006] The present invention aims to solve the problem that in the circuit manufacturing combining the traditional DSA process with the insertion of redundant vias, the impact on the process manufacturing is not considered when the redundant vias are inserted, thus increasing the cost of the process manufacturing stage.

[0007] The present invention is achieved through the following technical solutions:

[0008] A method for generating a through-hole layer layout, comprising:

[0009] Receiving an original through-hole layer layout, wherein the original through-hole layer layout includes more than two original through-holes;

[0010] According to a preset feasible guide pattern, determining a candidate position of an additional through hole corresponding to each original through hole on the original through hole layer layout, wherein the feasible guide pattern is a pattern corresponding to the through hole combination;

[0011] selecting a final position of the additional through hole from among the candidate positions according to a manufacturing cost of the feasible guide pattern;

[0012] inserting said additional through hole in said final position;

[0013] All through holes on the through hole layer layout after the additional through holes are inserted are split onto more than two mask plates to obtain a final through hole layer layout.

[0014] Optionally, the through hole combination includes two through holes arranged horizontally, three through holes arranged horizontally with equal spacing, two through holes arranged vertically, three through holes arranged vertically with equal spacing, four through holes whose centers are located at the four vertices of a square, two through holes arranged at a 45-degree angle to the horizontal direction, three through holes arranged at an equal spacing and at a 45-degree angle to the horizontal direction, two through holes arranged at a 135-degree angle to the horizontal direction, and three through holes arranged at an equal spacing and at a 135-degree angle to the horizontal direction.

[0015] Optionally, the hole spacing between two adjacent through holes arranged horizontally is twice the width of the original through hole, the hole spacing between two adjacent through holes arranged vertically is twice the width of the original through hole, and the hole spacing between two adjacent through holes arranged at a 45 degree angle to the horizontal direction is twice the width of the original through hole. times, the hole spacing between two adjacent through holes arranged at an angle of 135 degrees to the horizontal direction is the original through hole width times.

[0016] Optionally, each original through hole corresponds to an additional through hole, and the additional through hole is a redundant through hole or a pseudo through hole.

[0017] Optionally, each original through hole corresponds to two additional through holes, and both of the two additional through holes are redundant through holes, or both of the two additional through holes are dummy through holes, or the two additional through holes include one redundant through hole and one dummy through hole.

[0018] Optionally, after inserting the additional through hole in the final position, the method further comprises:

[0019] All through holes on the through hole layer layout after the additional through holes are inserted are grouped, and the through holes with the same hole spacing are located in the same group, so that different block copolymers can be used to manufacture through holes with different hole spacings when manufacturing through holes.

[0020] Optionally, splitting all through holes on the through hole layer layout after inserting the additional through hole into more than two mask plates includes:

[0021] Using a graphical model to represent a through-hole layer layout after inserting the additional through-hole;

[0022] Transform the through-hole splitting problem into an exact covering problem and obtain an exact covering matrix;

[0023] Constructing an objective function according to the graph model and the precise coverage matrix, wherein the objective function is used to characterize the total cost of unresolved conflicts and the use of masks;

[0024] Find a solution that minimizes the objective function.

[0025] Optionally, the graph model is G=(V, C, T), wherein V represents a through-hole set, C represents a conflicting edge set, and T represents a feasible guide pattern set, wherein the conflicting edges are edges between two through-holes that can be classified into the same feasible guide pattern and edges between two through-holes whose hole spacing is smaller than the minimum spacing that can be resolved by a single exposure but cannot be classified into the same feasible guide pattern.

[0026] Optionally, the precise coverage matrix is ​​a 2×2 matrix, wherein the through-hole column indicates that each through-hole must be assigned to a feasible guide pattern, the template column indicates that the hole spacing of the feasible guide patterns on the same mask is the same, the through-hole row indicates that the through-holes are assigned to a single-hole guide pattern, and the template row indicates that the through-holes in the same feasible guide pattern are assigned to the same mask.

[0027] Optionally, the objective function is:

[0028]

[0029] The constraints of the objective function are:

[0030]

[0031]

[0032] Among them, C i represents the i-th conflict edge, T j represents the jth feasible guide graph, as well as Represents a Boolean variable, W c represents the cost of mask space conflict, W T,j represents the mask cost of the jth feasible guide pattern, u and v represent two through holes in the same feasible guide pattern, K represents the number of masks to be used, |V| represents the number of through holes, |C| represents the number of spatial conflicting edges, V i represents the through hole in the i-th row, V j represents the through hole in the jth column.

[0033] Based on the same inventive concept, the present invention also provides a through-hole layer layout generation device, comprising:

[0034] A receiving module, used for receiving an original through-hole layer layout, wherein the original through-hole layer layout includes more than two original through-holes;

[0035] A candidate position determination module, used to determine the candidate position of the additional through hole corresponding to each original through hole on the original through hole layer layout according to a preset feasible guide pattern, wherein the feasible guide pattern is a pattern corresponding to the through hole combination;

[0036] A final position selection module, used for selecting a final position of the additional through hole in the candidate positions according to the manufacturing cost of the feasible guide pattern;

[0037] a through-hole insertion module for inserting the additional through-hole at the final position;

[0038] The through hole splitting module is used to split all through holes on the through hole layer layout after the additional through holes are inserted into more than two mask plates to obtain the final through hole layer layout.

[0039] Based on the same inventive concept, the present invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned through-hole layer layout generation method when executing the computer program.

[0040] Based on the same inventive concept, the present invention also provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the above-mentioned through-hole layer layout generation method are implemented.

[0041] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0042] The method and device for generating a through-hole layer layout provided by the present invention determine the candidate positions of the additional through-holes corresponding to each original through-hole according to a pre-set feasible guide pattern, and select the final positions of the additional through-holes from the candidate positions according to the manufacturing cost of the feasible guide pattern, that is, when inserting the additional through-holes, the manufacturing cost is taken into consideration, which can reduce the manufacturing cost of the pattern. In addition, the method and device for generating a through-hole layer layout provided by the present invention treat redundant through-holes and pseudo through-holes as additional through-holes and do not consider them separately, which simplifies the complexity of the problem, thereby simplifying the algorithm and improving the calculation speed. Furthermore, the method and device for generating a through-hole layer layout provided by the present invention split all through-holes onto more than two mask plates after inserting the additional through-holes, and use multiple pattern exposures to increase the pattern resolution in the photolithography stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings:

[0044] Figure 1 A flow chart of a method for generating a through-hole layer layout according to an embodiment of the present invention;

[0045] Figure 2 is a schematic diagram of redundant vias and dummy vias according to an embodiment of the present invention;

[0046] Figure 3 A feasible guide graph provided by an embodiment of the present invention;

[0047] Figure 4 A schematic diagram of candidate positions of additional through holes corresponding to original through holes of two different layouts provided in an embodiment of the present invention;

[0048] Figure 5 Schematic diagram of the process of DSA fabrication of through-holes using two different block copolymers;

[0049] Figure 6 A schematic diagram of a graph model provided by an embodiment of the present invention;

[0050] Figure 7 is a schematic diagram of the existing GG / SG graph model;

[0051] Figure 8 A schematic diagram of a precise coverage matrix provided by an embodiment of the present invention;

[0052] Fig. 9 A schematic diagram of a simplified accurate coverage matrix provided by an embodiment of the present invention;

[0053] Fig.10 Schematic diagram of the structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0054] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The exemplary embodiments of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention.

[0055] Example 1

[0056] This embodiment provides a method for generating a through hole layer layout. Figure 1 It is a flow chart of the method for generating a through hole layer layout, and the method for generating a through hole layer layout includes steps S11 to S15.

[0057] Step S11, receiving an original through-hole layer layout, wherein the original through-hole layer layout includes more than two original through-holes.

[0058] The original through-hole layer layout can be a layout actually designed or a layout randomly generated by a software system. The original through-holes are used to connect the metal wires in the upper layer of the through-hole layer and the metal wires in the lower layer of the through-hole layer. The number of the original through-holes is determined by the actual circuit structure, which is not limited in the embodiment of the present invention.

[0059] Step S12, determining the candidate position of the additional through hole corresponding to each original through hole on the original through hole layer layout according to a preset feasible guide pattern, wherein the feasible guide pattern is a pattern corresponding to the through hole combination.

[0060] In order to simplify the complexity of the problem, in this embodiment, redundant through holes and dummy through holes are uniformly regarded as additional through holes and are not considered separately. That is, the additional through holes can be redundant through holes or dummy through holes. Figure 2 It is a schematic diagram of redundant vias and pseudo vias, where the redundant vias are also used to connect the metal wires located in the upper layer of the via layer and the metal wires located in the lower layer of the via layer, which can make up for the manufacturing failure caused by insufficient etching and other reasons; the pseudo vias are independent vias and have no connection with the metal wires, which can enhance the diffusion capacity of stress-induced voids in metal interconnection and improve the reliability of metal interconnection.

[0061] In the DSA manufacturing process, due to the limitations of traditional photolithography, not all guide patterns can be manufactured. Therefore, it is necessary to pre-set the patterns corresponding to the through-hole combinations that can be manufactured, that is, pre-set the feasible guide patterns, and determine the candidate positions of the additional through-holes corresponding to each original through-hole according to the feasible guide patterns. Figure 3 It is a feasible guiding pattern provided by this embodiment. There are nine kinds of feasible guiding patterns, namely, two through holes arranged horizontally, three through holes arranged horizontally with equal spacing, two through holes arranged vertically, three through holes arranged vertically with equal spacing, four through holes whose centers are located at the four vertices of a square, two through holes arranged at a 45-degree angle to the horizontal direction, three through holes arranged at an equal spacing and at a 45-degree angle to the horizontal direction, two through holes arranged at a 135-degree angle to the horizontal direction, and three through holes arranged at an equal spacing and at a 135-degree angle to the horizontal direction.

[0062] The hole spacing between two through holes is the distance between the centers of the two through holes. In the feasible guide pattern, if the hole spacing between two adjacent through holes is set too small, the inserted additional through hole may not be manufactured; if the hole spacing between two adjacent through holes is set too large, the inserted additional through hole may not be able to improve the reliability of the circuit. Therefore, in the feasible guide pattern, the hole spacing between two adjacent through holes can be set according to the actual process level and the circuit performance that needs to be achieved. In the feasible guide pattern of the present embodiment, the hole spacing between two adjacent through holes arranged horizontally is twice the width of the original through hole, the hole spacing between two adjacent through holes arranged vertically is twice the width of the original through hole, and the hole spacing between two adjacent through holes arranged at a 45-degree angle to the horizontal direction is times, the hole spacing between two adjacent through holes arranged at an angle of 135 degrees to the horizontal direction is the original through hole width times. For a through hole with a circular horizontal cross section, the through hole width is the diameter of the circle; for a through hole with a square horizontal cross section, the through hole width is the side length of the square. Figure 3 The feasible guide patterns shown have different candidate positions for the additional vias corresponding to the original vias of different layouts. Figure 4 The candidate positions of the additional through holes corresponding to the original through holes of two different layouts are listed, and the candidate positions of the additional through holes corresponding to the original through holes of other layouts are not listed one by one.

[0063] Step S13, selecting a final position of the additional through hole from the candidate positions according to the manufacturing cost of the feasible guide pattern.

[0064] In the DSA manufacturing process, different guide patterns have different manufacturing costs. In this embodiment, when inserting the additional through hole, the manufacturing cost is taken into consideration, and a candidate position with a lower manufacturing cost is selected as the final position. For example, when the additional through hole can be inserted at an angle of 45 degrees to the horizontal direction, at an angle of 135 degrees to the horizontal direction, in the horizontal direction, and in the vertical direction, it is preferred to insert the additional through hole in the horizontal direction or in the vertical direction, so that the overall manufacturing cost can be reduced.

[0065] Step S14, inserting the additional through hole at the final position.

[0066] In this embodiment, each original through hole may correspond to one additional through hole, and the additional through hole may be a redundant through hole or a pseudo through hole; each original through hole may correspond to two additional through holes, and the two additional through holes may be redundant through holes, or the two additional through holes may be pseudo through holes, or the two additional through holes may include one redundant through hole and one pseudo through hole.

[0067] In an optional implementation, after inserting the additional through-holes, all through-holes on the through-hole layer layout after inserting the additional through-holes can be grouped, and through-holes with the same hole spacing are located in the same group, so that different block copolymers can be used to manufacture through-holes with different hole spacings when manufacturing through-holes. Figure 3 As an example of the feasible guide pattern shown in FIG. 1 , the through holes arranged horizontally and vertically have the same hole spacing, and the through holes arranged at an angle of 45 degrees to the horizontal direction and at an angle of 135 degrees to the horizontal direction have the same hole spacing, so that Figure 3 The feasible guide patterns shown are divided into two groups, upper and lower. When the DSA process is used to manufacture through holes, different block copolymers are used for feasible guide patterns with different hole spacings. Since the natural periods of different block copolymers are different, the hole spacings formed by the copolymers in microphase separation can adapt to the requirements of the target through hole pattern for different hole spacings. Applying two or more different block copolymers to different mask plates can greatly improve the alignment accuracy of each layer of through holes, increase the flexibility of inserting the additional through holes, and expand the types of the feasible guide patterns. Figure 5 This is a process step of using two different block copolymers to perform DSA to manufacture through holes. Those skilled in the art know how to use two different block copolymers to perform DSA to manufacture through holes, which will not be described in detail here.

[0068] Step S15, splitting all through holes on the through hole layer layout after inserting the additional through holes into more than two mask plates to obtain a final through hole layer layout.

[0069] All through holes are split onto more than two masks, and multiple pattern exposures are used to increase the pattern resolution at the photolithography stage. The larger the number of masks, the higher the photolithography resolution, but the cost is correspondingly higher. Therefore, the number of masks can be determined based on the manufacturing cost and the photolithography resolution, and this embodiment does not limit this. All through holes can be split using an existing splitting method. However, the existing splitting method does not consider the impact on process manufacturing, which will increase the cost of the process manufacturing stage. This embodiment provides a splitting method that takes into account the manufacturing difficulty brought about by through hole grouping, which can reduce the manufacturing cost of the pattern and improve circuit reliability.

[0070] First, a graph model is used to represent the via layer layout after the additional vias are inserted. This embodiment provides a simplified graph model G=(V, C, T), where V represents a via set, C represents a conflicting edge set, and T represents a feasible guide pattern set. Figure 6 It is a schematic diagram of the graphic model provided in this embodiment, wherein the solid line frame is a feasible guide pattern, and the dotted line is a conflicting edge, wherein the conflicting edge is an edge between two through holes that can be divided into the same feasible guide pattern and an edge between two through holes whose hole spacing is smaller than the minimum spacing that can be distinguished by a single exposure but cannot be divided into the same feasible guide pattern. Figure 7 is a schematic diagram of an existing GG / SG graph model, which includes vertices and three different edges. Compared with the existing GG / SG graph model, the graph model provided by this embodiment includes a feasible guide graph that directly constitutes a double through hole and a feasible guide graph of a triple through hole in the solid line frame, which simplifies the problem, greatly reduces the amount of calculation of the subsequent algorithm, and does not lose the key information between the through holes.

[0071] According to the graph model provided in this embodiment, a feasible guide pattern formed after inserting the additional through hole can be determined. For the through hole layer layout splitting problem, each through hole needs to be divided into a specific guide pattern. Based on the similarity of the problem, the through hole splitting problem can be transformed into an accurate coverage problem to obtain an accurate coverage matrix. The accurate coverage matrix is ​​as follows: Figure 8 As shown, it includes three columns: the through-hole column indicates that each through-hole must be assigned to a feasible guide pattern, the template column indicates that the hole spacing of the feasible guide patterns on the same mask is the same, the conflict column indicates that the through-holes smaller than the minimum exposure spacing must be assigned to the same feasible guide pattern or to different mask plates, the through-hole row indicates that the through-holes are assigned to a single-hole guide pattern, the template row indicates that the through-holes in the same feasible guide pattern are assigned to the same mask plate, and the independent row ensures that all conflict columns and template columns can be covered.

[0072] The precise coverage matrix can be analyzed for a specific BCP (block co-polymer) combination, and then the optimal BCP combination can be selected. Therefore, the precise coverage matrix can be simplified to obtain a simplified precise coverage matrix, such as Fig. 9 shown.

[0073] According to the graph model and Fig. 9 The exact coverage matrix shown uses the ILP (integer linear programming) equation to solve the via allocation problem and construct an objective function that characterizes the total cost of unresolved conflicts and mask usage. The objective function is:

[0074]

[0075] The constraints of the objective function are:

[0076]

[0077]

[0078] Among them, C i Indicates the i-th conflict edge, which contains two vertices;

[0079] T j represents the jth feasible guided graph, which contains a set of vertices in a feasible guided graph;

[0080] Represents a Boolean variable. If two points on the kth mask are included in the i-th conflicting edge C i In is 1;

[0081] V i k Represents a Boolean variable. If the through hole V in the i-th row i is assigned to a single hole guide pattern on the kth mask, then V i k is 1;

[0082] Represents a Boolean variable. If a porous guide graph is selected and all vertices in the porous guide graph are assigned to the kth mask, then is 1;

[0083] Represents a Boolean variable. If the through hole V in the jth column j is assigned to a single hole guide pattern on the kth mask, then is 1;

[0084] W c represents the cost of mask space conflict;

[0085] W T,j represents the mask cost of the jth feasible guide pattern;

[0086] u and v represent two vias in the same feasible guide pattern;

[0087] K represents the number of masks to be used;

[0088] |V| represents the number of through holes;

[0089] |C| represents the number of spatial conflicting edges;

[0090] V i represents the through hole in the i-th row;

[0091] V j represents the through hole in the jth column.

[0092] In general, the cost of mask space conflict is W c is large, ensuring that conflicts have a greater priority and are minimized. Constraint (1) means that each via can only belong to one feasible guide pattern, and constraint (2) means that for each conflicting column The number of 1s covered must be equal to or less than 1, otherwise will be set to 1 (an unresolved conflict), which will greatly increase the cost resulting in a larger conflict.

[0093] Solve the solution that minimizes the objective function, and the solution that minimizes the objective function is the through-hole layer layout splitting, and obtain the final through-hole layer layout. In this embodiment, Gurobi can be used to solve the ILP problem. In this embodiment, when splitting the through-hole, the manufacturing cost of the feasible guide pattern is taken into account, and the through-hole layer layout is optimized from the perspective of process manufacturing.

[0094] Example 2

[0095] Based on the same inventive concept, this embodiment provides a through-hole layer layout generation device, and the through-hole layer layout generation device includes:

[0096] A receiving module, used for receiving an original through-hole layer layout, wherein the original through-hole layer layout includes more than two original through-holes;

[0097] A candidate position determination module, used to determine the candidate position of the additional through hole corresponding to each original through hole on the original through hole layer layout according to a preset feasible guide pattern, wherein the feasible guide pattern is a pattern corresponding to the through hole combination;

[0098] A final position selection module, used for selecting a final position of the additional through hole in the candidate positions according to the manufacturing cost of the feasible guide pattern;

[0099] a through-hole insertion module for inserting the additional through-hole at the final position;

[0100] The through hole splitting module is used to split all through holes on the through hole layer layout after the additional through holes are inserted into more than two mask plates to obtain the final through hole layer layout.

[0101] In an optional implementation, the through hole combination includes two through holes arranged horizontally, three through holes arranged horizontally with equal spacing, two through holes arranged vertically, three through holes arranged vertically with equal spacing, four through holes whose centers are located at the four vertices of a square, two through holes arranged at a 45-degree angle to the horizontal direction, three through holes arranged at an equal spacing and at a 45-degree angle to the horizontal direction, two through holes arranged at a 135-degree angle to the horizontal direction, and three through holes arranged at an equal spacing and at a 135-degree angle to the horizontal direction.

[0102] In an optional implementation, the hole spacing between two adjacent through holes arranged horizontally is twice the original through hole width, the hole spacing between two adjacent through holes arranged vertically is twice the original through hole width, and the hole spacing between two adjacent through holes arranged at a 45 degree angle to the horizontal direction is twice the original through hole width. times, the hole spacing between two adjacent through holes arranged at an angle of 135 degrees to the horizontal direction is the original through hole width times.

[0103] In an optional implementation, each original through-hole corresponds to an additional through-hole, and the additional through-hole is a redundant through-hole or a pseudo through-hole.

[0104] In an optional implementation, each original through-hole corresponds to two additional through-holes, and the two additional through-holes are both redundant through-holes, or the two additional through-holes are both dummy through-holes, or the two additional through-holes include one redundant through-hole and one dummy through-hole.

[0105] In an optional implementation, the method further includes:

[0106] The grouping module is used to group all through holes on the through hole layer layout after the additional through holes are inserted, and the through holes with the same hole spacing are located in the same group, so that different block copolymers can be used to manufacture through holes with different hole spacings when manufacturing through holes.

[0107] In an optional implementation, the through-hole splitting module includes:

[0108] A model representation module, used for using a graphical model to represent a through-hole layer layout after the additional through-hole is inserted;

[0109] A problem conversion module is used to convert the through-hole splitting problem into an accurate coverage problem to obtain an accurate coverage matrix;

[0110] A function construction module, used for constructing an objective function according to the graph model and the precise coverage matrix, wherein the objective function is used for characterizing the total cost of unresolved conflicts and the use of a mask;

[0111] The solution module is used to find a solution that minimizes the objective function.

[0112] In an optional implementation, the graph model is G=(V, C, T), wherein V represents a through-hole set, C represents a conflicting edge set, and T represents a feasible guide pattern set, wherein the conflicting edges are edges between two through-holes that can be classified into the same feasible guide pattern and edges between two through-holes whose hole spacing is smaller than the minimum spacing that can be resolved by a single exposure but cannot be classified into the same feasible guide pattern.

[0113] In an optional implementation, the precise coverage matrix is ​​a 2×2 matrix, wherein the through-hole column indicates that each through-hole must be assigned to a feasible guide pattern, the template column indicates that the hole spacing of the feasible guide patterns on the same mask is the same, the through-hole row indicates that the through-holes are assigned to a single-hole guide pattern, and the template row indicates that the through-holes in the same feasible guide pattern are assigned to the same mask.

[0114] In an optional implementation, the objective function is:

[0115]

[0116] The constraints of the objective function are:

[0117]

[0118]

[0119] Among them, C i represents the i-th conflict edge, T j represents the jth feasible guide graph, V i k , as well as Represents a Boolean variable, W c represents the cost of mask space conflict, W T,jrepresents the mask cost of the jth feasible guide pattern, u and v represent two through holes in the same feasible guide pattern, K represents the number of masks to be used, |V| represents the number of through holes, |C| represents the number of spatial conflicting edges, V i represents the through hole in the i-th row, V j represents the through hole in the jth column.

[0120] The specific manner in which each module of this embodiment performs operations has been described in detail in Embodiment 1 and will not be elaborated here.

[0121] Example 3

[0122] Based on the same inventive concept, this embodiment provides a computer device. Fig.10 1 is a structural diagram of the computer device, which includes a memory 1004, a processor 1002, and a computer program stored in the memory 1004 and executable on the processor 1002. When the processor 1002 executes the program, the steps of the through-hole layer layout generation method provided in Example 1 are implemented.

[0123] Among them, Fig.10 In the embodiment of the present invention, a bus architecture (represented by bus 1000) is shown, bus 1000 may include any number of interconnected buses and bridges, bus 1000 links various circuits including one or more processors represented by processor 1002 and memory represented by memory 1004. Bus 1000 may also link various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. Bus interface 1006 provides an interface between bus 1000 and receiver 1001 and transmitter 1003. Receiver 1001 and transmitter 1003 may be the same element, namely a transceiver, providing a unit for communicating with various other devices over a transmission medium. Processor 1002 is responsible for managing bus 1000 and general processing, while memory 1004 may be used to store data used by processor 1002 when performing operations.

[0124] Example 4

[0125] Based on the same inventive concept, this embodiment provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the steps of the through-hole layer layout generation method provided in Embodiment 1 are implemented.

[0126] This specification is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of this specification. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that has the functions specified in one or more boxes.

[0127] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0128] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0129] Although the preferred embodiments of this specification have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of this specification.

[0130] Obviously, those skilled in the art can make various changes and modifications to this specification without departing from the spirit and scope of this specification. Thus, if these modifications and variations of this specification fall within the scope of the claims of this specification and their equivalents, this specification is also intended to include these modifications and variations.

Claims

1. A method for generating a through hole layer layout, characterized in that: include: Receiving an original through-hole layer layout, wherein the original through-hole layer layout includes more than two original through-holes; According to a preset feasible guide pattern, determining a candidate position of an additional through hole corresponding to each original through hole on the original through hole layer layout, wherein the feasible guide pattern is a pattern corresponding to the through hole combination; selecting a final position of the additional through hole from among the candidate positions according to a manufacturing cost of the feasible guide pattern; inserting said additional through hole in said final position; Splitting all through holes on the through hole layer layout after inserting the additional through holes onto two or more mask plates to obtain a final through hole layer layout; The through hole combination includes two through holes arranged horizontally, three through holes arranged horizontally with equal spacing, two through holes arranged vertically, three through holes arranged vertically with equal spacing, four through holes whose centers are located at the four vertices of a square, two through holes arranged at a 45-degree angle to the horizontal direction, three through holes arranged at an equal spacing and at a 45-degree angle to the horizontal direction, two through holes arranged at a 135-degree angle to the horizontal direction, and three through holes arranged at an equal spacing and at a 135-degree angle to the horizontal direction.

2. The method for generating a through hole layer layout according to claim 1, characterized in that: The hole spacing between two adjacent through holes arranged horizontally is twice the original through hole width, the hole spacing between two adjacent through holes arranged vertically is twice the original through hole width, and the hole spacing between two adjacent through holes arranged at a 45-degree angle to the horizontal direction is twice the original through hole width. times, the hole spacing between two adjacent through holes arranged at an angle of 135 degrees to the horizontal direction is the original through hole width times.

3. The method for generating a through hole layer layout according to claim 1, characterized in that: Each original through-hole corresponds to an additional through-hole, and the additional through-hole is a redundant through-hole or a pseudo through-hole.

4. The method for generating a through hole layer layout according to claim 1, characterized in that: Each original through-hole corresponds to two additional through-holes, and the two additional through-holes are both redundant through-holes, or the two additional through-holes are both dummy through-holes, or the two additional through-holes include one redundant through-hole and one dummy through-hole.

5. The method for generating a through hole layer layout according to claim 1, characterized in that: After inserting the additional through hole in the final position, further comprising: All through holes on the through hole layer layout after the additional through holes are inserted are grouped, and the through holes with the same hole spacing are located in the same group, so that different block copolymers can be used to manufacture through holes with different hole spacings when manufacturing through holes.

6. The method for generating a through hole layer layout according to claim 1, characterized in that: The step of splitting all the through holes on the through hole layer layout after inserting the additional through hole into two or more mask plates comprises: Using a graphical model to represent a through-hole layer layout after inserting the additional through-hole; Transform the through-hole splitting problem into an exact covering problem and obtain an exact covering matrix; Constructing an objective function according to the graph model and the precise coverage matrix, wherein the objective function is used to characterize the total cost of unresolved conflicts and the use of masks; Find a solution that minimizes the objective function.

7. The method for generating a through hole layer layout according to claim 6, characterized in that: The graph model is ,in, represents a set of through holes, represents the set of conflicting edges, represents a set of feasible guide patterns, wherein the conflicting edges are edges between two through holes that are classified into the same feasible guide pattern and edges between two through holes whose hole spacing is smaller than the minimum spacing that can be resolved by a single exposure but cannot be classified into the same feasible guide pattern.

8. The method for generating a through hole layer layout according to claim 7, characterized in that: The precise coverage matrix is ​​a 2×2 matrix, wherein the through-hole column indicates that each through-hole must be assigned to a feasible guide pattern, the template column indicates that the hole spacing of the feasible guide patterns on the same mask is the same, the through-hole row indicates that the through-hole is assigned to a single-hole guide pattern, and the template row indicates that the through-holes in the same feasible guide pattern are assigned to the same mask.

9. The method for generating a through hole layer layout according to claim 8, characterized in that: The objective function is: ， The constraints of the objective function are: ， ， in, Indicates conflicting sides, Indicates A feasible guide graph, , , as well as represents a Boolean variable, represents the cost of mask space conflict, Indicates The mask cost of a feasible guide pattern, and represents two vias in the same feasible guide pattern, Indicates the number of masks to be used. Indicates the number of through holes, represents the number of spatial conflict edges, Indicates Rows of through holes, Indicates The through holes in the column, V represents the through hole set.

10. A through hole layer layout generation device, characterized in that: include: A receiving module, used for receiving an original through-hole layer layout, wherein the original through-hole layer layout includes more than two original through-holes; A candidate position determination module is used to determine the candidate position of the additional through hole corresponding to each original through hole on the original through hole layer layout according to a preset feasible guide pattern, wherein the feasible guide pattern is a pattern corresponding to a through hole combination; the through hole combination includes two through holes arranged horizontally, three through holes arranged horizontally with equal spacing, two through holes arranged vertically, three through holes arranged vertically with equal spacing, four through holes whose hole centers are located at four vertices of a square, two through holes arranged at an angle of 45 degrees to the horizontal direction, three through holes arranged at an angle of 45 degrees to the horizontal direction with equal spacing, two through holes arranged at an angle of 135 degrees to the horizontal direction, and three through holes arranged at an angle of 135 degrees to the horizontal direction with equal spacing; A final position selection module, used for selecting a final position of the additional through hole in the candidate positions according to the manufacturing cost of the feasible guide pattern; a through-hole insertion module for inserting the additional through-hole at the final position; The through hole splitting module is used to split all through holes on the through hole layer layout after the additional through holes are inserted into more than two mask plates to obtain the final through hole layer layout.

11. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method according to any one of claims 1 to 9 when executing the computer program.

12. A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method according to any one of claims 1 to 9.

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