Data interface circuit and storage device

Abstract

The present disclosure provides a data interface circuit and a storage device, belonging to the field of memory technology. The data interface circuit includes at least one data pad, at least one first connection circuit, a clock pad, a second connection circuit and at least one latch, wherein each first connection circuit corresponds to each data pad one by one; the input end of the first connection circuit is connected to the corresponding data pad; the input end of the second connection circuit is connected to the clock pad; each latch corresponds to each first connection circuit one by one; the input end of the latch is connected to the output end of the corresponding first connection circuit, and the control end of the latch is connected to the output end of the second connection circuit; the delay time of each first connection circuit is within a set time range, and the path length of any first connection circuit is greater than the path length of the second connection circuit. The data interface circuit has a small power consumption.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a data interface circuit and a storage device. Background Art

[0002] In today's memory circuit design, for example, in the circuit design of DDR4 (fourth generation double data rate synchronous dynamic random access memory) DRAM (dynamic random access memory), the data pad and the clock pad are usually arranged in the same row. The clock signal on the clock pad is transmitted to the control end of the latch through the clock path, and the data signal of the data pad is transmitted to the input end of the latch through the data path, so that the data signal is latched in the latch by the clock signal and the output result is maintained.

[0003] In the prior art, latches are arranged in a one-to-one correspondence with each data pad, and are very close to the data pad but far away from the clock pad. However, since the clock path transmits a high-frequency clock signal, its power consumption is large, which increases the power consumption of the memory, limiting the improvement of the memory performance.

[0004] The above information disclosed in the Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may include information that does not constitute the prior art that is already known to one of ordinary skill in the art. Summary of the invention

[0005] The purpose of the present disclosure is to provide a data interface circuit and a storage device to reduce the power consumption of the data interface circuit.

[0006] In order to achieve the above-mentioned invention object, the present invention adopts the following technical solutions:

[0007] According to a first aspect of the present disclosure, there is provided a data interface circuit, comprising:

[0008] at least one data pad;

[0009] at least one first connection circuit, each of the first connection circuits corresponds to each of the data pads one by one; an input end of the first connection circuit is connected to the corresponding data pad;

[0010] Clock pad;

[0011] A second connection circuit, an input end of which is connected to the clock pad;

[0012] at least one latch, each latch corresponding to each first connection circuit one by one; an input end of the latch is connected to an output end of the corresponding first connection circuit, and a control end of the latch is connected to an output end of the second connection circuit;

[0013] The delay time of each of the first connection circuits is within a set time range, and the path length of any of the first connection circuits is greater than the path length of the second connection circuit.

[0014] In an exemplary embodiment of the present disclosure, any one of the first connection circuits includes:

[0015] A first lead, wherein an input end of the first lead is connected to the data pad, and an output end of the first lead is connected to an input end of the latch;

[0016] The virtual connection line is arranged between the input end and the output end of the first lead, and is used to make the parasitic capacitance and the parasitic resistance of the first connection circuit reach the target capacitance value and the target resistance value.

[0017] In an exemplary embodiment of the present disclosure, the material of the dummy line includes metal or polysilicon.

[0018] In an exemplary embodiment of the present disclosure, the material of the dummy wire is the same as that of the first lead wire.

[0019] In an exemplary embodiment of the present disclosure, the virtual line includes a rectangle, and one end of the rectangle is connected to the first lead.

[0020] In an exemplary embodiment of the present disclosure, at least one of the first connection circuits includes a plurality of the virtual lines.

[0021] In an exemplary embodiment of the present disclosure, any of the first connection circuits further includes:

[0022] The first buffer is arranged between the input end and the output end of the first lead.

[0023] In an exemplary embodiment of the present disclosure, the second connection circuit includes:

[0024] A second lead, an input end of the second lead connected to the clock pad, and an output end of the second lead connected to a control end of the latch;

[0025] The second buffer is arranged between the input end and the output end of the second lead.

[0026] According to a first aspect of the present disclosure, a storage device is provided, comprising the above-mentioned data interface circuit.

[0027] In an exemplary embodiment of the present disclosure, the storage device is a dynamic random access memory.

[0028] According to the data interface circuit provided by the present disclosure, the path length of the second connection circuit for connecting the clock pad and the control end of the latch is greater than the path length of the first connection circuit for connecting the data pad and the input end of the latch, so the path length of the second connection circuit is significantly reduced compared with the prior art. As a result, the capacitance and resistance of the second connection circuit itself and the parasitic capacitance and parasitic resistance formed by the surrounding environment can be significantly reduced, so the power consumption of the second connection circuit will be significantly reduced. Since the frequency of the clock signal transmitted on the second connection circuit is much greater than the data signal transmitted on the first connection circuit, the reduction in power consumption on the second connection circuit will be much greater than the increase in power consumption on the first connection circuit, so that the total power consumption of the entire data interface circuit is reduced, the restriction of power consumption on the data interface circuit is reduced, and it is convenient to improve the performance of the data interface circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0030] Figure 1 It is a structural diagram of a data interface circuit according to an embodiment of the present disclosure.

[0031] Figure 2 It is a structural schematic diagram of a data interface circuit according to another embodiment of the present invention.

[0032] The main component reference numerals in the figure include:

[0033] 1. Data pad; 2. First connection circuit; 21. First lead; 22. Virtual connection; 23. First buffer; 3. Clock pad; 4. Second connection circuit; 41. Second lead; 411. Main lead; 412. Branch lead; 42. Second buffer; 5. Latch. DETAILED DESCRIPTION

[0034] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure.

[0035] The described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, materials, etc. may be adopted. In other cases, known structures, materials or operations are not shown or described in detail to avoid blurring the main technical ideas of the present disclosure.

[0036] The terms "a", "an", etc. are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc. The terms "first" and "second" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0037] In the related art, the number of data pads and latches are multiple and one-to-one corresponding, and the latch is set close to the corresponding data pad to reduce the path length of the data path. However, this setting method makes the length of the clock path connecting the clock pad and the latch much longer than the data path, so that the clock path itself has a large capacitance and resistance, and can form a large parasitic capacitance and parasitic resistance with the surrounding environment, resulting in a large impedance of the clock path. Since the frequency of the clock signal is much greater than the data signal, the power consumption of the clock path is much greater than the power consumption on the data path.

[0038] In the embodiment of the present disclosure, a data interface circuit is provided, and the data interface circuit is used for data transmission. It can be understood that the data can be either address / command (ADDR / CMD) or data of other forms and functions.

[0039] like Figure 1 As shown, the data interface circuit includes at least one data pad 1 , at least one first connection circuit 2 , a clock pad 3 , a second connection circuit 4 and at least one latch 5 .

[0040] Among them, each first connection circuit 2 corresponds to each data pad 1 one by one; the input end of the first connection circuit 2 is connected to the corresponding data pad 1; the input end of the second connection circuit 4 is connected to the clock pad 3; each latch 5 corresponds to each first connection circuit 2 one by one; the input end of the latch 5 is connected to the output end of the corresponding first connection circuit 2, and the control end of the latch 5 is connected to the output end of the second connection circuit 4; the delay time of each first connection circuit 2 is within the set time range, and the path length of any first connection circuit 2 is greater than the path length of the second connection circuit 4.

[0041] According to the data interface circuit provided by the present disclosure, the path length of the second connection circuit 4 for connecting the clock pad 3 and the control end of the latch 5 is greater than the path length of the first connection circuit 2 for connecting the data pad 1 and the input end of the latch 5, so the path length of the second connection circuit 4 is significantly reduced compared with the prior art. As a result, the capacitance and resistance of the second connection circuit 4 itself and the parasitic capacitance and parasitic resistance formed by the surrounding environment can be significantly reduced, so the power consumption of the second connection circuit 4 will be significantly reduced. Since the frequency of the clock signal transmitted on the second connection circuit 4 is much greater than the data signal transmitted on the first connection circuit 2, the reduction in power consumption on the second connection circuit 4 will be much greater than the increase in power consumption on the first connection circuit 2, so that the total power consumption of the entire data interface circuit is reduced, the restriction of power consumption on the data interface circuit is reduced, and the performance of the data interface circuit is improved.

[0042] The following is a detailed description of the various components of the data interface circuit provided in the embodiment of the present disclosure in conjunction with the accompanying drawings:

[0043] like Figure 1 As shown, in one embodiment, the number of data pads 1 can be multiple, and each data pad 1 can be arranged in a row with the clock pad 3 to facilitate the connection of the external circuit. Of course, the data pads 1 can also be arranged in other ways, including but not limited to rectangular array arrangement, curved arrangement, etc.

[0044] The number of the data pads 1 can be determined according to the technical requirements of the data interface circuit, for example, it can be four, fourteen, etc., and the present disclosure does not make any special limitation on this.

[0045] It is understandable that the data pad 1 is used to connect to an external circuit to receive a data signal transmitted from the external circuit. The external circuit can be a circuit outside the device where the data interface circuit is located, or a circuit outside the device where the data interface circuit is located.

[0046] The first connection circuit 2 is used to connect the data pad 1 and the input end of the latch 5, and the delay time of each first connection circuit 2 is within a set time range. The delay time of each first connection circuit 2 needs to be basically consistent, so that the data on each data pad 1 can basically reach each latch 5 synchronously. The set time range can be set according to the technical requirements of the data interface circuit, and the present disclosure does not make any special limitation on this.

[0047] The path length of the first connection circuit 2 needs to be greater than the path length of the second connection circuit 4, so as to ensure that the path length of the second connection circuit 4 is significantly reduced. The path length of the first connection circuit 2 may refer to the length of the path that the data signal on the data pad 1 is transmitted to the corresponding latch 5. Correspondingly, the path length of the second connection circuit 4 may refer to the length of the path that the clock signal on the clock pad 3 is transmitted to the corresponding latch 5.

[0048] like Figure 1 As shown, the first connection circuit 2 may include a first lead 21 and a dummy line 22. The input end of the first lead 21 is connected to the data pad, and the output end of the first lead 21 is connected to the input end of the latch 5. The dummy line 22 is provided between the input end and the output end of the first lead 21, and is used to make the parasitic capacitance and parasitic resistance of the first connection circuit 2 reach the target capacitance value and the target resistance value.

[0049] It is understandable that the first lead 21 and / or the second lead 41 can be a lead made of the same conductive material or a lead made of multiple different conductive materials, and different conductive materials can be used at different positions. The first lead 21 and / or the second lead 41 can be arranged on the same layer, or on different layers through different methods such as via connections and bridge connections. The first lead 21 and / or the second lead 41 can also be changed in width and thickness according to changes in the surrounding environment to meet the performance requirements of the first connection circuit 2 and / or the second connection circuit 4.

[0050] The first lead 21 and / or the second lead 41 can be a continuous and uninterrupted lead, or a structure formed by directly connecting multiple different lead segments, or a structure formed by indirectly connecting with a conductive device. For example, when a conductive device is provided on the first lead 21, the first lead 21 is divided into at least two lead segments at the conductive device, wherein the lead segment close to the input end of the first lead 21 is connected to the input end of the conductive device, and the lead segment close to the output end of the first lead 21 is connected to the output end of the conductive device.

[0051] The virtual line 22 may be a sheet structure made of a conductive material and connected to the first lead 21. The virtual line 22 may form parasitic capacitance and parasitic resistance with the surrounding environment. Therefore, when the area, position, etc. of the virtual line 22 change, its parasitic capacitance and parasitic resistance will change, thereby changing the parasitic capacitance and parasitic resistance of the first connection circuit 2, resulting in a change in the delay time of the first connection circuit 2. Accordingly, different first leads 21 may cooperate with corresponding virtual lines 22 to ensure that the delay time of the first connection circuit 2 remains within a set time range.

[0052] Since the virtual line 22 can compensate for the parasitic capacitance and parasitic resistance of the first connection circuit 2, it is not necessary to make the first leads 21 of different first connection circuits 2 have the same parameters such as parasitic capacitance and parasitic resistance when laying out the first leads 21. Each first connection circuit 2 can flexibly set the first lead 21 according to the surrounding environment, the position of the data pad 1, the position of the latch 5 and other factors, so as to reduce the wiring complexity of the first lead 21 and reduce the path length of the first lead 21. According to the electrical parameters of the first lead 21, the various parameters of the first connection circuit 2 can be compensated by the corresponding virtual line 22, so that the delay time of the first connection circuit 2 is kept within the set time range.

[0053] The size of the virtual line 22 can be obtained by calculation. According to the requirements of each first connection circuit 2 for the delay time, that is, to make the delay time within the set time range, the target capacitance of each first connection circuit 2 can be calculated, and then the parasitic capacitance and parasitic resistance of the virtual line 22 on the first connection circuit 2 can be calculated to obtain the area of ​​the virtual line 22.

[0054] The material of the virtual line 22 can be selected from materials with good electrical conductivity, such as metal materials. It is understandable that the virtual line 22 can be made of not only a single material, but also a plurality of different conductive materials, or a combination of conductive structures composed of different conductive materials. For example, in one embodiment, the virtual line 22 can be a three-layer stacked structure of a molybdenum film layer, an aluminum film layer, and a molybdenum film layer.

[0055] The virtual wire 22 can be connected to the first lead 21, so the virtual wire 22 can be prepared at the same time when the portion where the first lead 21 and the virtual wire 22 are connected is prepared. In this way, the material of the virtual wire 22 is the same as that of the first lead 21, or the material of the virtual wire 22 is the same as that of the portion where the first lead 21 connects to the virtual wire 22. For example, in one embodiment, the virtual wire 22 and the portion where the first lead 21 and the virtual wire 22 are connected can be prepared on the substrate by a patterning process. The patterning process can generally include forming a conductive material film layer on the substrate, then forming a photoresist layer on the conductive material film layer, exposing using a mask, transferring the pattern on the mask to the photoresist layer, exposing to obtain a photoresist pattern, then removing the exposed portion of the conductive material film layer by etching, removing the residual photoresist layer, and then obtaining a pattern composed of conductive material. Of course, in other embodiments, the dummy line 22 and the portion where the first lead 21 is connected to the dummy line 22 may also be prepared by a lift-off process, a printing process, a vapor deposition process or other methods, which are not described in detail in the present disclosure.

[0056] The shape of the virtual line 22 can be a variety of different shapes within the scope allowed by the surrounding environment and the preparation process, for example, it can be rectangular, square, circular, elliptical or other shapes. It can be set on one side of the first lead 21, or it can be divided into two different parts by the first lead 21 that penetrates it.

[0057] For example, in one embodiment, Figure 1 As shown, the virtual line 22 is in the shape of a rectangle, and one short side of the rectangle is parallel to and connected to the first lead 21, so that the virtual line 22 is arranged on one side of the first lead 21. The width (i.e., the short side dimension) and length (i.e., the long side dimension) of the virtual line 22 of each first connection circuit 2 may be different.

[0058] In one embodiment, if Figure 2 As shown, there may be more than one virtual line 22 on at least one first connection circuit 2. In this way, a plurality of virtual lines 22 with relatively small areas may be used to replace a relatively large virtual line 22, thereby increasing the flexibility of setting the virtual line 22 and reducing the size restriction of the virtual line 22 by the surrounding environment of the first lead 21.

[0059] In one embodiment, if Figure 1 As shown, in order to improve the ability of the first connection circuit 2 to transmit data signals, a first buffer 23 may be further provided on the first connection circuit 2, and the first buffer 23 is provided between the input end and the output end of the first lead 21. The first buffer 23 may be provided close to the data pad 1. In other embodiments of the present disclosure, other devices, such as a driver, etc., may also be provided on the first connection circuit 2, and these other devices may also be provided on the first lead 21.

[0060] It can be understood that when a buffer, a driver or other device is set on the first lead 21, the changes in the electrical parameters of the first connection circuit 2 caused by the electrical parameters of all these devices (such as capacitance, resistance, etc.) can be compensated by the corresponding virtual connection 22, so that the delay time of the first connection circuit 2 is kept within the set time range.

[0061] The clock pad 3 is connected to the control terminals of the latches 5 through the second connection circuit 4 to achieve synchronous control of the latches 5. Since the clock signal has a high frequency, the second connection circuit 4 can minimize its path length within the allowable range to minimize its power consumption.

[0062] like Figure 1As shown, the second connection circuit 4 may include a second lead 41. The input end of the second lead 41 is connected to the clock pad 3, and the output end of the second lead 41 is connected to the control end of the latch 5. When the path length of the second lead 41 is relatively small, the resistance, parasitic capacitance and parasitic resistance of the second lead 41 are relatively small, so its power consumption is relatively low, which can reduce the power consumption of the data interface circuit.

[0063] In one embodiment, if Figure 1 As shown, the second lead 41 may include a main lead 411 and a plurality of branch leads 412, and each branch lead 412 is arranged in one-to-one correspondence with the latch 5. One end of each branch lead 412 is respectively connected to the corresponding latch 5, and the other end of each branch lead 412 is respectively connected to the main lead 411, and the main lead 411 is connected to the clock pad 3.

[0064] In another embodiment, Figure 1 As shown, the second connection circuit 4 may further include a second buffer 42, which may be disposed between the input end and the output end of the second lead 41 to improve the transmission capability of the clock signal in the second connection circuit 4. In a more specific embodiment, the second buffer 42 may be disposed on the main lead 411.

[0065] Of course, in other implementations, the second connection circuit 4 may further include other devices, such as a driver, etc.; these other devices may be disposed on the second lead 41 .

[0066] It can be understood that the smaller the path length of the second connection circuit 4, the smaller the loss of the clock signal thereon will be, the fewer auxiliary devices (such as buffers, drivers, etc.) required to improve the clock signal transmission capability will be, and the power consumption generated by fewer auxiliary devices will be smaller, thereby reducing the power consumption of the second connection circuit 4.

[0067] The present disclosure also provides a storage device, which includes the data interface circuit described in the above data interface circuit implementation. The storage device can be a random access memory (RAM), a read-only memory (ROM), a flash memory (FlashMemory), a first-in-first-out memory (FIFO), a first-in-last-out memory (FILO) or other types of memory. For example, the storage device can be a DDR4 dynamic random access memory (DRAM).

[0068] The data interface circuit used in the storage device of the embodiment of the present disclosure is the same as the data interface circuit in the embodiment of the above-mentioned data interface circuit, and therefore has the same beneficial effects, which will not be described in detail here.

[0069] It should be understood that the present disclosure does not limit its application to the detailed structure and arrangement of the components proposed in this specification. The present disclosure can have other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments described in this specification illustrate the best mode known for implementing the present disclosure and will enable those skilled in the art to utilize the present disclosure.

Claims

1. A data interface circuit, characterized in that: include: at least one data pad; at least one first connection circuit, each of the first connection circuits corresponds to each of the data pads one by one; an input end of the first connection circuit is connected to the corresponding data pad; Clock pad; A second connection circuit, an input end of which is connected to the clock pad; at least one latch, each latch corresponding to each first connection circuit one by one; an input end of the latch is connected to an output end of the corresponding first connection circuit, and a control end of the latch is connected to an output end of the second connection circuit; The delay time of each of the first connection circuits is within a set time range, and the path length of any of the first connection circuits is greater than the path length of the second connection circuit.

2. The data interface circuit according to claim 1, characterized in that: Any of the first connection circuits comprises: A first lead, wherein an input end of the first lead is connected to the data pad, and an output end of the first lead is connected to an input end of the latch; The virtual connection line is arranged between the input end and the output end of the first lead, and is used to make the parasitic capacitance and the parasitic resistance of the first connection circuit reach the target capacitance value and the target resistance value.

3. The data interface circuit according to claim 2, characterized in that: The material of the dummy line includes metal or polysilicon.

4. The data interface circuit according to claim 3, characterized in that: The material of the dummy wire is the same as that of the first lead wire.

5. The data interface circuit according to claim 3, characterized in that: The virtual line shape includes a rectangle, and one end of the rectangle is connected to the first lead.

6. The data interface circuit according to claim 3, characterized in that: At least one of the first connection circuits includes a plurality of the virtual wires.

7. The data interface circuit according to claim 3, characterized in that: Any of the first connection circuits further comprises: The first buffer is arranged between the input end and the output end of the first lead.

8. The data interface circuit according to claim 1, characterized in that: The second connection circuit comprises: A second lead, an input end of the second lead connected to the clock pad, and an output end of the second lead connected to a control end of the latch; The second buffer is arranged between the input end and the output end of the second lead.

9. A storage device, comprising the data interface circuit according to any one of claims 1 to 8.

10. The storage device according to claim 9, characterized in that: The storage device is a dynamic random access memory.

Images