A display power isolation circuit with correct power-on and power-off timing sequence

Abstract

A display power supply isolation circuit with a correct power-on and power-off timing sequence includes a DC-DC chip, a voltage doubling circuit, a startup capacitor, a time-delay capacitor, and an isolation diode. The input end of the DC-DC chip is respectively connected to an external power supply VCC and a voltage doubling circuit, and the output end outputs three voltages of AVDD, VGH, and VGL respectively; at the same time, the enable end EN of the DC-DC chip is also connected to the startup capacitor; the three voltages of AVDD, VGH, and VGL are used to drive the liquid crystal pixel switch tube of the liquid crystal display. The time-delay capacitor is connected between the display total power supply LCD_VCC and the power ground LCD_GNG. The correct power-on and power-off timing sequence of the liquid crystal display that fully meets the requirements of the liquid crystal display driver IC is realized, and at the same time, the power supply of the DC-DC drive circuit is isolated from the power supply of the liquid crystal display to prevent the DC-DC drive circuit from interfering with the display due to factors such as unstable voltage and current of the liquid crystal display, resulting in damage to the display and image display failure. The circuit design can be realized by only one set of DC-DC circuits, two capacitors, and one diode, which is extremely cost-saving.

Description

Technical Field

[0001] The invention relates to the technical field of liquid crystal displays, and in particular to a display power supply isolation circuit with a correct power-on and power-off timing sequence. Background Art

[0002] In an era of frequent human-computer interaction, displays are an important component. Liquid crystal displays (also known as LCD or TFT liquid crystal displays) appear more and more frequently among displays. From small portable screens to large screens for video projection, LCD displays are indispensable.

[0003] The driving of LCD requires two power sources: LCD power supply and LCD DC-DC drive circuit. At present, when a single power supply is used to drive the LCD and DC-DC drive circuit, it is difficult to ensure the correct power-on and power-off timing of the LCD that meets the requirements of the LCD driver IC. If necessary, two power supplies must be used to drive in sequence, or the drive must be controlled by single-chip software, which increases the cost. Summary of the invention

[0004] In order to solve the technical problems raised by the background technology, the present invention provides a display power isolation circuit with correct power-on and power-off timing, which is a low-cost display power isolation circuit design with correct power-on and power-off timing, and can realize a driving circuit with correct power-on and power-off timing of a liquid crystal display that fully meets the requirements of the liquid crystal display driver IC, and at the same time, the power supply of the DC-DC driving circuit is isolated from the power supply of the liquid crystal display to prevent the DC-DC driving circuit from interfering with the display due to factors such as unstable voltage and current of the liquid crystal display, resulting in damage to the display and image display failure. The circuit design can be realized by only one set of DC-DC circuits, two capacitors, and one diode, which is extremely cost-saving.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] A display power supply isolation circuit with a correct power-on and power-off timing sequence comprises a DC-DC chip (1), a voltage doubling circuit (2), a start-up capacitor (3), a delay capacitor (4), and an isolation diode (5).

[0007] The input end of the DC-DC chip (1) is respectively connected to an external power supply VCC and a voltage doubling circuit (2), and the output end outputs three voltages of AVDD, VGH and VGL respectively; at the same time, the enable end EN of the DC-DC chip (1) is also connected to a start capacitor (3); the three voltages of AVDD, VGH and VGL are used to drive a liquid crystal pixel switch tube of a liquid crystal display. The AVDD voltage is the power supply voltage of the pixel switch tube, VGH is the turn-on voltage of the pixel switch tube, and VGL is the turn-off voltage of the pixel switch tube.

[0008] The delay capacitor (4) is connected between the display main power supply LCD_VCC and the power ground LCD_GNG.

[0009] The anode of the isolation diode (5) is connected to the external power supply VCC, and the cathode is connected to the display main power supply LCD_VCC.

[0010] Furthermore, the DC-DC chip (1) is MP1530, and the SW terminal of MP1530 ​​outputs the AVDD voltage.

[0011] Furthermore, the voltage doubling circuit (2) comprises two groups of voltage doubling circuits, wherein the voltage output end of the first group of voltage doubling circuits is connected to the IN3 pin of MP1530, and the VGH pin corresponding to the IN3 pin outputs the VGH voltage, and at the same time, the output VGH voltage signal is also fed back to the FB3 pin of MP1530; the voltage output end of the second group of voltage doubling circuits is connected to the IN2 pin of MP1530, and the VGL pin corresponding to the IN2 pin outputs the VGL voltage, and at the same time, the output VGL voltage signal is also fed back to the FB2 pin of MP1530.

[0012] Furthermore, the delay capacitor (4) is an electrolytic capacitor of 1000uF or more.

[0013] Compared with the prior art, the present invention has the following beneficial effects:

[0014] 1) The circuit design of the present invention avoids the situation that the display cannot be started and shut down according to the correct power-on and power-off sequence when only a single power supply can be used to drive the liquid crystal display, thereby protecting the service life of the liquid crystal display, optimizing the display effect of the display when starting and shutting down, and preventing undesirable phenomena such as screen flickering and screen distortion. There is no need to use other programming ICs to control multiple power supplies. It can be achieved by only one set of DC-DC circuits, two capacitors, and one diode, greatly saving software and hardware costs. This circuit design can be applied to all power supply circuits that require multiple power supplies.

[0015] 2) The starting capacitor is used to delay the start of the DC-DC circuit, and utilizes the delayed power-on function of the capacitor to realize the delayed power-on function of the three voltages of AVDD, VGH, and VGL; the delay capacitor utilizes the energy storage function of the capacitor to maintain the voltage for a period of time after power failure, thereby realizing the delayed power-off function of the display's total power supply LCD_VCC; the isolation diode can prevent LCD_VCC from returning to the power supply VCC while the LCD_VCC voltage is maintained after the power supply VCC disappears. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic diagram of the power-on sequence specified by the LCD;

[0017] Figure 2 This is a schematic diagram of the power-off sequence specified by the LCD;

[0018] Figure 3 It is a circuit diagram of the DC-DC chip circuit outputting AVDD, VGH, and VGL of the present invention;

[0019] Figure 4 It is a delayed power-off circuit diagram of the display main power supply LCD_VCC of the present invention.

[0020] In the figure: 1-DC-DC chip 2-voltage doubler circuit 3-start capacitor 4-delay capacitor 5-isolation diode. DETAILED DESCRIPTION

[0021] The specific implementation modes provided by the present invention are described in detail below with reference to the accompanying drawings.

[0022] The LCD is composed of multiple pixels, three sub-pixels make up one pixel, each sub-pixel is composed of a switch tube, and each switch tube is driven by AVDD, VGH, and VGL voltages. AVDD is the power supply voltage of the pixel switch tube, VGH is the switching voltage, and VGL is the shutdown voltage. In addition, there is the total power supply voltage LCD_VCC of the LCD.

[0023] 1) First: AVDD, VGH, VGL voltages and the total power supply voltage LCD_VCC need to have a correct power-on and power-off sequence, as follows:

[0024] like Figure 1 As shown in the figure, the correct power-on sequence is: first start the LCD_VCC total power supply voltage, then start the DC-DC circuit to generate AVDD, VGH, and VGL voltages;

[0025] like Figure 2 As shown in the figure, the correct power-off sequence is: first turn off the DC-DC circuit to generate AVDD, VGH, and VGL voltages, and then turn off the LCD_VCC total power supply voltage.

[0026] Most of the time we can only use one power supply to drive these voltages, which cannot provide the correct power-up and power-down sequence for the LCD. This can be achieved by using the energy storage characteristics of capacitors.

[0027] 2) AVDD, VGH, VGL voltages. It is not economical to generate these voltages with multiple DC-DC circuits. You can use the MP1530 ​​IC and add 2 voltage doubling circuits to generate them. Specific embodiment:

[0029] like Figure 3As shown, a display power isolation circuit with a correct power-on and power-off timing sequence comprises a DC-DC chip (1), a voltage doubling circuit (2), a start-up capacitor (3), a delay capacitor (4), and an isolation diode (5).

[0030] The input end of the DC-DC chip (1) is respectively connected to an external power supply VCC and a voltage doubling circuit (2), and the output end outputs three voltages of AVDD, VGH and VGL respectively; the three voltages of AVDD, VGH and VGL are used to drive a liquid crystal pixel switch tube of a liquid crystal display.

[0031] At the same time, the enable terminal EN of the DC-DC chip (1) is also connected to a start-up capacitor (3); the start-up capacitor (3) is used to delay starting the DC-DC circuit, and utilizes the delayed power-on function of the capacitor to realize the delayed power-on function of the three voltages of AVDD, VGH and VGL.

[0032] like Figure 3 As shown, the DC-DC chip (1) is MP1530, and the SW terminal of MP1530 ​​outputs the AVDD voltage.

[0033] The voltage doubling circuit (2) comprises two groups of voltage doubling circuits. The first group of voltage doubling circuits and the second group of voltage doubling circuits are connected in series and then connected between the SW output terminal of MP1530 ​​and the power ground.

[0034] The first voltage doubling circuit is composed of diodes D3, D4, D5, and D6 connected in series. The voltage output end of the first voltage doubling circuit is connected to the IN3 pin of MP1530. The VGH pin corresponding to the IN3 pin outputs the VGH voltage. At the same time, the output VGH voltage signal is also fed back to the FB3 pin of MP1530. The second voltage doubling circuit is composed of diodes D7, D8, D9, and D10 connected in series. The voltage output end of the second voltage doubling circuit is connected to the IN2 pin of MP1530. The VGL pin corresponding to the IN2 pin outputs the VGL voltage. At the same time, the output VGL voltage signal is also fed back to the FB2 pin of MP1530.

[0035] like Figure 4 As shown, the delay capacitor (4) is connected between the display main power supply LCD_VCC and the power ground LCD_GNG. The delay capacitor (4) utilizes the energy storage function of the capacitor to maintain the voltage for a period of time after power failure, thereby realizing the delay power-off function of the display main power supply LCD_VCC. The delay capacitor (4) adopts an electrolytic capacitor of 1000uF or more.

[0036] The positive electrode of the isolation diode (5) is connected to the external power supply VCC, and the negative electrode is connected to the display main power supply LCD_VCC. The isolation diode (5) can prevent LCD_VCC from returning to the power supply VCC when the power supply VCC disappears and the LCD_VCC voltage is maintained. The isolation diode (5) can use a common Schottky diode.

[0037] The above embodiments are implemented based on the technical solution of the present invention, and detailed implementation methods and specific operation processes are given, but the protection scope of the present invention is not limited to the above embodiments. The methods used in the above embodiments are conventional methods unless otherwise specified.

Claims

1. A display power isolation circuit with correct power-on and power-off timing, characterized in that: It includes a DC-DC chip (1), a voltage doubling circuit (2), a starting capacitor (3), a delay capacitor (4), and an isolation diode (5); The input end of the DC-DC chip (1) is respectively connected to an external power supply VCC and a voltage doubling circuit (2), and the output end outputs a first voltage AVDD, a second voltage VGH, and a third voltage VGL; at the same time, the enable end EN of the DC-DC chip (1) is also connected to a start-up capacitor (3); the first voltage AVDD, the second voltage VGH, and the third voltage VGL are used to drive a liquid crystal pixel switch tube of a liquid crystal display; The delay capacitor (4) is connected between the display main power supply LCD_VCC and the power ground LCD_GNG; The positive electrode of the isolation diode (5) is connected to the external power supply VCC, and the negative electrode is connected to the display main power supply LCD_VCC; The delay capacitor (4) is an electrolytic capacitor of 1000uF or more; The AVDD voltage is the power supply voltage of the liquid crystal pixel switch tube, the VGH voltage is the turn-on voltage of the liquid crystal pixel switch tube, and the VGL voltage is the turn-off voltage of the liquid crystal pixel switch tube.

2. A display power isolation circuit with correct power-on and power-off timing sequence according to claim 1, characterized in that: The DC-DC chip (1) is MP1530, and the SW terminal of MP1530 ​​outputs the AVDD voltage.

3. A display power isolation circuit with correct power-on and power-off timing sequence according to claim 2, characterized in that: The voltage doubling circuit (2) comprises two groups of voltage doubling circuits. The voltage output end of the first group of voltage doubling circuits is connected to the IN3 pin of MP1530, and the VGH pin corresponding to the IN3 pin outputs the VGH voltage. At the same time, the output VGH voltage signal is also fed back to the FB3 pin of MP1530. The voltage output end of the second group of voltage doubling circuits is connected to the IN2 pin of MP1530, and the VGL pin corresponding to the IN2 pin outputs the VGL voltage. At the same time, the output VGL voltage signal is also fed back to the FB2 pin of MP1530.

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