A power tube overcurrent protection circuit

Abstract

The present invention discloses a power tube overcurrent protection circuit, comprising an overcurrent detection circuit, a timing control circuit and an enabling control circuit, wherein the overcurrent detection circuit is used to detect whether a controlled power tube has overcurrent; the timing control circuit and the enabling control circuit jointly control the controlled power tube. The present invention can protect the controlled power tube by shutting down the controlled power tube when an overcurrent occurs in the controlled power tube used to control whether a load works or not.

Description

Technical Field

[0001] The invention relates to the field of electronic circuits, and in particular to an overcurrent protection circuit for a power tube. Background Art

[0002] In the field of electronic circuits, power tubes are often used as switching devices to control the back-end load circuit. The on and off of the power tubes is used to control whether the back-end load circuit is working or not. During use, if the load is short-circuited and the current of the power tube is too large, the power tube is easily damaged, causing the entire circuit to stop working. Summary of the invention

[0003] The object of the present invention is to provide a power tube overcurrent protection circuit, which can shut down the controlled power tube to protect the controlled power tube when an overcurrent occurs in the controlled power tube.

[0004] In order to achieve the above object, the solution of the present invention is:

[0005] A power tube overcurrent protection circuit is applied to a power tube control circuit, wherein the power tube control circuit includes a load and a controlled power tube for controlling whether the load works or not; the power tube overcurrent protection circuit includes:

[0006] An overcurrent detection circuit is connected to the controlled power tube; the overcurrent detection circuit is used to detect whether the controlled power tube has overcurrent; if the controlled power tube has overcurrent, the output end of the overcurrent detection circuit outputs an overcurrent signal; and if the controlled power tube has no overcurrent, the output end of the overcurrent detection circuit outputs a normal signal;

[0007] A timing control circuit is connected to the output end of the overcurrent detection circuit; when the timing control circuit is powered on, the output end of the timing control circuit outputs an on signal; after the timing control circuit is powered on, the output end signal of the timing control circuit is controlled according to the signal output from the output end of the overcurrent detection circuit; if the output end of the overcurrent detection circuit outputs an overcurrent signal, the output end of the timing control circuit continuously outputs a shutoff signal within a set time and re-outputs an on signal after the set time is reached; if the output end of the overcurrent detection circuit outputs a normal signal, the output end of the timing control circuit keeps outputting the on signal;

[0008] An enable control circuit is connected to the output end of the timing control circuit and the gate of the controlled power tube respectively; the enable control circuit is used to control the on and off of the controlled power tube, and the enable control circuit is controlled by a signal output from the output end of the timing control circuit and an enable signal; as long as the enable control circuit receives a shutdown signal output by the timing control circuit, the enable control circuit shuts down the controlled power tube; and when the enable control circuit receives a valid enable signal and a start signal output by the timing control circuit at the same time, the enable control circuit turns on the controlled power tube.

[0009] The timing control circuit is connected to the overcurrent detection circuit through a signal conversion circuit; the overcurrent signal is a low-level signal, and the normal signal is a high-level signal; the input end of the signal conversion circuit is connected to the output end of the overcurrent detection circuit; the signal conversion circuit is used to perform level conversion on the signal output from the output end of the overcurrent detection circuit, the signal conversion circuit converts the high-level normal signal into a low-level hold signal and outputs it to the input end of the timing control circuit, and the signal conversion circuit converts the low-level overcurrent signal into a high-level trigger signal and outputs it to the input end of the timing control circuit; the input end of the timing control circuit is connected to the output end of the signal conversion circuit; after the timing control circuit is powered on, if the input end of the timing control circuit receives a hold signal, the output end of the timing control circuit keeps outputting an on signal; and if the signal received at the input end of the timing control circuit changes from a hold signal to a trigger signal, the output end of the timing control circuit continuously outputs a shut-down signal within a set time and re-outputs an on signal after the set time is reached.

[0010] The controlled power tube is a PMOS tube, the source of which is connected to a first DC power supply, and the drain of which is connected to the load; the overcurrent detection circuit comprises a second switch tube, a second current source and a comparator; the second switch tube is a PMOS tube, and the transconductance of the second switch tube is smaller than the transconductance of the controlled power tube; the source of the second switch tube is connected to the first DC power supply, the gate of the second switch tube is connected to the gate of the controlled power tube and the output end of the enable control circuit, the drain of the second switch tube is connected to the negative input end of the comparator and is grounded through the second current source; the positive input end of the comparator is connected to the drain of the controlled power tube, the output end of the comparator serves as the output end of the overcurrent detection circuit, the power supply end of the comparator is connected to the first DC power supply, and the ground end of the comparator is connected to the virtual ground circuit.

[0011] The virtual ground circuit includes a fourth switch tube, a fourth resistor, a third current source, and a fourth current source, wherein the fourth switch tube is a PMOS tube; wherein one end of the fourth resistor is connected to the first DC power supply, the other end of the fourth resistor is connected to the input end of the third current source and the gate of the fourth switch tube, the source of the fourth switch tube is connected to the ground end of the comparator, the drain of the fourth switch tube is connected to the input end of the fourth current source, and the output end of the third current source and the output end of the fourth current source are grounded.

[0012] The signal conversion circuit includes a third switch tube, a first resistor, a second resistor, a third resistor, a first capacitor and a Schmitt trigger, wherein the third switch tube is a PMOS tube; wherein the source of the third switch tube is connected to the first DC power supply, the gate of the third switch tube serves as the input end of the signal conversion circuit, the drain of the third switch tube is connected to one end of the first resistor, the other end of the first resistor is connected to one end of the third resistor and is grounded through the second resistor, the other end of the third resistor is connected to the input end of the Schmitt trigger and is grounded through the first capacitor, and the output end of the Schmitt trigger serves as the output end of the signal conversion circuit.

[0013] The enable control circuit includes an AND gate, a first current source, a current limiting resistor and a first switch tube, wherein the first switch tube is an NMOS tube; wherein the first input end of the AND gate is used to access an enable signal, the second input end of the AND gate is used to connect to the output end of the timing control circuit, and the output end of the AND gate is connected to the gate of the first switch tube; one end of the current limiting resistor is connected to a first DC power supply, the other end of the current limiting resistor is connected to the drain of the first switch tube, and the source of the first switch tube is grounded through the first current source; the common end of the current limiting resistor and the first switch tube is connected to the gate of the controlled power tube as the output end of the enable control circuit.

[0014] The controlled power tube is an NMOS tube, the input end of the load is connected to a first DC power supply, the drain of the controlled power tube is connected to the output end of the load, and the source of the controlled power tube is grounded; the overcurrent detection circuit includes a second switch tube, a second current source and a comparator; the second switch tube is an NMOS tube, and the transconductance of the second switch tube is smaller than the transconductance of the controlled power tube; the input end of the second current source is connected to the first DC power supply, the output end of the second current source is connected to the drain of the second switch tube and the positive input end of the comparator, the gate of the second switch tube is connected to the gate of the controlled power tube and the output end of the enable control circuit, and the source of the second switch tube is grounded; the negative input end of the comparator is connected to the drain of the controlled power tube, the power supply end of the comparator is connected to a second DC power supply, and the ground end of the comparator is grounded.

[0015] The signal conversion circuit includes a third switch tube, a first resistor, a second resistor, a third resistor, a first capacitor and a Schmitt trigger, wherein the third switch tube is a PMOS tube; wherein the source of the third switch tube is connected to the second DC power supply, the gate of the third switch tube serves as the input end of the signal conversion circuit, the drain of the third switch tube is connected to one end of the first resistor, the other end of the first resistor is connected to one end of the third resistor and is grounded through the second resistor, the other end of the third resistor is connected to the input end of the Schmitt trigger and is grounded through the first capacitor, and the output end of the Schmitt trigger serves as the output end of the signal conversion circuit.

[0016] The enable control circuit includes an AND gate; wherein the first input end of the AND gate is used to access the enable signal, the second input end of the AND gate is used to connect to the output end of the timing control circuit, and the output end of the AND gate is connected to the gate of the controlled power tube as the output end of the enable control circuit.

[0017] The timing control circuit includes a D flip-flop and a counter; wherein the input end of the D flip-flop is connected to a second DC power supply, the clock end of the D flip-flop is connected to an enable end of the counter and serves as the input end of the timing control circuit, the output end of the counter is connected to a reset end of the D flip-flop, and the negative output end of the D flip-flop serves as the output end of the timing control circuit.

[0018] After adopting the above scheme, when the controlled power tube has an overcurrent, the timing control circuit of the present invention can output a shutdown signal to the enabling control circuit, so that the enabling control circuit shuts down the controlled power tube, thereby realizing overcurrent protection and preventing the controlled power tube from being damaged due to excessive current. In addition, after the controlled power tube has an overcurrent, the timing control circuit of the present invention continuously outputs a shutdown signal to the enabling control circuit within a set time, and then re-outputs a start signal to the enabling control circuit, so that the enabling control circuit can control the controlled power tube to turn on again, realizing automatic restart of the controlled power tube; after the controlled power tube is turned on again, if the controlled power tube does not have an overcurrent, the controlled power tube works normally and the circuit returns to a normal working state, and if the controlled power tube still has an overcurrent, the timing control circuit and the enabling control circuit will shut down the controlled power tube again to protect the controlled power tube. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a circuit diagram of Embodiment 1 of the present invention;

[0020] Figure 2 This is a circuit diagram of Embodiment 2 of the present invention;

[0021] Description of labels:

[0022] Overcurrent detection circuit 1, second switch tube Q2, second current source I2, comparator U2,

[0023] Virtual ground circuit 11, fourth switch tube Q4, fourth resistor R4, third current source I3, fourth current source I4,

[0024] Timing control circuit 2, D flip-flop U4, counter U5,

[0025] Enable control circuit 3, AND gate U1, first current source I1, current limiting resistor RT, first switch tube Q1,

[0026] Signal conversion circuit 4, third switch tube Q3, first resistor R1, second resistor R2, third resistor R3, first capacitor C1, Schmitt trigger U3,

[0027] Power tube control circuit 5, load 51, controlled power tube M1,

[0028] A first DC power supply VDD, a second DC power supply VCC, and an enable signal EN. DETAILED DESCRIPTION

[0029] like Figure 1 and Figure 2 As shown, the present invention discloses a power tube overcurrent protection circuit, which is applied to a power tube control circuit 5. The power tube control circuit 5 includes a load 51 and a controlled power tube M1 for controlling whether the load 51 works or not.

[0030] Cooperate Figure 1 and Figure 2 As shown, a power tube overcurrent protection circuit of the present invention includes an overcurrent detection circuit 1, a timing control circuit 2 and an enable control circuit 3.

[0031] Cooperate Figure 1 and Figure 2 As shown, the overcurrent detection circuit 1 is connected to the controlled power tube M1, and the overcurrent detection circuit 1 is used to detect whether the controlled power tube M1 is overcurrent; if the controlled power tube is overcurrent, the output end of the overcurrent detection circuit 1 outputs an overcurrent signal; and if the controlled power tube M1 is not overcurrent, the output end of the overcurrent detection circuit 1 outputs a normal signal.

[0032] Cooperate Figure 1 and Figure 2 As shown, the timing control circuit 2 is connected to the output end of the overcurrent detection circuit 1. When the timing control circuit 2 is powered on, the output end of the timing control circuit 2 outputs a start signal. After the timing control circuit 2 is powered on, the output end signal of the timing control circuit 2 is controlled according to the signal output from the output end of the overcurrent detection circuit 1. If the output end of the overcurrent detection circuit 1 outputs an overcurrent signal, the output end of the timing control circuit 2 continuously outputs a shutdown signal within a set time and re-outputs a start signal after the set time is reached. If the output end of the overcurrent detection circuit 1 outputs a normal signal, the output end of the timing control circuit 2 keeps outputting the start signal. Figure 1 and Figure 2As shown, the overcurrent signal is a low-level signal, while the normal signal is a high-level signal; the timing control circuit 2 can be connected to the overcurrent detection circuit 1 through a signal conversion circuit 4; the input end of the signal conversion circuit 4 is connected to the output end of the overcurrent detection circuit 1; the signal conversion circuit 4 is used to perform level conversion on the signal output from the output end of the overcurrent detection circuit 1, the signal conversion circuit 4 converts the high-level normal signal into a low-level holding signal and outputs it to the input end of the timing control circuit 2, and the signal conversion circuit 4 converts the low-level overcurrent signal into a high-level trigger signal and outputs it to the input end of the timing control circuit 2; the input end of the timing control circuit 2 is connected to the output end of the signal conversion circuit 4; after the timing control circuit 2 is powered on, if the input end of the timing control circuit 2 receives the holding signal, the output end of the timing control circuit 2 keeps outputting the start signal; and if the signal received at the input end of the timing control circuit 2 changes from the holding signal to the trigger signal, the output end of the timing control circuit 2 continuously outputs a shutdown signal within the set time and re-outputs the start signal after the set time is reached.

[0033] Cooperate Figure 1 and Figure 2 As shown, the enable control circuit 3 is connected to the output end of the timing control circuit 2 and the gate of the controlled power tube respectively; the enable control circuit 3 is used to control the on and off of the controlled power tube M1, and the enable control circuit 3 is controlled by the signal output from the output end of the timing control circuit 2 and an enable signal EN; as long as the enable control circuit 3 receives the shutdown signal output by the timing control circuit 2, the enable control circuit 3 shuts down the controlled power tube M1; and when the enable control circuit 3 receives the valid enable signal EN and the start signal output by the timing control circuit 2 at the same time, the enable control circuit 3 turns on the controlled power tube M1.

[0034] Cooperate Figure 1 and Figure 2 As shown, the working principle of the present invention is:

[0035] When the present invention starts working, the timing control circuit 2 outputs a start signal to the enable control signal, and at the same time the enable control circuit 3 receives a valid enable signal EN, so that the enable control circuit 3 controls the controlled power tube M1 to turn on;

[0036] After the controlled power tube M1 is turned on, if the current of the controlled power tube M1 is normal, the overcurrent detection circuit 1 outputs a normal signal to the signal conversion circuit 4, and the signal conversion circuit 4 converts the received normal signal into a holding signal and outputs the holding signal to the timing control circuit 2. The input end of the timing control circuit 2 receives the holding signal and keeps outputting the start signal to the enable control circuit 3, thereby ensuring that the controlled power tube M1 is turned on;

[0037] After the controlled power tube M1 is turned on, if the controlled power tube M1 has an overcurrent, the overcurrent detection circuit 1 outputs an overcurrent signal to the signal conversion circuit 4. The signal conversion circuit 4 converts the received overcurrent signal into a trigger signal and outputs the trigger signal to the timing control circuit 2. The signal received at the input end of the timing control circuit 2 changes from a holding signal to a trigger signal. The timing control circuit 2 outputs a shutdown signal to the enable control circuit 3 within a set time, so that the enable control circuit 3 turns off the controlled power tube M1, thereby realizing overcurrent protection and preventing the controlled power tube M1 from being damaged due to excessive current. The timing control After the circuit 2 outputs a shutdown signal to the enable control circuit 3 within the set time, the timing control circuit 2 will re-output a start signal to the enable control circuit 3, so that the enable control circuit 3 can control the controlled power tube M1 to turn on again, so that the controlled power tube M1 is restarted; after the controlled power tube M1 is turned on again, if the controlled power tube M1 does not have an overcurrent, the controlled power tube M1 works normally and the circuit returns to a normal working state, and if the controlled power tube M1 still has an overcurrent, the timing control circuit 2 and the enable control circuit 3 will turn off the controlled power tube M1 again to protect the controlled power tube M1.

[0038] In order to further explain the technical solution of the present invention, the present invention is described in detail below through two embodiments.

[0039] Embodiment 1:

[0040] Cooperate Figure 1 As shown, in the first embodiment of the present invention, the controlled power tube M1 of the power tube control circuit 5 is a PMOS tube, the source of the controlled power tube M1 is connected to a first DC power supply VDD, and the drain of the controlled power tube M1 is connected to the load 51.

[0041] Cooperate Figure 1As shown, in the first embodiment of the present invention, the overcurrent detection circuit 1 includes a second switch tube Q2, a second current source I2 and a comparator U2, the second switch tube Q2 is a PMOS tube, and the transconductance of the second switch tube Q2 is less than the transconductance of the controlled power tube M1; wherein the source of the second switch tube Q2 is connected to the first DC power supply VDD, the gate of the second switch tube Q2 is connected to the gate of the controlled power tube M1 and the output end of the enable control circuit 3, the drain of the second switch tube Q2 is connected to the negative input end of the comparator U2 and is grounded through the second current source I2; the positive input end of the comparator U2 is connected to the output end of the controlled power tube M1, and the output end of the comparator U2 is connected to the signal conversion circuit 4 as the output end of the overcurrent detection circuit 1; in this way, when the enable control circuit 3 controls the controlled power tube M1 to turn on, the second switch tube Q2 is also turned on synchronously; when the enable control circuit 3 controls the controlled power tube M1 to turn off, the second switch tube Q2 can also be turned off synchronously, thereby reducing energy consumption. In addition, since the sources of the second switch tube Q2 and the controlled power tube M1 are both connected to the first DC power supply VDD, the gates of the second switch tube Q2 and the controlled power tube M1 are both connected to the output end of the enable control circuit 3, and the second switch tube Q2 and the controlled power tube M1 are the same type of field effect tubes, when the controlled power tube M1 and the second switch tube Q2 are turned on, if the drain voltages of the controlled power tube M1 and the second switch tube Q2 are equal, that is, the positive input terminal voltage of the comparator U2 is equal to the negative input terminal voltage of the comparator U2, at this time, the current of the controlled power tube M1 is N times the current of the second switch tube Q2, and N is equal to the transconductance of the controlled power tube M1 divided by the transconductance of the second switch tube Q2; and if the drain voltage of the controlled power tube M1 is less than the drain voltage of the second switch tube Q2, that is, the positive input terminal voltage of the comparator U2 is less than the negative input terminal voltage of the comparator U2, at this time, the current of the controlled power tube M1 is greater than N times the current of the second switch tube Q2. times, the comparator U2 outputs a low-level overcurrent signal; and if the drain voltage of the controlled power tube M1 is greater than the drain voltage of the second switch tube Q2, that is, the positive input terminal voltage of the comparator U2 is greater than the negative input terminal voltage of the comparator U2, at this time, the current of the controlled power tube M1 is less than N times the current of the second switch tube Q2, and the comparator U2 outputs a high-level normal signal; in this way, N times the current of the second switch tube Q2 is set as the overcurrent threshold of the controlled power tube M1. When the controlled power tube M1 does not have an overcurrent, the current of the controlled power tube M1 is less than the overcurrent threshold, then the positive input terminal voltage of the comparator U2 is greater than the negative input terminal voltage of the comparator U2, and at this time the comparator U2 outputs a high-level normal signal; and if the controlled power tube M1 has an overcurrent, the current of the controlled power tube M1 is greater than the overcurrent threshold, then the positive input terminal voltage of the comparator U2 is less than the negative input terminal voltage of the comparator U2, and at this time the comparator U2 outputs a low-level overcurrent signal.

[0042] Cooperate Figure 1As shown, in the first embodiment of the present invention, the power supply end of the comparator U2 of the overcurrent detection circuit 1 is connected to the first DC power supply VDD, and the ground end of the comparator U2 is connected to the virtual ground circuit 11; wherein the virtual ground circuit 11 includes a fourth switch tube Q4, a fourth resistor R4, a third current source I3, and a fourth current source I4, and the fourth switch tube Q4 is a PMOS tube; wherein one end of the fourth resistor R4 is connected to the first DC power supply VDD, the other end of the fourth resistor R4 is connected to the input end of the third current source I3 and the gate of the fourth switch tube Q4, the source of the fourth switch tube Q4 is connected to the ground end of the comparator U2, the drain of the fourth switch tube Q4 is connected to the input end of the fourth current source I4, and the output end of the third current source I3 and the output end of the fourth current source I4 are grounded. ; In this way, the ground terminal voltage Vgnd of the comparator U2 is Vdd=vdd-i3*r4+Vgs, wherein vdd is the voltage of the first DC power supply VDD, i3 is the current of the third current source I3, r4 is the resistance value of the fourth resistor R4, and Vgs is the source-gate voltage when the fourth switch tube Q4 is turned on. Therefore, it can be known that the voltage difference between the power supply terminal and the ground terminal of the comparator U2 is Vu2=i3*r4-Vgs. In this way, by setting the current of the third current source I3 and the resistance value of the fourth resistor R4, the comparator U2 can operate in a low voltage area lower than the voltage of the first DC power supply VDD (the low voltage area refers to a voltage lower than 5V), so that the comparator U2 can use low-voltage devices, and the first DC power supply VDD voltage can be a high voltage higher than 60V.

[0043] Cooperate Figure 1As shown, in the first embodiment of the present invention, the signal conversion circuit 4 includes a third switch tube Q3, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1 and a Schmitt trigger U3, and the third switch tube Q3 is a PMOS tube; wherein the source of the third switch tube Q3 is connected to the first DC power supply VDD, the gate of the third switch tube Q3 is connected to the output end of the overcurrent detection circuit 1 as the input end of the signal conversion circuit 4, the drain of the third switch tube Q3 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to one end of the third resistor R3 and is grounded through the second resistor R2, the other end of the third resistor R3 is connected to the input end of the Schmitt trigger U3 and is grounded through the first capacitor C1, and the output end of the Schmitt trigger U3 is used as the output end of the signal conversion circuit 4. In this way, when a high-level normal signal is input into the signal conversion circuit 4, the third switch tube Q3 is turned off, so that the input voltage of the Schmitt trigger U3 is low, and then the output end of the Schmitt trigger U3 outputs a low-level holding signal; and when a low-level overcurrent signal is input into the signal conversion circuit 4, the third switch tube Q3 is turned on, so that the input voltage of the Schmitt trigger U3 is high, and then the output end of the Schmitt trigger U3 outputs a high-level trigger signal; wherein the first resistor R1 and the second resistor R2 can perform a voltage division operation, so that the Schmitt trigger U3 can operate in a low voltage region lower than the voltage of the first DC power supply VDD, and then the back-end timing control circuit 2 can also operate in a low voltage region lower than the voltage of the first DC power supply VDD, so that the Schmitt trigger U3 and the timing control circuit 2 can use low-voltage devices; in addition, the voltage of the output holding signal and the trigger signal can be stabilized by the Schmitt trigger U3.

[0044] Cooperate Figure 1As shown, in the first embodiment of the present invention, the timing control circuit 2 includes a D flip-flop U4 and a counter U5; the initial state of the positive output end of the D flip-flop U4 is a low level; wherein the input end of the D flip-flop U4 is connected to the second DC power supply VCC, the voltage of the second DC power supply VCC may be lower than the voltage of the first DC power supply VDD, the clock end of the D flip-flop U4 is connected to the enable end of the counter U5 and serves as the input end of the timing control circuit 2, the output end of the counter U5 is connected to the reset end of the D flip-flop U4, and the negative output end of the D flip-flop U4 is connected to the enable control circuit 3 as the output end of the timing control circuit 2; in this way, in the timing When the control circuit 2 is powered on, the negative output terminal of the D flip-flop U4 outputs a high-level start signal; and when the signal received at the input terminal of the timing control circuit 2 changes from a holding signal to a trigger signal, that is, when the signal received at the input terminal of the timing control circuit 2 generates a rising edge, the D flip-flop U4 is triggered, so that the negative output terminal of the D flip-flop U4 outputs a low-level shutdown signal. At the same time, the counter U5 starts counting. After counting for a set time, the counter U5 outputs a signal to the reset terminal of the D flip-flop U4 to reset the D flip-flop U4, and the negative output terminal of the D flip-flop U4 outputs a high-level start signal again.

[0045] Cooperate Figure 1 As shown, in the first embodiment of the present invention, the enabling control circuit 3 includes an AND gate U1, a first current source I1, a current limiting resistor RT and a first switch tube Q1, and the first switch tube Q1 is an NMOS tube; wherein the first input end of the AND gate U1 is used to access the enabling signal EN, the second input end of the AND gate U1 is used to connect to the output end of the timing control circuit 2 and access the output signal of the timing control circuit 2, and the output end of the AND gate U1 is connected to the gate of the first switch tube Q1; one end of the current limiting resistor RT is connected to the first DC power supply VDD, and the other end of the current limiting resistor RT is connected to the drain of the first switch tube Q1, and the source of the first switch tube Q1 is grounded through the first current source I1; the current limiting resistor R The common end of T and the first switch tube Q1 is connected to the gate of the controlled power tube M1 as the output end of the enable control circuit 3; the enable signal EN is valid at a high level. When the first input end and the second input end of the AND gate U1 are respectively connected to the high-level enable signal EN and the high-level start signal, the AND gate U1 outputs a high level to the first switch tube Q1 to turn on the first switch tube Q1, thereby controlling the controlled power tube M1 and the second switch tube Q2 to turn on; and when the second input end of the AND gate U1 is connected to a low-level shutdown signal, the AND gate U1 outputs a low level to the first switch tube Q1 to turn off the first switch tube Q1, thereby controlling the controlled power tube M1 and the second switch tube Q2 to turn off.

[0046] Embodiment 2:

[0047] Cooperate Figure 2As shown, in the second embodiment of the present invention, the controlled power tube M1 of the power tube control circuit 5 is an NMOS tube, the input end of the load 51 is connected to a first DC power supply VDD, the output end of the load 51 is connected to the drain of the controlled power tube M1, and the source of the controlled power tube M1 is grounded.

[0048] Cooperate Figure 2As shown, in the second embodiment of the present invention, the overcurrent detection circuit 1 includes a second switch tube Q2, a second current source I2 and a comparator U2, the second switch tube Q2 is an NMOS tube, and the transconductance of the second switch tube Q2 is less than the transconductance of the controlled power tube M1; wherein the input end of the second current source I2 is connected to the first DC power supply VDD, the output end of the second current source I2 is connected to the drain of the second switch tube Q2 and the positive input end of the comparator U2, the gate of the second switch tube Q2 is connected to the gate of the controlled power tube M1 and the output end of the enable control circuit 3, and the source of the second switch tube Q2 is grounded; the negative input end of the comparator U2 is connected to the drain of the controlled power tube M1, the power supply end of the comparator U2 is connected to a second DC power supply VCC, and the ground end of the comparator U2 is grounded; in this way, when the enable control circuit 3 controls the controlled power tube M1 to turn on, the second switch tube Q2 is also turned on synchronously; when the enable control circuit 3 controls the controlled power tube M1 to turn off, the second switch tube Q2 can also be turned off synchronously, thereby reducing energy consumption. In addition, since the sources of the second switch tube Q2 and the controlled power tube M1 are both grounded, the input terminals of the load 51 and the second current source I2 are both connected to the first DC power supply VDD, the gates of the second switch tube Q2 and the controlled power tube M1 are both connected to the output terminal of the enable control circuit 3, and the second switch tube Q2 and the controlled power tube M1 are the same type of field effect tubes. Thus, when the controlled power tube M1 and the second switch tube Q2 are turned on, if the drain voltages of the controlled power tube M1 and the second switch tube Q2 are equal, that is, the positive input terminal voltage of the comparator U2 is equal to the negative input terminal voltage of the comparator U2, at this time, the current of the controlled power tube M1 is N times the current of the second switch tube Q2, and N is equal to the transconductance of the controlled power tube M1 divided by the transconductance of the second switch tube Q2; and if the drain voltage of the controlled power tube M1 is greater than the drain voltage of the second switch tube Q2, that is, the positive input terminal voltage of the comparator U2 is less than the negative input terminal voltage of the comparator U2, at this time, the current of the controlled power tube M1 is greater than the second switch tube Q2. If the drain voltage of the controlled power tube M1 is less than the drain voltage of the second switch tube Q2, that is, the positive input terminal voltage of the comparator U2 is greater than the negative input terminal voltage of the comparator U2, the current of the controlled power tube M1 is less than N times the current of the second switch tube Q2, and the comparator U2 outputs a high-level normal signal; in this way, N times the current of the second switch tube Q2 is set as the overcurrent threshold of the controlled power tube M1. When the controlled power tube M1 does not have an overcurrent, the current of the controlled power tube M1 is less than the overcurrent threshold, then the positive input terminal voltage of the comparator U2 is greater than the negative input terminal voltage of the comparator U2, and the comparator U2 outputs a high-level normal signal; and if the controlled power tube M1 has an overcurrent, the current of the controlled power tube M1 is greater than the overcurrent threshold, then the positive input terminal voltage of the comparator U2 is less than the negative input terminal voltage of the comparator U2, and the comparator U2 outputs a low-level overcurrent signal.

[0049] Cooperate Figure 2 As shown, in the second embodiment of the present invention, the signal conversion circuit 4 includes a third switch tube Q3, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1 and a Schmitt trigger U3, and the third switch tube Q3 is a PMOS tube; wherein the source of the third switch tube Q3 is connected to the second DC power supply VCC, the gate of the third switch tube Q3 is connected to the output end of the overcurrent detection circuit 1 as the input end of the signal conversion circuit 4, the drain of the third switch tube Q3 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to one end of the third resistor R3 and is grounded through the second resistor R2, the other end of the third resistor R3 is connected to the input end of the Schmitt trigger U3 and is grounded through the first capacitor C1, and the output end of the Schmitt trigger U3 is used as the output end of the signal conversion circuit 4. In this way, when a high-level normal signal is input into the signal conversion circuit 4, the third switch tube Q3 is turned off, so that the input voltage of the Schmitt trigger U3 is low, and then the output end of the Schmitt trigger U3 outputs a low-level holding signal; and when a low-level overcurrent signal is input into the signal conversion circuit 4, the third switch tube Q3 is turned on, so that the input voltage of the Schmitt trigger U3 is high, and then the output end of the Schmitt trigger U3 outputs a high-level trigger signal; wherein a voltage division operation can be performed through the first resistor R1 and the second resistor R2 to reduce the voltage; in addition, the voltage of the output holding signal and the trigger signal can be stabilized through the Schmitt trigger U3.

[0050] Cooperate Figure 2 As shown, in the second embodiment of the present invention, the timing control circuit 2 includes a D flip-flop U4 and a counter U5; the initial state of the positive output end of the D flip-flop U4 is a low level; wherein the input end of the D flip-flop U4 is connected to the second DC power supply VCC, the voltage of the second DC power supply VCC may be lower than the voltage of the first DC power supply VDD, the clock end of the D flip-flop U4 is connected to the enable end of the counter U5 and serves as the input end of the timing control circuit 2, the output end of the counter U5 is connected to the reset end of the D flip-flop U4, and the negative output end of the D flip-flop U4 is connected to the enable control circuit 3 as the output end of the timing control circuit 2; in this way, in the timing control circuit 2, the clock end of the D flip-flop U4 is connected to the enable end of the counter U5 and serves as the input end of the timing control circuit 2. When the timing control circuit 2 is powered on, the negative output terminal of the D flip-flop U4 outputs a high-level start signal; and when the signal received by the input terminal of the timing control circuit 2 changes from a holding signal to a trigger signal, that is, when the signal received by the input terminal of the timing control circuit 2 generates a rising edge, the D flip-flop U4 is triggered, so that the negative output terminal of the D flip-flop U4 outputs a low-level shutdown signal. At the same time, the counter U5 starts counting. After counting for a set time, the counter U5 outputs a signal to the reset terminal of the D flip-flop U4 to reset the D flip-flop U4, and the negative output terminal of the D flip-flop outputs a high-level start signal again.

[0051] Cooperate Figure 2As shown, in the second embodiment of the present invention, the enable control circuit 3 includes an AND gate U1; wherein the first input end of the AND gate U1 is used to access the enable signal EN, the second input end of the AND gate U1 is used to connect to the output end of the timing control circuit 2 and access the output signal of the timing control circuit 2, and the output end of the AND gate U1 is connected as the output end of the enable control circuit 3; the enable signal EN is high level valid, when the first input end and the second input end of the AND gate U1 are respectively connected to the high level enable signal EN and the high level start signal, the AND gate U1 outputs a high level to the gate of the controlled power tube M1 and the second switch tube Q2, thereby controlling the controlled power tube M1 and the second switch tube Q2 to turn on; and when the second input end of the AND gate U1 is connected to the low level shutdown signal, the AND gate U1 outputs a low level to the gate of the controlled power tube M1 and the second switch tube Q2, thereby controlling the controlled power tube M1 and the second switch tube Q2 to turn off.

[0052] The above embodiments and drawings do not limit the product form and style of the present invention. Any appropriate changes or modifications made by ordinary technicians in the relevant technical field should be deemed to be within the patent scope of the present invention.

Claims

1. A power tube overcurrent protection circuit is applied to a power tube control circuit, the power tube control circuit includes a load and a controlled power tube for controlling whether the load works or not, and is characterized by: The power tube overcurrent protection circuit comprises: An overcurrent detection circuit is connected to the controlled power tube; the overcurrent detection circuit is used to detect whether the controlled power tube has overcurrent; if the controlled power tube has overcurrent, the output end of the overcurrent detection circuit outputs an overcurrent signal; and if the controlled power tube has no overcurrent, the output end of the overcurrent detection circuit outputs a normal signal; A timing control circuit is connected to the output end of the overcurrent detection circuit; when the timing control circuit is powered on, the output end of the timing control circuit outputs an on signal; after the timing control circuit is powered on, the output end signal of the timing control circuit is controlled according to the signal output from the output end of the overcurrent detection circuit; if the output end of the overcurrent detection circuit outputs an overcurrent signal, the output end of the timing control circuit continuously outputs a shutoff signal within a set time and re-outputs an on signal after the set time is reached; if the output end of the overcurrent detection circuit outputs a normal signal, the output end of the timing control circuit keeps outputting the on signal; An enable control circuit is connected to the output end of the timing control circuit and the gate of the controlled power tube respectively; the enable control circuit is used to control the on and off of the controlled power tube, and the enable control circuit is controlled by a signal output from the output end of the timing control circuit and an enable signal; as long as the enable control circuit receives a shutdown signal output by the timing control circuit, the enable control circuit shuts down the controlled power tube; and when the enable control circuit receives a valid enable signal and a start signal output by the timing control circuit at the same time, the enable control circuit turns on the controlled power tube; The controlled power tube is a PMOS tube, the source of which is connected to a first DC power supply, and the drain of which is connected to the load; the overcurrent detection circuit comprises a second switch tube, a second current source and a comparator; the second switch tube is a PMOS tube, and the transconductance of the second switch tube is smaller than the transconductance of the controlled power tube; the source of the second switch tube is connected to the first DC power supply, the gate of the second switch tube is connected to the gate of the controlled power tube and the output end of the enable control circuit, the drain of the second switch tube is connected to the negative input end of the comparator and is grounded through the second current source; the positive input end of the comparator is connected to the drain of the controlled power tube, the output end of the comparator serves as the output end of the overcurrent detection circuit, the power supply end of the comparator is connected to the first DC power supply, and the ground end of the comparator is connected to the virtual ground circuit; the overcurrent signal is a low-level signal, and the normal signal is a high-level signal.

2. A power tube overcurrent protection circuit as claimed in claim 1, characterized in that: The timing control circuit is connected to the overcurrent detection circuit through a signal conversion circuit; The input end of the signal conversion circuit is connected to the output end of the overcurrent detection circuit; the signal conversion circuit is used to perform level conversion on the signal output from the output end of the overcurrent detection circuit, the signal conversion circuit converts a high-level normal signal into a low-level holding signal and outputs it to the input end of the timing control circuit, and the signal conversion circuit converts a low-level overcurrent signal into a high-level trigger signal and outputs it to the input end of the timing control circuit; The input end of the timing control circuit is connected to the output end of the signal conversion circuit; after the timing control circuit is powered on, if the input end of the timing control circuit receives a hold signal, the output end of the timing control circuit continues to output an on signal; and if the signal received at the input end of the timing control circuit changes from a hold signal to a trigger signal, the output end of the timing control circuit continuously outputs a shut-off signal within a set time and re-outputs an on signal after the set time is reached.

3. A power tube overcurrent protection circuit as claimed in claim 1 or 2, characterized in that: The virtual ground circuit includes a fourth switch tube, a fourth resistor, a third current source, and a fourth current source, wherein the fourth switch tube is a PMOS tube; wherein one end of the fourth resistor is connected to the first DC power supply, the other end of the fourth resistor is connected to the input end of the third current source and the gate of the fourth switch tube, the source of the fourth switch tube is connected to the ground end of the comparator, the drain of the fourth switch tube is connected to the input end of the fourth current source, and the output end of the third current source and the output end of the fourth current source are grounded.

4. A power tube overcurrent protection circuit as claimed in claim 2, characterized in that: The signal conversion circuit includes a third switch tube, a first resistor, a second resistor, a third resistor, a first capacitor and a Schmitt trigger, and the third switch tube is a PMOS tube; The source of the third switch tube is connected to the first DC power supply, the gate of the third switch tube serves as the input end of the signal conversion circuit, the drain of the third switch tube is connected to one end of the first resistor, the other end of the first resistor is connected to one end of the third resistor and is grounded through the second resistor, the other end of the third resistor is connected to the input end of the Schmitt trigger and is grounded through the first capacitor, and the output end of the Schmitt trigger serves as the output end of the signal conversion circuit.

5. A power tube overcurrent protection circuit as claimed in claim 1 or 2, characterized in that: The enable control circuit includes an AND gate, a first current source, a current limiting resistor and a first switch tube, wherein the first switch tube is an NMOS tube; wherein the first input end of the AND gate is used to access the enable signal, the second input end of the AND gate is used to connect to the output end of the timing control circuit, and the output end of the AND gate is connected to the gate of the first switch tube; One end of the current limiting resistor is connected to the first DC power supply, the other end of the current limiting resistor is connected to the drain of the first switching tube, and the source of the first switching tube is grounded through the first current source; the common end of the current limiting resistor and the first switching tube is connected to the gate of the controlled power tube as the output end of the enable control circuit.

6. A power tube overcurrent protection circuit as claimed in claim 2, characterized in that: The timing control circuit includes a D flip-flop and a counter; the initial state of the positive output end of the D flip-flop is a low level; The input end of the D flip-flop is connected to the second DC power supply, the clock end of the D flip-flop is connected to the enable end of the counter and serves as the input end of the timing control circuit, the output end of the counter is connected to the reset end of the D flip-flop, and the negative output end of the D flip-flop serves as the output end of the timing control circuit.

7. A power tube overcurrent protection circuit, applied to a power tube control circuit, the power tube control circuit includes a load and a controlled power tube for controlling whether the load works or not, characterized in that: The power tube overcurrent protection circuit comprises: An overcurrent detection circuit is connected to the controlled power tube; the overcurrent detection circuit is used to detect whether the controlled power tube has overcurrent; if the controlled power tube has overcurrent, the output end of the overcurrent detection circuit outputs an overcurrent signal; and if the controlled power tube has no overcurrent, the output end of the overcurrent detection circuit outputs a normal signal; A timing control circuit is connected to the output end of the overcurrent detection circuit; when the timing control circuit is powered on, the output end of the timing control circuit outputs an on signal; after the timing control circuit is powered on, the output end signal of the timing control circuit is controlled according to the signal output from the output end of the overcurrent detection circuit; if the output end of the overcurrent detection circuit outputs an overcurrent signal, the output end of the timing control circuit continuously outputs a shutoff signal within a set time and re-outputs an on signal after the set time is reached; if the output end of the overcurrent detection circuit outputs a normal signal, the output end of the timing control circuit keeps outputting the on signal; An enable control circuit is connected to the output end of the timing control circuit and the gate of the controlled power tube respectively; the enable control circuit is used to control the on and off of the controlled power tube, and the enable control circuit is controlled by a signal output from the output end of the timing control circuit and an enable signal; as long as the enable control circuit receives a shutdown signal output by the timing control circuit, the enable control circuit shuts down the controlled power tube; and when the enable control circuit receives a valid enable signal and a start signal output by the timing control circuit at the same time, the enable control circuit turns on the controlled power tube; The controlled power tube is an NMOS tube, the input end of the load is connected to a first DC power supply, the drain of the controlled power tube is connected to the output end of the load, and the source of the controlled power tube is grounded; the overcurrent detection circuit includes a second switch tube, a second current source and a comparator; the second switch tube is an NMOS tube, and the transconductance of the second switch tube is smaller than the transconductance of the controlled power tube; the input end of the second current source is connected to the first DC power supply, the output end of the second current source is connected to the drain of the second switch tube and the positive input end of the comparator, the gate of the second switch tube is connected to the gate of the controlled power tube and the output end of the enable control circuit, and the source of the second switch tube is grounded; the negative input end of the comparator is connected to the drain of the controlled power tube, the power supply end of the comparator is connected to a second DC power supply, and the ground end of the comparator is grounded; the overcurrent signal is a low-level signal, and the normal signal is a high-level signal.

8. A power tube overcurrent protection circuit as claimed in claim 7, characterized in that: The timing control circuit is connected to the overcurrent detection circuit through a signal conversion circuit; The input end of the signal conversion circuit is connected to the output end of the overcurrent detection circuit; the signal conversion circuit is used to perform level conversion on the signal output from the output end of the overcurrent detection circuit, the signal conversion circuit converts a high-level normal signal into a low-level holding signal and outputs it to the input end of the timing control circuit, and the signal conversion circuit converts a low-level overcurrent signal into a high-level trigger signal and outputs it to the input end of the timing control circuit; The input end of the timing control circuit is connected to the output end of the signal conversion circuit; after the timing control circuit is powered on, if the input end of the timing control circuit receives a hold signal, the output end of the timing control circuit continues to output an on signal; and if the signal received at the input end of the timing control circuit changes from a hold signal to a trigger signal, the output end of the timing control circuit continuously outputs a shut-off signal within a set time and re-outputs an on signal after the set time is reached.

9. A power tube overcurrent protection circuit as claimed in claim 8, characterized in that: The signal conversion circuit includes a third switch tube, a first resistor, a second resistor, a third resistor, a first capacitor and a Schmitt trigger, and the third switch tube is a PMOS tube; The source of the third switch tube is connected to the second DC power supply, the gate of the third switch tube serves as the input end of the signal conversion circuit, the drain of the third switch tube is connected to one end of the first resistor, the other end of the first resistor is connected to one end of the third resistor and is grounded through the second resistor, the other end of the third resistor is connected to the input end of the Schmitt trigger and is grounded through the first capacitor, and the output end of the Schmitt trigger serves as the output end of the signal conversion circuit.

10. The power tube overcurrent protection circuit according to claim 7, characterized in that: The enable control circuit includes an AND gate; wherein the first input end of the AND gate is used to access the enable signal, the second input end of the AND gate is used to connect to the output end of the timing control circuit, and the output end of the AND gate is connected to the gate of the controlled power tube as the output end of the enable control circuit.

11. A power tube overcurrent protection circuit according to any one of claims 7 to 10, characterized in that: The timing control circuit includes a D flip-flop and a counter; the initial state of the positive output end of the D flip-flop is a low level; The input end of the D flip-flop is connected to the second DC power supply, the clock end of the D flip-flop is connected to the enable end of the counter and serves as the input end of the timing control circuit, the output end of the counter is connected to the reset end of the D flip-flop, and the negative output end of the D flip-flop serves as the output end of the timing control circuit.

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