Controller device and processing method thereof

Abstract

The technology relates to devices, methods and / or systems for responding to a request to access a portion of memory before completing a requested operation to place the portion of memory in an initialized state. In one example implementation, a memory controller may delay the start of a write operation addressed to a particular portion of memory until a pending request to initialize the particular portion of memory is completed. In another example implementation, a memory controller may service a request for a read operation by returning values ​​in response to the presence of a pending request to initialize the particular portion of memory, the values ​​including a value indicating an initialized state.

Description

Technical Field

[0001] The present disclosure relates to techniques for accessing memory in a computing system and, in particular, but not exclusively, to techniques for initializing bits in memory. Background Art

[0002] In a computing system, different applications (or processes) may use the same memory, making it possible for a subsequent application to access or restore data from memory used by a previous application, and the data thus restored may include sensitive / security information. In systems with persistent memory, such access may occur, for example, after a restart from a power failure.

[0003] To prevent such access, the memory or portions thereof may be initialized prior to access by an application, or to improve the efficiency of an application (eg, cryptographic operations).

[0004] Such initialization may include zeroing the kernel for initialization so data is not leaked to another process.

[0005] Additionally, Linux platforms can perform lazy initialization when writing to a page (e.g., "Copy-on-Write"), while FreeBSD platforms can perform eager initialization by initializing multiple pages of memory over multiple clock cycles and maintaining a pool of memory for allocation. Userspace applications are required to initialize heap memory pages after allocation by memset as in C, or implicitly by constructors as in C++ or C#.

[0006] Additionally, the hypervisor initializes physical pages over multiple clock cycles before allocating them to another machine, e.g., for security / data privacy between virtual machines. Summary of the invention

[0007] In short, a specific implementation is directed to a controller device that includes: a first buffer for maintaining a record of pending requests for the state of a portion of an initialized memory, the pending requests including at least a first pending request for the state of a first portion of the initialized memory; and a circuit configured to delay the start of a write operation addressed to a second portion of the memory until an operation for servicing the first pending request for the state of the first portion of the initialized memory is completed.

[0008] Another specific implementation is directed to a method at a controller device, the method comprising: maintaining a record of pending requests for the state of a portion of an initialized memory in a first buffer, the pending requests including at least a first pending request for the state of a first portion of the initialized memory; and delaying the start of a write operation addressed to a second portion of the memory until an operation for servicing the first pending request for the state of the first portion of the initialized memory is completed.

[0009] Another specific implementation is directed to a controller device, which includes: a first buffer for maintaining a record of pending requests for the state of a portion of an initialized memory, the pending requests including at least a first pending request for the state of a first portion of the initialized memory; and a circuit configured to return values ​​to service a request for an operation to read a second portion of the memory in response to detecting the first pending request for the initialized first portion of the memory without accessing the second portion of the memory, the values ​​including values ​​representing the initialized state.

[0010] Another specific implementation is directed to a method at a controller device, the method comprising: maintaining a record of pending requests for a state of a portion of an initialized memory in a first buffer, the pending requests comprising at least a first pending request for a state of a first portion of the initialized memory; and in response to detecting the first pending request for the first portion of the initialized memory, returning values ​​to service a request for an operation to read a second portion of the memory without accessing the second portion of the memory, the values ​​comprising a value representing the initialized state.

[0011] Another specific implementation is directed to a method at a controller device, the method comprising: maintaining in a first buffer a record of pending requests for performing operations for initializing the state of a portion of a memory, the pending requests comprising at least a first pending request for performing operations for initializing the state of a first portion of a memory; and in the absence of a request to perform a read operation before the requested write operation, conditionally merging the write operation with the operation for initializing the state of the first portion of the memory, the write operation being addressed to a second portion of the memory within the first portion of the memory.

[0012] Another specific implementation is directed to a controller device, which includes: a first buffer for maintaining a record of pending requests for initializing the state of a portion of a memory, the pending requests including at least a first pending request for initializing the state of a first portion of the memory; and a circuit configured to conditionally merge the write operation with an operation for initializing the state of the first portion of the memory in the absence of a request to perform a read operation before the requested write operation, the write operation being addressed to a second portion of the memory within the first portion of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] It should be understood that the implementations described above are merely example implementations, and that claimed subject matter is not necessarily limited to any specific aspects of these example implementations.

[0014] The claimed subject matter is particularly pointed out and distinctly claimed in the concluding portion of the specification. However, the organization and / or method of operation, and objects, features, and / or advantages thereof, will be best understood from the following detailed description when read in conjunction with the accompanying drawings, in which:

[0015] Figure 1 Schematically shows a block diagram of a computing system according to an embodiment;

[0016] Figure 2A schematically shows a block diagram of a controller device according to an embodiment;

[0017] Figure 2B is a flowchart of a process according to a specific embodiment;

[0018] Figure 2C is a schematic diagram of a queue of a controller device according to an embodiment;

[0019] Figure 2D is a flowchart of a process according to a specific embodiment;

[0020] Figure 3A is a schematic block diagram of a memory and a controller device according to an embodiment;

[0021] Figure 3B schematically illustrates a timing diagram for initializing a portion of a memory according to an embodiment;

[0022] Figure 4A is a schematic diagram of a controller device and a memory according to an embodiment;

[0023] Figure 4B Schematically shows the process for initializing Figure 4A A timing diagram of a portion of a memory;

[0024] Figure 4C and Figure 4D A diagram schematically showing a controller device and memory according to an embodiment using the present technology;

[0025] Figure 5 schematically illustrates the architecture of a memory array according to an embodiment using the present technology; and

[0026] Figure 6 An example flow chart illustrating a process of initializing a portion of memory according to an embodiment is shown. DETAILED DESCRIPTION

[0027] Reference is made to the accompanying drawings forming a part thereof in the following detailed description, wherein similar numbers may indicate similar parts throughout the text, which are corresponding and / or similar. It will be understood that the drawings are not necessarily drawn to scale, for example for the sake of simplicity and clarity of illustration. For example, the dimensions of certain aspects may be exaggerated relative to other aspects. In addition, it should be understood that other embodiments may be utilized. In addition, structural and / or other changes may be made without departing from the claimed subject matter. Throughout the specification, references to "claimed subject matter" refer to the subject matter intended to be covered by one or more claims or any part thereof, and are not necessarily intended to refer to a complete set of claims, to a specific combination of claim sets (e.g., method claims, device claims, etc.), or to a specific claim. It should also be noted that directions and / or references such as upper, lower, top, bottom, etc. may be used to facilitate discussion of the drawings and are not intended to limit the application of the claimed subject matter. Therefore, the following detailed description should not be used to limit the claimed subject matter and / or its equivalent.

[0028] Computer memory may be initialized using any of several different techniques, including, for example, using cyclic writes that may cause cache pollution. Such cache pollution may further cause other dirty and valid lines to be evicted (e.g., causing unnecessary write-backs to non-volatile memory (NVM) devices, thereby affecting the performance of the NVM devices and affecting their durability), as well as additional movement of data between off-chip NVM and on-chip cache. While using non-volatile storage for initial memory can avoid cache pollution and movement of data between off-chip NVM and on-chip cache, this may cause long write latencies, stalling the execution of applications.

[0029] Given the expected increase in density of NVM, terabyte-level NVM as primary memory is expected to become a reality in the near future, and memory initialization may not be sufficient even at cache line granularity. In one approach, range-based cache memory operations (CMOs) may enable initialization of a portion of memory using fewer CMOs (and thus fewer operation and confirmation cycles). In other words, range-based bulk operations may initialize a range more efficiently than current finer-grained instructions.

[0030] In one implementation, the memory controller may include a buffer for storing initialization requests (e.g., in a queue). Once the initialization request is queued, an acknowledgement signal may be quickly provided to the CPU that issued the initialization request. However, the memory controller may perform the initialization operation to satisfy the request quickly (e.g., as a write-through operation) or less urgently (e.g., as a write-back operation).

[0031] According to an embodiment, the memory controller may delay the execution of an operation to initialize a portion of the memory. In one implementation, if the memory controller receives a request to read a page in the portion of the memory before the requested operation to initialize a portion of the off-chip memory is completed (e.g., when the requested initialization operation is still in the buffer queue), the memory controller may provide an initialization state without accessing the off-chip memory. In another implementation, if a request for a write operation to a page in a portion of the off-chip memory is received after receiving the initialization request but before completing the initialization request (e.g., when the initialization request is still in the buffer queue), the memory controller may delay the execution of the requested write operation until the requested write operation is completed. This can prevent the initialization state from being accidentally written on data that was previously stored in the requested write operation. The comparison logic for checking whether the requested read or write operation overlaps with a previously incomplete initialization may include an inclusion test of the address.

[0032] Figure 1 is a schematic diagram of a computing system 1, which includes a processor 2, which may include a general-purpose processor, a network processor, an application processor (e.g., as used in a mobile phone), or other types of processors (including a reduced instruction set computer (RISC) processor or a complex instruction set computer (CISC) processor). In addition, the processor 2 may have a single core or multiple cores.

[0033] In this example, processor 2 includes local memory 4 , depicted as a level one (L1) cache 4 , for caching data ( L1 D) and instructions ( L1 I) local to processor 2 .

[0034] An interconnect or bus 6 (hereinafter referred to as "system bus" 6) couples the processor 2 to a controller device 8, which is coupled to a storage device 10 via an interconnect or bus 12 (hereinafter referred to as "memory bus" 12), which storage device 10 includes a memory 10 in the illustrative example. In a specific implementation, the controller device 8 can be implemented as a media controller or a memory controller. In this context, the terms "media controller" and "memory controller" mentioned herein refer to devices that facilitate transactional access to a memory or media device. For example, a media controller or a memory controller can detect the state of a physically addressable portion of a memory or a media device corresponding to a physical address in response to a request, that is, "read" the physically addressable portion. Moreover, a media controller or a memory controller can affect the state of a physically addressable portion of a memory or a media device in response to a request, that is, "write" to the physically addressable portion.

[0035] The controller device 8 receives read or write requests generated by the processor 2 and generates signals in response to the read or write requests to access the memory 10, as described below.

[0036] The memory 10 includes control logic for decoding signals received from the controller device 8 and providing read or write access accordingly.

[0037] In an embodiment, the memory 10 includes a plurality of addressable bit cells. It is understood that a "bit cell" as referred to herein includes a circuit or a portion of a circuit capable of storing a value, symbol, parameter or condition representing its memory state.

[0038] The memory 10 may include a nonvolatile memory such as a nanowire memory, a ferroelectric transistor random access memory (FeTRAM), a magnetoresistive random access memory (MRAM), a flash memory, a spin torque transfer random access memory (STTRAM), a STT magnetic RAM (STTMRAM), a 3D cross-point memory such as a phase change memory (PCM), an SSD with a NAND / NOR memory, a memory using a correlated electronic material (CEM), etc. In some embodiments, the NVM memory 10 may include a storage class memory (SCM).

[0039] In other embodiments, the memory 10 may be a volatile memory such as a random access memory (RAM) (eg, static RAM (SRAM) or dynamic RAM (DRAM)).

[0040] Although not specifically depicted, other logic may be provided in computing system 1 .

[0041] For example, Figure 1 As shown, a shared level 2 (L2) cache 14 may be provided between the system bus 6 and the memory 10 , whereby the L2 cache 14 may be used to store data and / or instructions utilized by the processor 2 .

[0042] As another example, computing system 1 may include additional storage devices (not shown) such as a hard disk drive (HDD), or may include additional or alternative bus masters (depicted as bus master(s) 3), which may include one or more of the following: processor(s), graphics processing unit(s) (GPUs), direct memory access (DMA) controller(s), and input / output (I / O) interface(s), although this list is not exhaustive.

[0043] Figure 2A A block diagram of a controller device 8 according to an embodiment is schematically shown, wherein the controller device 8 includes a buffer or queue for storing access requests, wherein the access request may include a read / write (e.g., initialization) request to a portion of the memory from a processor. In one implementation, the controller device 8 may include circuits or logic (e.g., CMOS logic circuits, field programmable gate array logic, or microcontroller logic, or a combination thereof) to implement the features described herein. In addition, the controller device 8 may be implemented as a memory controller and integrated with a CPU such as a CPU as a single device, or may be implemented as an "off-chip" device separated from the CPU. Alternatively, the controller device 8 may be implemented as a media controller integrated on a device (the device includes an array of bit cells to be accessed). However, the features described herein with respect to a specific embodiment of a memory controller or a media controller are not limited to any specific implementation of the memory controller or the media controller, and it should also be understood that the subject matter claimed for protection is not limited in this regard.

[0044] According to an embodiment, an "operation to initialize a target portion of memory" or an "initialization operation" for a target portion of memory refers to a process of placing bit cells of a target portion of memory in a uniform state. Such a uniform state may include the same value, symbol, parameter, or condition for all bit cells of the target portion so that all bit cells represent the same memory state. It should be understood that the initialization operation may be for a target portion of memory of any size, such as an addressable page of memory, and may be as small as an addressable cache line of memory. In one embodiment, a memory controller or media controller may service a single request or command (e.g., originating from a CPU) to initialize a larger portion of memory (e.g., a page) by performing multiple initialization operations for smaller portions (e.g., cache lines) that constitute the larger portion.

[0045] In addition, the controller device 8 can receive a request for performing an operation on the memory 10 (e.g., originating from CPU2). The controller device 8 can maintain such a request for performing an operation on the memory 10 in a plurality of buffer queues, the plurality of buffer queues including, for example: a write queue 20, for queuing requests for write operations; a read queue 22, for requests for performing read operations; and an initialization queue 25, for requests for performing initialization operations. The controller device 8 can also maintain a response queue 28 of confirmation signals to be sent (e.g., to CPU 2), which are used to confirm the receipt or completion of a write request, a read request, or an initialization request. In a specific implementation, the queues maintained at the controller device 8 (e.g., the write queue 20, the read queue 22, the initialization queue 25, and the response queue 28) can operate a first-in-first-out (FIFO) queue.

[0046] According to an embodiment, an arbitration mechanism, depicted as arbitrator 24, may determine the order in which these access requests are executed. For example, arbitrator 24 may arbitrate the order of access requests between the access requests in write queue 20, read queue 22, and initialization queue 25 based on one or more of efficiency, predictability, speed, and flexibility requirements of the system. However, it should be understood that this list is not exhaustive and arbitration may be performed based on other system requirements or user instructions.

[0047] The interface (I / F) 26 generates hardware / electrical signals in response to the read and write requests performed. The signals generated by the controller device 8 may include address signals (A) and data signals (DQ), clock signals (CLK), write enable (WE) signals, read / write (R / W) signals to access the memory, as understood by the skilled person.

[0048] In an embodiment using the present technique, the signal interface 26 also generates further signals to initialize a portion of the memory, as will be described in more detail below.

[0049] The interface (I / F) 26 can also receive signals (e.g., from Figure 3A , 4A 4C-D) and generates a response signal (Rsp) to be sent to the bus master. In this illustrative example, the controller device 8 includes a response queue 28 for storing received signals, wherein the response queue 28 can be used as a FIFO.

[0050] As noted above, specific implementations are directed to achieving a delay in performing an operation to initialize a portion of memory while avoiding corruption of computing operations. For example, specific features are directed to enabling the arbiter 24 to delay the execution of an operation requested by an entry in the initialization queue 25 to initialize an addressable portion (e.g., a page or cache line) of the memory 10. In one implementation, before the requested operation to initialize the portion of memory is completed (e.g., when the requested initialization operation is still in the initialization queue 25), if the controller device 8 receives a request to read an addressable portion of the off-chip memory (e.g., a page or cache line of the memory 10), the controller device 8 can satisfy the requested read operation by returning a value based on the initialization state without accessing the off-chip memory. In another implementation, if a request to write a page in the portion of the off-chip memory is received after receiving the initialization request but before the initialization request is completed (e.g., when the initialization request is still in the buffer queue), the memory controller or media controller can delay the execution of the requested operation until the requested initialization operation is completed. This prevents accidental writing of the initialized state over data previously stored in a requested write operation.

[0051] Figure 2B is a flow chart of a process according to an embodiment that can enable delayed initialization of a portion of a memory while avoiding corruption of computing operations. In a specific implementation, the process can be performed at least in part by circuits or logic for implementing the controller device 8. Figure 2B Action in the processing of. Block 202 may include maintaining a record of pending requests for the status of a portion of initialized memory in a buffer. For example, the controller device 8 may maintain requests for initializing a first portion of the memory 10 in a FIFO queue formed by the initialization queue 25. Such requests maintained in the initialization queue 25 may specify the time when the request was received or initiated (e.g., the time when the request was received from the CPU 2 on the signal bus or the time when the request was initiated on the CPU 2) and the size of the portion of the memory to be initialized (e.g., a page or cache line). In one implementation, the request maintained in the initialization queue 25 may indicate the portion of the memory to be initialized as a range of physical memory addresses, such as a target starting address and a range.

[0052] After receiving the initialization request maintained at block 202, the controller device 8 may receive a request for a write operation for writing a value to a second portion of the memory. The second portion of the memory may overlap at least in part with the first portion of the memory to be initialized by the initialization operation requested by the first pending request for initializing the state of the first portion of the memory. In one implementation, the received request for the write operation stored in the write queue 20 may indicate an initiation or reception time after the reception or initiation time of the initialization request indicated in the initialization queue 25. For example, the reception or initiation time of the request for the write operation and the initialization operation may be indicated in the state of the buffer forming the write queue 20 and the initialization queue 25. In addition, the controller device 8 may include comparison logic to determine whether the memory address specified in the request for the write operation overlaps with the memory address specified by the previous uncompleted initialization request maintained at block 202. For example, the logic in the controller device 8 may implement a test to determine whether any address specified by the requested write operation is included in the address specified by the initialization operation. If there is an overlap, the controller device 8 may delay starting the execution of the requested write operation until the initialization operation requested by the first pending request to initialize the first portion of the memory is completed. In one embodiment, a memory controller or a media controller (e.g., the controller device 8) may "initiate" a write operation to a particular portion of the memory by sending one or more signals on the bus (e.g., signals sent on the memory bus 12 via the I / F 26). Such signals for initiating a write operation may specify the physical address of a bit cell of the particular portion of the memory to be written and / or the value or state to be written to the bit cell. In addition, the "completion" of an operation to initialize a portion of the memory may include a specific event in which a specific bit cell constituting the portion of the memory is placed in an initialized state (e.g., all "0" or all "1"). In a non-limiting example, the memory controller or the media controller may determine that the initialization operation has been completed based on the time (e.g., clock cycles or memory cycles) that has passed after sending a signal on the memory bus to perform the initialization operation.

[0053] In an alternative implementation, instead of delaying the start of the write operation at block 204, the memory controller or media controller 8 may merge the operation for writing to the second portion of the memory with the operation for initializing the first portion of the memory (which satisfies the request for initializing the first portion of the memory). For example, if the address range of the second portion of the memory (specified in the request for the write operation) includes the address range of the first portion of the memory (specified in the request for the initialization operation), the controller device 8 may remove or save the initialization request. Here, it may be observed that the initialization of the first portion of the memory will be overwritten by the subsequent write operation to the second portion of the memory in any case. In another embodiment, if the address range of the second portion of the memory falls within the address range of the first portion of the memory, and if the address range of the second portion of the memory is greater than half (or another threshold x%) of the address range of the first portion of the memory, two smaller initialization operations may be used to service the initialization request, with the overlapping address ranges of the first portion and the second portion removed. On the other hand, if the address range of the second portion of the memory is not greater than half (or another threshold x%) of the initialization address range, block 204 may delay execution of the write operation until the operation for initializing the first portion of the memory is completed (which satisfies the pending request to initialize the first portion of the memory).

[0054] Figure 2C is a schematic diagram of features of a write queue 20, an initialization queue 25, and a read queue 22 according to an implementation of a controller device 8. According to an embodiment, memory access requests are executed sequentially according to an order such that requests with lower orders are serviced before requests with higher orders. Figure 2C As shown, initialization request "D" has order 0, read request "E" has order 1, and write request "A" has order 2. The order associated with a particular request in write queue 20, initialization queue 25, or read queue 22 may be determined based at least in part on the time at which the order is received at controller device 8. Figure 2C In a specific example, initialization request "D" is scheduled to be executed before read request "E", and read request "E" is scheduled to be executed before write request "A". According to an embodiment, initialization request "D" can be merged with write request "A" under certain conditions, for example, if read request "E" (having an order before that of write request "A") does not depend on a memory address constrained by initialization request "D". For example, if read request "E" does not cover any memory address covered by initialization request "D", initialization request "D" can be merged with write request "A". However, if read request "E" covers a memory address covered by initialization request "D", initialization request "D" cannot be merged with write request "A".

[0055] For example, assuming that the address range of a write request "A" is 0x00FF_00000 to x00FF_FFFF (64KB page), the address range of an initialization request "D" is 0x00FF_0000 to 0x00FF_0FFF (4KB page), and the address range of a read request "E" is 0x00FF_0000 to 0xFF00_0FFF (4KB page), there is no overlap between the address ranges of the initialization request "D" and the read request "E". In this way, the initialization request "D" can be merged with the write request "A".

[0056] In one embodiment, a method at a controller device, the method comprising: maintaining a record of pending requests to perform operations for initializing the state of a portion of a memory in a first buffer, the pending requests comprising at least a first pending request to perform operations for initializing the state of a first portion of the memory; and conditionally merging the write operation with the operation for initializing the state of the first portion of the memory in the absence of a request to perform a read operation prior to the requested write operation, the write operation being addressed to a second portion of the memory within the first portion of the memory. In one specific implementation, the read operation is addressed to a third portion of the memory, the third portion of the memory at least partially overlapping with the portion of the memory. In another specific implementation, the method further comprises comparing an address range of the third portion of the memory with an address range of the portion of the memory to determine whether the third portion of the memory at least partially overlaps with the portion of the memory.

[0057] In another embodiment, a controller device includes: a first buffer for maintaining a record of pending requests to initialize the state of a portion of a memory, the pending requests including at least a first pending request to initialize the state of a first portion of the memory; and circuitry configured to conditionally merge the write operation with an operation to initialize the state of the first portion of the memory in the absence of a request to perform a read operation prior to the requested write operation, the write operation being addressed to a second portion of the memory within the first portion of the memory. In one specific implementation, the read operation is addressed to a third portion of the memory, the third portion of the memory at least partially overlapping with the portion of the memory. In another specific implementation, the circuitry is further configured to compare an address range of the third portion of the memory with an address range of the portion of the memory to determine whether the third portion of the memory at least partially overlaps with the portion of the memory.

[0058] Figure 2Dis a flow chart of a process according to a second embodiment that can enable delayed initialization of a portion of a memory while avoiding corruption of computing operations. In a specific implementation, the process can be performed at least in part by circuits or logic for implementing the controller device 8. Figure 2D . Similar to block 202 as described above, block 206 may include maintaining a record of pending requests for initializing the state of a portion of memory in a buffer, the pending requests including a first pending request for initializing the state of a first portion of memory (e.g., a page or cache line of memory 10). The memory controller or media controller may then receive a request for an operation to read a second portion of memory such as memory 10. For example, the controller device 8 may receive a request to read the portion of memory and store the request in the read queue 22. The request stored in the read queue 22 may indicate an initiation or reception time of the request that is after a reception or initiation time of the first pending request for initializing the state of the first portion of memory (e.g., as indicated in the initialization queue 25). According to an embodiment, the controller device 8 may include comparison logic for determining whether a memory address specified in a request for a read operation overlaps with a memory address specified by a previous, incomplete initialization request (e.g., as maintained in the buffer at block 206). For example, logic in the controller device 8 may implement a test to determine whether the address specified by the requested read operation is included in the address specified by the initialization operation. If there is an overlap, the controller device 8 may return values ​​to service the request for the read operation at block 208, including values ​​representing the initialization state (e.g., all "0" or "1" bits within the range for the read request) without accessing a specific portion of the memory.

[0059] In an embodiment, accessing a portion of a memory during a read operation may include, among other things, sending a signal on a memory bus (e.g., sending a signal on memory bus 12 via I / F 26) indicating an address associated with a bit cell in the portion of the memory. In a specific implementation, the controller device 8 may service the read request at block 208 without accessing the memory 10 (e.g., without sending a signal on memory bus 12 indicating a physical address of a bit cell in the portion of the memory to be read). Here, the controller device 8 may include logic or circuitry that automatically generates a signal for a message on the system bus 6 at block 208 to return a value (e.g., based on an initialization state) to service the request for a read operation without attempting to access the memory 10 via the memory bus 12. For example, the controller device 8 may, in response to determining an overlap between a previous request to initialize a first portion of the memory 10 and a memory address specified in a request received at box 206 to read a second portion of the memory 10, generate a signal for a message on the system bus 6 at box 208 that includes an initialization value or state (e.g., all "0"s or "1"s) corresponding to an address or bit cell in the second portion without accessing the physical bit cells in the memory 10 via the memory bus 12 (e.g., without requiring interaction between the I / F 26 and the memory 10).

[0060] Figure 3A Schematically shows a block diagram of a memory 300 and a media controller 302 according to a specific embodiment of the memory 10 and the controller device 8, respectively. Figure 3B A timing diagram for initializing a portion of the memory 300 is schematically shown.

[0061] In an embodiment, the memory 300 includes control logic 303 , 304 to decode one or more signals received from the media controller 302 .

[0062] The memory 300 also includes a plurality of bit cells which, in this illustrative example, are arranged in a memory bank or array 305 comprising “m” rows and “l” columns, wherein each bit cell has a unique physical address associated with an intersection of the row and the column, wherein the rows of bit cells are coupled to and addressable via respective signal lines arranged as word lines WL(0) through WL(m), while the columns of bit cells are coupled to and addressable via respective signal lines arranged as bit lines BL(0) through BL(l).

[0063] The memory 300 also includes read logic 308 for determining the memory state of the bit cell and generating an output (RQ) accordingly.

[0064] In this arrangement, to initialize the bit cells of a word line of the memory, and as Figure 3B As shown, media controller 302 generates an address signal (A0) to identify a first target bit cell or word to be initialized, wherein the address signal is provided on address bus 306 in a first clock cycle, wherein the target bit cell may be a first bit cell of a word on a first word line.

[0065] The media controller 302 also provides a data signal (DQ) on the data bus 307, wherein the data signal (DQ) defines the memory state to be stored or written to the first target bit cell.

[0066] like Figure 3B As shown, when decoding the address and data signals, the control logic 303, 304 drives the corresponding word lines and bit lines during the first clock cycle and stores the decoded (DQ) memory state in one or more first target bit cells of the word.

[0067] The media controller 302 may repeat this operation for each remaining address in the memory portion to be initialized, where the addresses (A1, A2, etc.) are repeated as follows: Figure 3B The successive clock cycles shown are sent from the media controller 302 to the control logic 303, 304.

[0068] It will therefore be appreciated that initializing different bit cells or words may comprise serial operations performed over multiple clock cycles, with data being stored in one bit cell or word in each clock cycle.

[0069] With this in mind, initializing a portion of memory (e.g., 32kb of memory) over multiple clock cycles may cause an application to be paused until initialization of that portion of memory is complete, which may result in processing delays in system 1.

[0070] Furthermore, writing a memory state to a bit cell will generate a write current. Taking STT-MRAM as an illustrative example, writing memory to a bit cell of STT-MRAM draws approximately 1.0 mA, where the current drawn will increase with the number of bit cells being written on the same clock cycle.

[0071] As an illustrative example, writing memory state to multiple bit cells comprising 32kb STT-MRAM memory in a single clock cycle will draw approximately 32A.

[0072] Writing similar sized portions (e.g., 32kb) of other types of NV memory (e.g., flash or PCM) in the same clock cycle may draw similar amounts of current so that the number of bit cells written in any one clock cycle is controlled to one word or less, depending on the application.

[0073] Figure 4A Schematically shows a block diagram of a media controller 418 and a memory 410 according to another specific embodiment of the controller device 8 and the memory 10, respectively. Figure 4B A timing diagram schematically illustrates initializing a portion of the memory 410 in an initialization operation within a clock cycle.

[0074] In this illustrative example, memory 410 includes a plurality of bit cells that are arranged in a memory bank or array 405 that includes "m" rows and "l" columns in this illustrative example, wherein each bit cell has a unique address defined by the intersection of the row and the column, as described above, wherein in this illustrative example the rows of bit cells are coupled to and addressable via respective first signal lines arranged as word lines WL(0) to WL(m), while the columns of bit cells are coupled to and addressable via second signal lines arranged as bit lines BL(0) to BL(l).

[0075] In the context of the present disclosure, a signal line includes a conductor for transmitting a signal, wherein a "word line" sends a signal to select one or more bit cells in a read operation or a write operation (e.g., an initialization operation), and a "bit line" sends a signal for controlling or driving one or more bit cells to change their memory state in a write operation or to sense their memory state in a read operation.

[0076] As described above, the media controller 418 may be configured to generate hardware / electrical signals such as address signals (A) and data signals (DQ) in response to an access request from a bus master (not shown) to initiate a read or write access to one or more target bit cells in the array 405 .

[0077] The media controller 418 may also be configured to generate one or more initialization signals, including an initialization address (IA) signal, an initialization range (IR) signal (wherein the IA and IR signals specify a range of memory locations / bit cells to be initialized in an initialization operation), and an initialization data (ID) signal, including hardware / electrical signals generated in response to instructions from a bus master. In combination with the above Figure 2B In the specific implementation discussed, the media controller 418 may respond to the write operation by delaying the write operation until after the initialization signals IA, ID, and ID are generated to the control logic 404. Figure 2D In the particular implementation discussed, according to block 208, the media controller 418 may respond to a request for a subsequent read operation before generating initialization signals IA, ID, and ID.

[0078] In some embodiments, the media controller 418 may generate an initialization (I) signal indicating a command to cause the memory 410 to perform an initialization operation. For example, the initialization signal (I) may include (one or more) encoded bits that the memory 410 decodes and recognizes as a command to initialize a portion of the memory 410. However, in alternative embodiments, the memory 410 may recognize one or more of an initialization address (IA) signal, an initialization range (IR) signal, and an initialization data (ID) signal as (one or more) commands to initialize a portion of the memory 410. For example, the initialization (I) signal may be encoded in one of these signals, such as in the lowest bit of the initialization address (IA) signal.

[0079] In this illustrative example, the initialization address (IA) signal includes a first address or starting address of the target portion, where the first address may refer to a bit cell, a word, or a word line.

[0080] The initialization range (IR) signal specifies the addresses up to the final address or end address of the target portion, whereby the range may start from the first address. In an example, the initialization range (IR) signal may be an offset value for specifying all addresses within the range from the first address to the last address. In an embodiment, the addresses of the target portion are consecutive bit cell addresses.

[0081] It should be understood that a range may specify a portion of memory, such as a word, a portion of a page, one or more pages, or up to an array of the entire memory.

[0082] In an example, the initialized address range (IR) signal may include one or more bits provided on a single input line to the memory 410. In other examples, the initialized address (IR) range signal may be provided on a bus such as the range bus 409.

[0083] The initialization data (ID) signal specifies a specific value, symbol, parameter, or condition to be stored in the bit cell of the target portion to represent the memory state as the "initialization state" of the bit cell therein, whereby the control logic 403, 404 that decodes the received initialization data (ID) signal will store the initialization state to the bit cell of the target portion.

[0084] In an embodiment, the initialization data (ID) signal may be provided to the memory 410 on a single input line, or on a bus line (e.g., data bus 407). In other embodiments, the initialization data (ID) signal may be a data (DQ) signal, and / or may be provided on the data bus 407 (e.g., data bus 407). Figure 3AIn another example, the initialization data (ID) signal may be optional, whereby when the memory 410 recognizes the received signal as a command to initialize a portion of the memory 410, a default initialization state (e.g., all "1" or "0") may be written to one or more bit cells during the initialization operation. Such received signals may include an initialization signal (I), an initialization address (IA) signal, and an initialization range (IR) signal.

[0085] In operation, media controller 418 may receive an access request from a bus master to initialize a target portion of memory 410 .

[0086] In response to the access request, and if Figure 4B As shown, the media controller 418 generates an initialization (I) signal indicating a command to cause the memory 410 to perform an initialization operation. As described above, the initialization (I) signal is optional. The media controller 418 may also generate an initialization address (IA) signal that specifies the first address of the target portion, and an initialization range (IR) signal that specifies all addresses of the target portion to be initialized.

[0087] The media controller 418 may further generate an initialization data (ID) signal that specifies an initialization state to be stored in the bit cells of the target portion. As described above, the initialization data (ID) signal may be optional, whereby in an alternative example, when the memory 410 recognizes the received signal as a command to initialize a portion of the memory 410, a default initialization state (e.g., all "1"s or "0"s) may be written to one or more bit cells during an initialization operation.

[0088] Control logic 403 and 404 may receive and decode an initialization signal (I), an initialization address signal (IA), and an initialization range (IR) signal to identify a bit cell of a target portion, and decode an initialization data signal (ID) to identify an initialization state to be stored therein.

[0089] Then, the control logic 403 and 404 may generate an initialization word line signal (IWL) to select a corresponding bit cell and an initialization bit line signal (IBL), and control or drive the selected bit cell to store a desired initialization state therein on the same clock cycle (eg, on a rising edge of a clock signal (CLK)).

[0090] Therefore, with Figure 3A In contrast to the arrangement of , multiple bit cells on different word lines can be initialized on the same clock cycle.

[0091] As mentioned above, as memory sizes and application requirements increase, the time to initialize enough memory to start an application (e.g., after boot or an application request) grows rapidly. Therefore, initializing a portion of the memory in a single clock cycle means that Figure 3A A startup process for an application or a portion of an initialization memory may be performed faster than with existing arrangements that are performed in multiple clock cycles.

[0092] although Figure 4B Initialization signals (I), (IA), (IR), and (ID) are depicted as being generated on the same cycle, but this is for illustrative purposes only, and these signals may be generated on different clock cycles. Figure 4B The initialization operation is depicted as being performed in the clock cycle immediately after the initialization signal is generated, but the initialization operation may be performed in any number of clock cycles after the initialization signal is generated. It should be understood that the clock signal may be generated by a PLL (phase locked loop), a CDR (clock data recovery), or any suitable generation method.

[0093] In an embodiment, the memory 410 may generate an acknowledgement signal (ACK) to acknowledge that the initialization operation is started and / or completed. Such acknowledgement may be performed after the read logic verifies the initialization state of the target bit cell.

[0094] Figure 4C A block diagram of a media controller 418 and a memory 410 according to another embodiment is schematically shown.

[0095] The media controller 418 and the memory 410 are the same as those in the above Figure 4A , where control logic 403 and 404 decode initialization signals (e.g., an initialization (I) signal, an initialization address (IA) signal, and an initialization range (IR) signal) to identify that an initialization operation is required, and identify a target portion to be initialized, and decode an initialization data (ID) signal to identify an initialization state to be stored in its target bit cell.

[0096] In this illustrative embodiment, memory 410 may include other logic in the form of logic gates whose outputs are used to select corresponding word lines, where in this illustrative example, the logic gates include an OR gate 410 .

[0097] As above Figure 4A and Figure 4BAs described in the above, the control logics 203 and 204 can select word lines having target bit cells coupled thereto by generating an initialization word line signal (IWL), and can control or drive these bit lines by generating an initialization bit line signal (IBL) to write or store an initialization state into the target bit cells coupled thereto, wherein the initialization word line signal (IWL) is used as the first input of each logic gate in the present embodiment.

[0098] also, Figure 4C The control logic 404 depicted in the figure generates an initialization select (IS) signal based at least in part on one or more initialization signals (e.g., (I), (IA), (IR), (ID)), wherein the initialization select (IS) signal is used as a second input to the corresponding logic gates 410 to cause all logic gates 410 to select all respective word lines when asserted.

[0099] The initialization state specified by the initialization data (ID) signal may then be written to all target bit cells by controlling the bit lines based at least in part on the decoded initialization data (ID) signal.

[0100] Thus, the output of logic gate 410 may be used to individually select one or more word lines using corresponding initialization word line signals (IWL) generated based at least in part on the initialization address (IA) signal and / or the initialization range (IR) signal.

[0101] Alternatively, logic gate 410 may be used to select all word lines in array 405 substantially simultaneously in response to the (IS) signal, rather than requiring control logic 403 to generate a separate initialize word line (IWL) signal.

[0102] This capability can reduce the time it takes to initialize multiple target bit cells compared to the time it would otherwise take.

[0103] Figure 4D Schematically shows a block diagram of a media controller 418 and a memory 410 according to another embodiment. The media controller 418 and the memory 410 may be the same as those described above. Figure 4C Similar to those described in .

[0104] Figure 4D The logic gates include AND gates 412 , wherein an initialization word line signal (IWL) is used as a first input to each AND gate 412 on each word line.

[0105] In the present embodiment, the control logic 404 may also generate an initialization select signal (IS) based at least in part on one or more initialization signals (e.g., (I), (IA), (IR), (ID)), wherein (IS) is provided as a second input to the AND gate 310 so that a target word line is selected only when the initialization select (IS) signal is asserted by the control logic 403 and 404 and one or more initialization word line signals (IWL) are asserted.

[0106] Thus, in this embodiment, the (IS) signal may be used as a control signal, wherein the initialized state of a particular bit cell(s) is stored or written only when (IS) and the corresponding initialized word line signal (IWL) are asserted.

[0107] This feature prevents erroneous initialization states from being written to non-target bit locations.

[0108] Although in Figure 4C and 4D Logic gates 411 and 412 are depicted as an OR gate and an AND gate, respectively, but the claims are not limited in this regard and the logic gates may include one or more logic gates arranged to provide any logic operation (e.g., exclusive OR (NOR), NAND (NAND), exclusive OR (NOR), etc.).

[0109] As described above, the memory 410 may be volatile memory or non-volatile (NV) memory, where the NV memory may include storage class memory (SCM).

[0110] Figure 5 It's the one above FIG. 4A to FIG. 4D Schematic diagram of an example architecture of memory array 405.

[0111] As described above, the memory array 515 includes a plurality of bit cells 502 arranged in rows (m) and columns (l) (in Figure 5 Four of these 502a-d are depicted in FIG), and these bit cells 502 can be addressed by control logic 503 and 504 as previously described.

[0112] In this illustrative example, each bit cell 502 a - d includes a storage element 505 coupled between a corresponding bit line and a first terminal of a conductive element 506 , while a second terminal of the conductive element 506 is coupled to a reference node 508 .

[0113] In this illustrative example, a third terminal (eg, a gate terminal) of the conductive element 506 is coupled to a corresponding word line, whereby an operational state of the conductive element can be controlled via the corresponding word line.

[0114] In the context of the present disclosure, a "conductive element" includes a circuit element that can control the current flow between its first and second terminals according to its operating state, and as described above, its operating state can be controlled via its third terminal. For example, when in the "on" or "closed" state, the conductive element 506 allows current to pass between its first and second terminals, while in the "off" or "open" state, the conductive element 506 blocks substantially all current from passing between its first and second terminals.

[0115] Furthermore, a "reference node" includes a node in a circuit that is maintained at a specific voltage level or at a specific voltage difference from another node in the circuit. In one example, the reference node 508 may include or be connected to a ground node. In other specific implementations, the reference node 508 may be maintained at a specific voltage relative to the voltage of the ground node.

[0116] In Figure 5 the illustrative example shown, the storage element 505 includes a correlated electron switch (CES) having a correlated electron material (CEM) sandwiched between conductive terminals.

[0117] By applying a first programming signal (PS1) including a first voltage (V SET ) (J(A / µm 2 )) at a first current density (J SET ) on the conductive terminals of the CES, the CES can be placed in a first impedance state including a low impedance or conductive state, where the first impedance state represents the first memory state of the bit cell.

[0118] By applying a second programming signal (PS2) including a second voltage (V RESET ) at a current density (J RESET ) on the conductive terminals of the CES, the CES can be placed in a second impedance state including a high impedance or insulating state, where the second impedance state represents the second memory state of the bit cell. In an embodiment, |V SET |> |V RESET | and |J RESET | > |J SET |.

[0119] In the context of the present disclosure, an "impedance state" refers to a detectable impedance state of the CES that represents the memory state of the associated bit cell.

[0120] Furthermore, it should be understood that the terms "low impedance state" and "high impedance state" are relative terms and are not specific to any particular values ​​of impedance, conductance, or capacitance. For example, a CES may be more conductive (and less insulating) when in a low impedance state than when the CES is in a high impedance state.

[0121] A programming signal (PS1 or PS2) for placing the CES in a specific impedance state may be generated or provided by the control logic 204 via each bit line. In addition, both the voltage (V) and the current density (J) of the programming signal may be controlled (e.g., by the control logic) to switch the impedance state of the CES. For example, when the CES is in a first impedance state and a voltage (V RESET ), CES will continue until the current density reaches the desired value (J RESET ) before switching to the second impedance state.

[0122] In this illustrative example, when the control logic 503 selects the corresponding word line, a programming signal (PS1) or (PS2) is applied to each bit line via the conductive elements 510 and 512, whereby, in this illustrative example, a programming control signal (PCS) is used to control the operating state of the conductive elements 510 and 512, which may be generated at the control logic 504 at least in part based on an initialization data (ID) signal from the media controller 504, or the programming control signal (PCS) may be based on a default initialization state to be written to one or more bit cells.

[0123] Conductive elements 510 and 512 may be transistors such as field effect transistors (FETs). Figure 5 In the illustrative example of , conductive element 510 is an nFET and conductive element 512 is a pFET such that when PCS is high (e.g., logic 1), conductive element 510 is in a closed or “on” state and conductive element 512 is in an open or “off” state, thereby applying a first programming signal (PS1) to the target CES.

[0124] Similarly, when PCS is low (eg, logic 0), conductive element 512 is in a closed or “on” state and conductive element 510 is in an open or “off” state, thereby applying a second programming signal (PS2) to the bit line of the target CES.

[0125] Thus, it will be appreciated that the impedance state of one or more CESs may be controlled by applying the first or second programming signal ( PS1 or PS2 ) to the one or more CESs based at least in part on an initialization data (ID) signal from the media controller 504 .

[0126] In typical operation, when writing to a bit cell including a CES storage element using the first programming signal (PS1) or the second programming signal (PS2), the write current is reduced compared to writing to bit cells of other types of memory (eg, STT-MRAM).

[0127] Thus, it will be appreciated that it is possible to write to or initialize a large number of CES storage elements in a single cycle with reduced write currents compared to other storage types.

[0128] It will be understood that the above-described conductive elements 506, 510, and 412 need not be limited to FETs, and may be any suitable type of transistor, such as a bipolar junction transistor (BJT). It will also be understood that conductive elements 406, 410, 412 are also not limited to being transistors, and other types of devices, such as diodes, variable resistors, etc., may also be used as conductive elements, and the claimed subject matter is not limited in this respect.

[0129] It should also be understood that the present architecture is provided only as an illustrative example, and any suitable architecture for a memory array may be used. For example, array 515 is not limited to having Figure 5 Rather, the techniques may be used with different storage elements arranged to store a value, symbol, parameter, or condition as a memory state of an associated bit cell. As illustrative examples, storage element 505 may include one or more resistors (e.g., variable resistors), one or more capacitors, and / or one or more transistors that are arranged to store a value, symbol, parameter, or condition as a memory state of an associated bit cell.

[0130] Figure 6 An example flow chart illustrating a process of initializing a portion of memory is shown.

[0131] In step S500, the process starts.

[0132] In step S502, a bus master such as a processor generates software instructions that specify an access request for initializing a portion of memory (e.g., a word, a page, an entire array, the entire memory, etc.) and sends these instructions to a memory controller or a media controller. As described above, in the context of the present disclosure, initialization of a portion of memory generally refers to the process of writing the same value, symbol, parameter, or condition to all bit cells of the target portion so that all bit cells represent the same initialization state.

[0133] In step S504, the memory controller or the media controller converts the software instructions into hardware / electrical signals and sends the signals to the memory.

[0134] In this embodiment, the hardware signals include: an initialization (I) signal, an initialization address (IA) signal including the address of a portion to be initialized, an initialization range (IR) signal specifying a range of addresses in a portion of a memory, and an initialization data (ID) signal specifying an initialization state to be written to a specified bit cell.

[0135] At step S506 , control logic in the memory decodes the hardware signal from the memory controller or media controller and at step S508 selects the appropriate word line and writes the initialization state to the bit cells of the target portion based at least in part on the initialization data (ID) signal.

[0136] The bit cell includes (one or more) storage elements for storing a value, symbol, parameter, or condition as a memory state of the associated bit cell. In an embodiment, the (one or more) storage elements include (one or more) CES, whereby initializing the CES means applying a programming signal to place the CES in a high impedance state or a low impedance state based at least in part on an initialization data (ID) signal. Using CES as a storage element in an array can reduce write current compared to other types of storage elements (e.g., STT-MRAM, NAND or NOR flash memory, etc.).

[0137] At step 510 , the control logic optionally generates an acknowledgement signal (ACK) to confirm that the initialization operation has been initiated and / or completed.

[0138] At step 512, the process ends.

[0139] The specific embodiments discussed above are directed to a method comprising: maintaining a record of pending requests for initializing a state of a portion of a memory in a first buffer, the pending requests comprising at least a first pending request for initializing a state of a first portion of the memory; and in response to detecting the first pending request for initializing the first portion of the memory, returning values ​​to service a request for an operation to read a second portion of the memory without accessing the second portion of the memory, the values ​​comprising a value representing the initialization state. In one specific implementation, accessing the second portion of the memory comprises sending one or more signals on a memory bus connected to the memory, the one or more signals indicating a physical address corresponding to the second portion of the memory. In another specific implementation, the method further comprises: in response to determining that the request for an operation to read from the second portion of the memory was initiated or received after the initiation or receipt of the pending request for initializing the state of the first portion of the memory, returning values ​​to service the request for an operation to read the second portion of the memory. In another specific implementation, the method further comprises: determining, based at least in part on the states of the first and second buffers, that the request to read the second portion of the memory was initiated or received after the initiation or receipt of the first pending request for initializing the state of the first portion of the memory. In another specific implementation, after receiving a pending request to initialize a particular portion of memory, a request is received from the processing unit to read from a second portion of memory. In another specific implementation, the first portion of memory includes bit cells corresponding to a first range of physical memory addresses, and the second portion of memory includes bit cells corresponding to a second range of physical memory addresses, and the method further includes returning a value to service the request for an operation to read the second portion of memory in response to an overlap of the first range of physical memory addresses and the second range of physical memory addresses.

[0140] In the foregoing description, various details are described to provide an understanding of the various embodiments. However, it will be appreciated that the various embodiments may be practiced without the specific details.

[0141] In other cases, well-known methods, processes, components, and logic are not described in detail to avoid obscuring the specific embodiments. In addition, various means may be used to perform various aspects of the embodiments, such as hardware (e.g., circuits such as integrated semiconductor circuits), software (e.g., computer program code), or some combination of hardware and software.

[0142] For purposes of this disclosure, reference to "logic" shall mean hardware, software, or some combination thereof.

[0143] As mentioned above, and as Figure 5As shown, the storage elements of the bit cells of the array 505 may include CES. In the present context, CES may represent a sudden transition of a conductor / insulator from a low impedance (and low capacitance) state to a high impedance (and high capacitance) state, or vice versa, due to electronic relationships in the CEM rather than a solid-state structural phase change (e.g., the crystalline / amorphous change that occurs in a phase change memory (PCM) device or the filamentation that occurs in a resistive RAM device).

[0144] In embodiments, the abrupt conductor / insulator transition in a CEM may be in response to a quantum mechanical phenomenon, as opposed to melting / solidification or filament formation. Such quantum mechanical transitions between impedance states in a CES may be understood in any of several ways.

[0145] In an embodiment, the quantum mechanical transition between the first and second impedance states may be understood in terms of a Mott transition. For example, when a first Mott transition condition is met, the CEM may switch from a high impedance state to a low impedance state, and when a second Mott transition condition is met, the CEM may switch from a low impedance state to a high impedance state. Different Mott transition conditions are described in further detail below.

[0146] In one aspect, the impedance of the CES in the second impedance state may be more than 100 times greater than the impedance of the CES in the first impedance state.

[0147] In an embodiment, the CEM comprises a switching region (S) arranged in electrical contact with (e.g., sandwiched between) a conductive region (C) in a (C / S / C) arrangement of semiconductors (e.g., in a stacked arrangement). The conductive region (C) may comprise any suitable material, and may comprise a transition metal oxide, and may also comprise any material having metal-like properties, including, for example, polysilicon or a doped semiconductor. In an embodiment, the conductive region (C) may additionally or alternatively comprise a material selected from the group comprising aluminum, cadmium, chromium, cobalt, copper, gold, iron, manganese, mercury, molybdenum, nickel, palladium, rhenium, ruthenium, silver, tin, titanium, vanadium, and zinc (which may be linked to cations such as oxygen or other types of ligands) or combinations thereof.

[0148] According to an embodiment, the switching region (S) may include any transition metal oxide (TMO) material, for example, perovskite, Mott insulator, charge exchange insulator, and Anderson disordered insulator.

[0149] In a specific implementation, the switching region (S) material may include switching materials such as nickel oxide, cobalt oxide, iron oxide, yttrium oxide, and perovskites such as Cr-doped strontium titanate, lanthanum titanate, and the manganite family, including praesidium calcium manganite and praesydium lanthanum manganite, to provide just a few examples. Specifically, oxides incorporating elements with incomplete d and f orbital shells may exhibit sufficient resistive switching properties to be used as switching region (S) materials. In an embodiment, the CES may be prepared without electroforming.

[0150] Without departing from the claimed subject matter, other implementations may employ other transition metal compounds as the switching region (S) material. For example, {M(chxn)2Br}Br2, where M may include Pt, Pd, or Ni, and chxn includes 1R,2R-cyclohexanediamine, and other such metal complexes may be used without departing from the claimed subject matter.

[0151] In one aspect, the CEM can include a material that is a TMO variable resistance material, but it should be understood that these are exemplary only and are not intended to limit the claimed subject matter.

[0152] The specific implementation method may also adopt other variable resistor materials. Although nickel oxide NiO is disclosed above as a specific TMO, the NiO material may also be doped with foreign ligands, which can stabilize the variable resistor characteristics. Specifically, the NiO variable resistor material disclosed herein may include a carbon-containing ligand, which may be represented by NiO(Cx). Here, those skilled in the art can simply determine the x value for any specific carbon-containing ligand and any specific combination of carbon-containing ligands and NiO by balancing the valence. In another specific example, NiO doped with foreign ligands can be expressed as NiO(Lx), where Lx is a ligand element or compound, and x indicates the number of units of the ligand used for one unit of NiO. Those skilled in the art can simply determine the x value for any specific ligand and any specific combination of ligands and NiO or any other transition metal by balancing the valence.

[0153] Furthermore, the terminals may include the same material as the conductive region (C) so that the conductive region (C) may function as a terminal. In embodiments where the materials used for the terminals and the conductive region (C) are different, it is preferred that the different materials are matched to reduce the effects of boundary interactions or surface defects that may otherwise affect the performance of the CES. For example, the materials should be matched to ensure that the electrical properties (e.g., electrical conductivity) and / or chemical properties (e.g., thermal expansion matching coefficients) of the CEM and that the terminals do not negatively affect the operation of the CES.

[0154] Although the above embodiments depict a memory array comprising rows and columns, the claims are not limited in this regard, and the bit cells may be arranged in any suitable configuration that are selected and driven via signal lines where appropriate.

[0155] Computer program code for performing operations of the present technology may be written in any combination of one or more programming languages, including object-oriented programming languages ​​and conventional procedural programming languages. For example, program code for performing operations of the present technology may include source code, object code, or executable code in a conventional programming language (interpreted or compiled) such as C, or assembly code, code for setting up or controlling an ASIC (application specific integrated circuit) or FPGA (field programmable gate array), or code such as Verilog. TM Or code in a hardware description language such as VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language).

[0156] Depending on the embodiment, the devices described herein may be formed in a device in combination with conductive elements formed by the same or different processes. In an example implementation, a memory device may be formed in combination with conductive elements using different and / or complementary process technologies such as complementary metal oxide semiconductor (CMOS) technology. For example, conductive elements such as NFET and PFET devices may be formed using well-known processes and techniques.

[0157] References in the specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one implementation. The phrase "in one embodiment" appearing in various places in the specification may or may not all refer to the same embodiment.

[0158] Likewise, in the specification and claims, the terms "coupled" and "connected" and their derivatives may be used. In some embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" may refer to two or more elements being in direct physical or electrical contact. However, "coupled" may also refer to two or more elements that may not be in direct contact with each other, but may still collaborate or interact with each other.

[0159] It will be apparent to those skilled in the art that many improvements and modifications may be made to the foregoing exemplary embodiments without departing from the scope of the present technology.

Claims

1. A controller device, comprising: a first buffer queue for maintaining a record of pending requests to initialize a state of a portion of a memory, the pending requests comprising at least a first pending request to initialize a state of a first portion of the memory, the record of pending requests to initialize a state comprising a receipt or initiation time of the pending request to initialize a state of the portion of the memory; a second buffer queue, separate from the first buffer queue, the second buffer queue being used to maintain a record of pending write operation requests for writing to the portion of the memory, the record of pending write operation requests including a receipt or initiation time of the pending write operation request; as well as circuitry for delaying initiation of a write operation for servicing a write operation request maintained in the second buffer queue, the write operation addressed to the second portion of the memory, until completion of an operation for servicing the first pending request to initialize a state of the first portion of the memory, Wherein, the circuit for delaying the start of the write operation is also used to: delay the start of the write operation in response to determining that the write operation request maintained in the second buffer queue is initiated or received after the initiation or reception of the first pending request for initializing the state of the first part of the memory, and the determination is based on the reception or initiation time of the pending request for initialization and the reception or initiation time of the pending write operation request.

2. The controller device according to claim 1, wherein: Initiation of the write operation includes sending one or more signals on a memory bus connected to the memory, the one or more signals indicating a physical address corresponding to a bit cell in the second portion of the memory.

3. The controller device according to claim 1, and further comprising: Circuitry is configured to determine, based at least in part on the states of the first buffer queue and the second buffer queue, that the write operation request was initiated or received after the initiation or receipt of the first pending request to initialize the state of the first portion of the memory.

4. The controller device according to any one of claims 1 to 3, wherein: The write operation request maintained in the second buffer queue is received from a processing unit subsequent to receipt of the first pending request to initialize the first portion of the memory.

5. The controller device according to any one of claims 1 to 3, wherein: The first portion of the memory includes bit cells corresponding to a first range of physical memory addresses, and the second portion of the memory includes bit cells corresponding to a second range of physical memory addresses, and the circuit configured to delay the start of the write operation is also used to: in response to determining an overlap between the first range of physical memory addresses and the second range of physical memory addresses, delay the start of the write operation for servicing the write operation request maintained in the second buffer queue.

6. A controller device according to any one of claims 1 to 3, and further comprising: Circuitry for servicing a request for a read operation addressed to a third portion of the memory, the circuitry servicing the request for a read operation addressed to the third portion of the memory to return a value representing an initialized state in response to detecting the first pending request to initialize the first portion of the memory without accessing the third portion of the memory.

7. The controller device according to claim 6, wherein: The first portion of the memory includes bit cells corresponding to a first range of physical memory addresses, and the third portion of the memory includes bit cells corresponding to a third range of physical memory addresses, and wherein the circuit for servicing the request for a read operation addressed to the third portion is further used to: further in response to determining an overlap between the first range of physical memory addresses and the third range of physical memory addresses, return a value representing the initialization state without accessing the third portion of the memory.

8. The controller device according to claim 1, wherein: The circuit for delaying the start of the write operation is configured to delay the start of the write operation in response to detecting at least a partial overlap of the first portion of the memory to be initialized and the second portion of the memory to be written.

9. A processing method of a controller device, comprising: maintaining in a first buffer queue a record of pending requests to initialize state of a portion of a memory, the pending requests to initialize state comprising at least a first pending request to initialize state of a first portion of the memory, the record comprising a receipt or initiation time of the pending request to initialize state of the portion of the memory; maintaining a record of pending write operation requests for writing to the portion of the memory in a second buffer queue, the second buffer queue being maintained separately from the first buffer queue, the record of pending write operation requests including a receipt or initiation time of the pending write operation request; and In response to determining that the write operation request maintained in the second buffer queue was initiated or received after the initiation or receipt of the first pending request for initializing the state of the first portion of the memory, delaying the start of a write operation for servicing the write operation request maintained in the second buffer queue and addressed to the second portion of the memory until the operation for servicing the first pending request for initializing the state of the first portion of the memory is completed, the determination being based on a receipt or initiation time of the pending request for initialization and a receipt or initiation time of the pending write operation request.

10. The method according to claim 9, wherein: Initiation of the write operation includes sending one or more signals on a memory bus connected to the memory, the one or more signals indicating an address corresponding to a bit cell in the second portion of the memory.

11. The method according to claim 9, and further comprising: Based at least in part on the state of the first buffer queue and the state of the second buffer queue, it is determined that the write operation request maintained in the second buffer queue was initiated or received after the initiation or receipt of the first pending request to initialize the state of the first portion of the memory.

12. The method according to any one of claims 9 to 11, wherein: The write operation request maintained in the second buffer queue is received from a processing unit subsequent to receipt of the first pending request to initialize the first portion of the memory.

13. The method according to any one of claims 9 to 11, wherein: The first portion of the memory includes bit cells corresponding to a first range of physical memory addresses, and the second portion of the memory includes bit cells corresponding to a second range of physical memory addresses, and wherein the method further includes delaying the start of the write operation in response to determining an overlap between the first range of physical memory addresses and the second range of physical memory addresses.

14. A method according to any one of claims 9 to 11, and further comprising: A request for a read operation addressed to a third portion of the memory is serviced by returning a value representative of an initialization state without accessing the third portion of the memory in response to detecting the first pending request to initialize the first portion of the memory.

15. The method according to claim 14, wherein: The first portion of the memory includes bit cells corresponding to a first range of physical memory addresses, and the third portion of the memory includes bit cells corresponding to a third range of physical memory addresses, and wherein the method further includes: servicing the request for the read operation by returning a value representing the initialization state without accessing the third portion of the memory in further response to determining an overlap between the first range of physical memory addresses and the third range of physical memory addresses.

16. A controller device comprising: a first buffer queue for maintaining a record of pending initialization requests to initialize the state of a portion of a memory, the pending initialization requests comprising at least a first pending initialization request to initialize the state of a first portion of the memory; a second buffer queue for providing a read queue to maintain a record of pending read operation requests, the read queue including at least a first pending read operation request specifying a portion of the memory to be read; as well as circuitry for, in response to detecting the first pending initialization request to initialize a state of the first portion of the memory, returning a value to service a request for an operation to read the second portion of the memory without accessing the second portion of the memory, the value comprising a value representing an initialization state; The circuit is also used to: in response to detecting the first pending initialization request and in response to detecting at least partial overlap between the designated portion of the memory to be initialized and the designated portion of the memory to be read, return a value to serve the first pending read operation request without accessing the designated portion of the memory to be read, wherein the value represents an initialization state.

17. The controller device of claim 16, wherein: Accessing the second portion of the memory includes sending one or more signals on a memory bus connected to the memory, the one or more signals indicating a physical address corresponding to the second portion of the memory.

18. A controller device according to claim 16 or claim 17, wherein the circuit for returning a value to service a request for an operation to read the second portion of the memory is also used to: in response to determining that the request for an operation to read from the second portion of the memory was initiated or received after the initiation or receipt of the first pending initialization request to initialize the state of the first portion of the memory, return a value to service the request for an operation to read the second portion of the memory.

19. The controller device of claim 18, and further comprising: Circuitry for determining, based at least in part on the states of the first buffer queue and the second buffer queue, that the request to read the second portion of the memory was initiated or received after the initiation or receipt of the first pending initialization request to initialize the state of the first portion of the memory.

20. A controller device according to claim 16 or claim 17, wherein: The record includes a receipt or initiation time of the pending initialization request to initialize a state of a portion of the memory; as well as The request to read the second portion of the memory is obtained from a read request received from a processing unit after an initiation or receipt time in the record of the first pending initialization request to initialize the first portion of the memory.

21. A controller device according to claim 16 or claim 17, wherein: The first portion of the memory includes bit cells corresponding to a first range of physical memory addresses, and the second portion of the memory includes bit cells corresponding to a second range of physical memory addresses, and wherein the circuit for returning a value to service a request for an operation to read the second portion of the memory is further configured to return a value to service the request for an operation to read the second portion of the memory in response to determining an overlap between the first range of physical memory addresses and the second range of physical memory addresses.

Images