Embedded chip and method for manufacturing the same

Abstract

The present application provides an embedded chip and a method for manufacturing the same. The manufacturing method includes: providing a conductive substrate; arranging a bare core and a conductive boss on the conductive substrate, arranging a connecting terminal on the bottom surface of the bare core, and electrically connecting the connecting terminal to the conductive substrate; arranging a first insulating layer on the bare core and the conductive boss; arranging a conductive blind hole on the top of the first insulating layer corresponding to the conductive boss, the conductive blind hole exposes the conductive boss, and arranging a fan-out terminal electrically connected to the conductive boss in the conductive blind hole, and the bottom of the conductive boss is electrically connected to the connecting terminal through the conductive substrate, so that the connecting terminal fans out through the conductive boss and the fan-out terminal. Therefore, the thickness of the conductive blind hole to be opened does not need to be too thick, and only the distance between the first insulating layer and the conductive boss needs to be opened, which simplifies the process, avoids the situation where the laser cannot penetrate due to the thicker package, and also avoids the large vibration and low precision caused by mechanical drilling.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to an embedded chip and a manufacturing method thereof. Background Art

[0002] With the development of high-frequency and high-speed requirements for electronic products, traditional wire bonding packaging and flip-chip packaging interconnection methods are difficult to meet the needs of high-frequency and high-speed signal transmission. Therefore, more and more chips use substrate embedding or wafer-level fan-out processes to achieve bare chip packaging, reduce the size of package interconnection, and achieve the signal integrity requirements of high-frequency and high-speed transmission of chips. However, when the chip's connection terminal and its fan-out position are not on the same side of the existing embedded packaging solution, the fan-out process of the connection terminal will be very complicated. Summary of the invention

[0003] The main technical problem solved by the present application is to provide an embedded chip and a manufacturing method thereof, which can simplify the process of fanning out the connection terminals.

[0004] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a method for manufacturing an embedded chip, the manufacturing method comprising: providing a conductive substrate; arranging a bare core and at least one conductive boss on the conductive substrate, the bare core comprising a top surface and a bottom surface arranged opposite to each other, a connecting terminal being arranged on the bottom surface, and the connecting terminal being electrically connected to the conductive substrate; arranging a first insulating layer on the bare core and the conductive boss; arranging a conductive blind hole on the first insulating layer corresponding to the top of the conductive boss, the conductive blind hole exposing the conductive boss, and further arranging a fan-out terminal electrically connected to the conductive boss in the conductive blind hole, the bottom of the conductive boss being electrically connected to the connecting terminal through the conductive substrate, so that the connecting terminal fans out through the conductive boss and the fan-out terminal.

[0005] In order to solve the above technical problems, another technical solution adopted in the present application is: to provide an embedded chip, the embedded chip comprising: a conductive substrate; a conductive boss, arranged on the conductive substrate; a bare core, arranged on the conductive substrate, the bare core comprising a top surface and a bottom surface arranged opposite to each other, a connecting terminal is arranged on the bottom surface, and the connecting terminal is electrically connected to the conductive substrate; a dielectric layer, arranged on the bare core and the conductive boss, the dielectric layer is provided with a conductive blind hole on the top of the conductive boss; a fan-out terminal, arranged in the conductive blind hole and electrically connected to the conductive boss, the bottom of the conductive boss is electrically connected to the connecting terminal through the conductive substrate, so that the connecting terminal fans out through the conductive boss and the fan-out terminal.

[0006] The present application sets a conductive boss and a bare core on a conductive substrate, and a conductive blind hole is opened on the top of the insulating layer corresponding to the conductive boss. A fan-out terminal electrically connected to the conductive boss is set in the conductive blind hole. The connection terminal on the bottom of the bare core can be electrically connected to the conductive boss through the conductive substrate, and then fanned out to the outside of the insulating layer through the conductive boss and the fan-out terminal. The thickness of the conductive blind hole that needs to be opened is only the thickness of the insulating layer corresponding to the top of the conductive boss, and does not need to be too thick, which can simplify the process, avoid the situation where the laser cannot penetrate due to the thick package, and also avoid the large vibration and low precision caused by mechanical drilling. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a schematic flow chart of a method for manufacturing an embedded chip provided in an embodiment of the present application;

[0008] Figure 2 It is a schematic flow chart of another method for manufacturing an embedded chip provided in an embodiment of the present application;

[0009] Figure 3a It corresponds to Figure 2 A process flow diagram of step S10 is shown;

[0010] Figure 3b It corresponds to Figure 2 Another process flow diagram of step S10 is shown;

[0011] Figure 3c It corresponds to Figure 2 Another process flow diagram of step S10 is shown;

[0012] Figure 4 It corresponds to Figure 2 The process flow diagram of step S20 is shown;

[0013] Figure 5 It corresponds to Figure 2 The process flow diagram of step S30 is shown;

[0014] Figure 6 It corresponds to Figure 2 The process flow diagram of step S40 is shown;

[0015] Figure 7 It corresponds to Figure 2 The process flow diagram of step S50 and the structural diagram of an embedded chip according to an embodiment of the present application are shown;

[0016] Figure 8 is a schematic diagram of the structure of another embedded chip provided in an embodiment of the present application;

[0017] Fig. 9This is a schematic diagram of the structure of another embedded chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described below are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0019] In order to make the technical solution provided by the embodiments of the present application clearer, the following embodiments describe the technical solution of the present application in detail with reference to the accompanying drawings.

[0020] See also Figure 1 , Figure 1 FIG. 1 is a flow chart of a method for manufacturing an embedded chip provided in an embodiment of the present application. Figure 1 As shown, the manufacturing method of this embodiment includes the following steps:

[0021] Step S1: providing a conductive substrate.

[0022] Step S2: a bare core and at least one conductive boss are arranged on the conductive substrate, wherein the bare core comprises a top surface and a bottom surface arranged opposite to each other, a connecting terminal is arranged on the bottom surface, and the connecting terminal is electrically connected to the conductive substrate.

[0023] Step S3: Disposing an insulating layer on the bare core and the conductive bosses.

[0024] Step S4: a conductive blind hole is set on the top of the insulating layer corresponding to the conductive boss, the conductive blind hole exposes the conductive boss, and a fan-out terminal electrically connected to the conductive boss is further set in the conductive blind hole, and the bottom of the conductive boss is electrically connected to the connecting terminal through the conductive substrate, so that the connecting terminal is fanned out through the conductive boss and the fan-out terminal.

[0025] Therefore, in this embodiment, a conductive boss and a bare core are arranged on a conductive substrate, and a conductive blind hole is opened on the top of the insulating layer corresponding to the conductive boss. A fan-out terminal electrically connected to the conductive boss is arranged in the conductive blind hole. The connection terminal on the bottom of the bare core can be electrically connected to the conductive boss through the conductive substrate, and then fanned out to the outside of the insulating layer through the conductive boss and the fan-out terminal. The thickness of the conductive blind hole that needs to be opened does not need to be too thick, and only the thickness of the insulating layer corresponding to the top of the conductive boss needs to be opened, which simplifies the process, avoids the situation where the laser cannot penetrate due to the thick package, and also avoids the large vibration and low precision caused by mechanical drilling.

[0026] See also Figure 2 , Figure 2FIG. 3 is a schematic diagram of a process for manufacturing another embedded chip provided in an embodiment of the present application. Figure 7 It corresponds to Figure 2 The process flow diagram of the manufacturing method shown in FIG. Figure 2 As shown, the manufacturing method of this embodiment includes the following steps:

[0027] Step S10: providing a conductive substrate 100 .

[0028] The conductive substrate 100 may have various structures, and the structure may be selected according to the number of connection terminals of the bare core.

[0029] Specifically, if the bare core has only one connection terminal, there is no need to consider the short circuit problem between the connection terminals. In order to ensure the electrical connectivity between the connection terminals and the conductive bosses, the surface of the conductive substrate 100 may be entirely a metal structure. Figure 3a To illustrate step S10, the conductive substrate 100 can be a single-layer metal plate, such as a copper plate, etc. Its thickness can be greater than or equal to 0.2 mm. Based on this, the entire metal plate can be used as a circuit to electrically connect the connection terminal and the conductive boss, ensuring the stability of the electrical connection.

[0030] If the bare core has two or more connecting terminals, considering the insulation problem between the connecting terminals, a conductive substrate 100 with wires on the surface can be selected, and the connecting terminals can be electrically connected to the corresponding conductive bosses through the insulated wires.

[0031] Specific combination Figure 3b To illustrate step S10, the conductive substrate 100 may include an insulating substrate 101 and a wire 102 disposed on the surface thereof. The thickness of the conductive substrate 100 may be greater than or equal to 0.5 mm. The wire 102 includes two wires insulated from each other. The number of the wires 102 is equal to the number of the connection terminals, and each wire 102 may be electrically connected to the connection terminal of the corresponding bare core, which will be described in detail below.

[0032] In addition, Figure 3c To illustrate step S10, the conductive substrate 100 may also be a multi-layer composite structure. Specifically, the conductive substrate 100 includes a first conductive layer 103, an insulating layer 104, and a second conductive layer 105 stacked in sequence.

[0033] The materials of the first conductive layer 101 and the second conductive layer 102 may be the same or different. For example, they may both be made of copper or other materials, and the insulating layer 103 may be made of aluminum oxide. Based on this, the conductive substrate 100 may be a ceramic substrate.

[0034] The first conductive layer 103 may be provided with a conductive line 102. Specifically, the conductive line 102 may be formed by patterning at least a portion of the metal of the first conductive layer 103. The function of the conductive line 102 is as described above, and will not be repeated here.

[0035] Combination Figure 3a-3c Regardless of the structure of the conductive substrate 100, at least one side thereof has metal, for example Figure 3a The single-layer metal plate shown, for example Figure 3b-3c The surface of the conductive substrate 100 is provided with metal wires. Based on this, when the conductive substrate 100 is used as a carrier to package a chip, usually, holes are not punched on one side of the conductive substrate 100, but the other side is selected for punching.

[0036] The principle of using each conductive substrate 100 to package the chip is similar, so the following steps of this embodiment will be described as follows unless otherwise specified. Figure 3b The conductive substrate 100 is shown for detailed description.

[0037] Step S20 : ​​a frame 200 is disposed on the conductive substrate 100 , wherein the frame 200 is provided with a first through slot 201 and a second through slot 202 spaced apart from each other.

[0038] Combination Figure 4 Step S20 is described, the frame 200 includes two second through slots 202 and one first through slot 201. The first through slot 201 and the second through slot 202 expose the conductive substrate 100. More specifically, part of the wire 102 of the conductive substrate 100 is located in the first through slot 201 and the second through slot 202, forming an exposed state.

[0039] The two second through slots 202 will be provided with conductive bosses correspondingly, and the first through slot 201 will be provided with a bare core correspondingly.

[0040] Step S30: a bare core 300 is disposed in the first through-groove 201 , and a conductive boss 400 is disposed in the second through-groove 202 , so that the bare core 300 and the conductive boss 400 are disposed at intervals.

[0041] Combination Figure 5 To illustrate step S30 , the thickness of the frame 200 is greater than or equal to the thickness of the bare core 300 and the thickness of the conductive boss 400 . The width of the first through slot 201 may be greater than the width of the bare core 300 , and the width of the second through slot 202 may be greater than the width of the conductive boss 400 .

[0042] The side surface of the bare core 300 is spaced apart from the side wall of the first through-slot 201, and the side surface of the conductive boss 400 is also spaced apart from the side wall of the second through-slot 202. The gap between the two may be in the range of (10, 150) microns.

[0043] The bare core 300 includes a top surface 301 and a bottom surface 302 , and a connection terminal 303 is disposed on the bottom surface 302 . Figure 5 The bare core 300 shown includes two connection terminals 303. Here, the connection terminals 303 can be electrically connected to external circuits through a conductive medium. For example, they can be I / O (input / output) terminals, including input terminals and output terminals, usually in the form of pads or copper pillars.

[0044] In other embodiments, other numbers of connection terminals 303 may be provided.

[0045] In step S30, a connection layer 304 may be disposed at a position of the conductive substrate 100 corresponding to the first through groove 201, and the connection terminal 303 of the bare core 300 is electrically connected to the conductive substrate 100 through the connection layer 304. The connection layer 304 may be metal paste or the like.

[0046] In combination with step S20, the two wires 102 of the conductive substrate 100 each have a portion located in the first through slot 201. Based on this, step S30 is more specifically to respectively set connection layers 304 on the two sections of the wires 102 located in the first through slot 201. After the bare core 300 is set in the first through slot 201, the two connection terminals 303 on the bottom surface 302 thereof are respectively electrically connected to the corresponding connection layers 304, so as to be electrically connected to the corresponding wires 102 through the electrically connected connection layers 304.

[0047] That is to say, the number of the connection layers 304 is equal to the number of the connection terminals 303 and corresponds one to one.

[0048] In the second through slot 202 , a conductive boss 400 may be provided by electroplating. The conductive boss 400 is electrically connected to the wire 102 located in the second through slot 202 . Thus, the wire 102 realizes the connection between the connection terminal 303 and the conductive boss 400 .

[0049] like Figure 5 As shown, the number of conductive bosses 400 and connecting terminals 303 is the same, and they correspond one to one. The number of connecting layers 304 and wires 102 and connecting terminals 303 is also the same, and they correspond one to one. That is, one connecting terminal 303 is electrically connected to one conductive boss 400 through one connecting layer 304 and one wire 102.

[0050] If the conductive substrate 100 is Figure 3aThe structure shown in the figure should be used in the case where there is only one connection terminal 303 in the bare core 300. Then the frame 200 in step S20 only includes one first through slot 201 and one second through slot 202. In step S30, a connection layer 304 can be directly arranged in the first through slot 201, and the connection terminal 303 can be electrically connected to the conductive base 100 of the metal plate through the connection layer 304. The conductive boss 400 is the same as described above.

[0051] If the conductive substrate 100 is Figure 3c In the structure shown in FIG. 1 , the frame 200 is arranged on the first conductive layer 103 in step S20. And step S30 is more specifically to arrange the conductive boss 400 and the bare core 300 on the first conductive layer 103. The specific arrangement is as described above and will not be repeated here.

[0052] Step S40 : disposing an insulating layer 500 on the bare core 300 and the conductive boss 400 , the insulating layer 500 further covering the surface of the frame 200 , filling the gap between the bare core 300 and the first through groove 201 , and the gap between the conductive boss 400 and the second through groove 202 .

[0053] The insulating layer 500 can be a semi-cured resin material, such as epoxy resin or bismaleimide-triazine resin and inorganic fillers, etc. The thickness of the material can be selected between 20 microns and 100 um as needed. The insulating layer 500 can also be a photosensitive sheet material, which can be completely cured after heating. Of course, the insulating layer 500 can also be a non-photosensitive sheet material.

[0054] Combination Figure 6 Step S40 is described below. In this embodiment, the insulating layer 500 is first covered on the frame 200, and then the insulating layer 500 is cured. Specifically, the insulating layer 500 is pressed onto the surface of the frame 200 under high temperature and high pressure and completely cured, thereby covering the surface of the frame 200, the top surface 301 of the bare core 300, and the top of the conductive boss 400. The insulating layer 500 can also be liquefied under high temperature and high pressure and flow between the bare core 300 and the first through groove 201 and between the conductive boss 400 and the second through groove 202.

[0055] As described above, the thickness of the first through groove 201 is greater than the thickness of the bare core 300, so when the insulating layer 500 is pressed, the frame 200 is the first to bear the force. This can avoid the situation where the bare core 300 is the main force bearer when the insulating layer 500 is pressed, thereby avoiding the situation where the bare core 300 is damaged due to the bare core 300 being the main force bearer when the insulating layer 500 is pressed.

[0056] In this embodiment, the material of the insulating layer 500 can be the same as that of the frame 200, so the insulating layer 500 and the frame 200 after curing form an integrated structure. The integrated structure can be collectively referred to as a dielectric layer 600.

[0057] Based on the above, in this embodiment, the insulating layer 500 is provided by laminating once. In other embodiments, the insulating layer 500 may be provided by laminating twice.

[0058] Specifically, the insulating layer 500 is first placed only in the first through groove 201 and the second through groove 202, and the insulating layer 500 in the first through groove 201 and the second through groove 202 is subjected to high temperature and high pressure treatment for the first time, so that the insulating layer 500 is pressed to the top surface of the bare core 300 and the conductive boss 400 under high temperature and high pressure, and liquefied and flows between the bare core 300 and the first through groove 201 and between the conductive boss 400 and the second through groove 202.

[0059] After the first lamination, the surface of the insulating layer 500 may be flush with the surface of the frame 200 .

[0060] Furthermore, an insulating layer 500 is placed on the surface of the frame 200 , and a second high temperature and high pressure treatment is performed, so that the insulating layer 500 covers the surface of the frame 300 .

[0061] Step S50 : a conductive blind hole 501 is provided on the top of the insulating layer 500 corresponding to the conductive boss 400 , the conductive blind hole 501 exposes the conductive boss 400 , and a fan-out terminal 401 electrically connected to the conductive boss 400 is further provided in the conductive blind hole 501 .

[0062] Combination Figure 7 Step S50 is described below. The conductive blind via 501 may be a laser hole. The fan-out terminal 401 further extends outside the insulating layer 500 .

[0063] In combination with the foregoing, the bottom of the conductive boss 400 is electrically connected to the connecting terminal 303 through the wire 102 of the conductive substrate 100, and the top of the conductive boss 400 is electrically connected to the fan-out terminal 401, so that the connecting terminal 303 can be fanned out of the insulating layer 500 through the conductive boss 400 and the fan-out terminal 401.

[0064] Depend on Figure 7 As shown. The thickness of the conductive blind hole 501 is only the distance from the insulating layer 500 to the top of the conductive boss 400, which is less than the thickness of the dielectric layer 600. Therefore, it can be avoided that when the conductive boss 400 is not provided, the dielectric layer 600 needs to be pierced to set the fan-out terminal 401. Because the entire dielectric layer 600 (including the thickness of the frame 200 and the thickness of the insulating layer 500 provided above the frame 200) is pierced, it is possible that laser drilling cannot be performed due to the large thickness of the dielectric layer 600, so mechanical drilling is required, and mechanical drilling brings about problems of large vibration and low precision. In other words, the solution of providing the conductive boss 400 in this embodiment can use laser drilling, simplify the process and improve the precision.

[0065] In yet another embodiment, the conductive boss 400 may be fixed to the conductive substrate 100 by means of a conductive adhesive.

[0066] In another embodiment, the height of the conductive boss 400 may be the same as the height of the bare core 300. In this way, the top surface of the conductive boss 400 is flush with the top surface of the bare core 300. Therefore, when the insulating layer 500 is pressed, the bare core 300 and the conductive boss 400 are subjected to equal forces, so that the bare core 300 and the conductive boss 400 can be effectively pressed and fixed.

[0067] The present application also provides an embedded chip, which can be formed using the manufacturing method described above.

[0068] First see Figure 7 The embedded chip 10 of the present embodiment includes a conductive substrate 100 , a conductive boss 400 , a bare core 300 , an insulating layer 500 and a fan-out terminal 401 .

[0069] The thickness of the conductive substrate 100 may be greater than or equal to 0.5 mm. The conductive substrate 100 has a conductor, which may include an insulating substrate 101 and a conductor 102 disposed on the surface thereof. The conductor 102 includes two conductors insulated from each other. The number of the conductors 102 is equal to the number of the connection terminals of the bare core 300, and each conductor 102 may be electrically connected to the connection terminal of the corresponding bare core 300.

[0070] The wire 102 can be made of metal materials such as copper, aluminum or alloy.

[0071] Due to the presence of metal wires on the conductive substrate 100 , when the conductive substrate 100 is used as a carrier to package a chip, usually holes are not punched on one side of the conductive substrate 100 , but the other side is selected for the punching operation.

[0072] The bare core 300 is disposed on the conductive substrate 100. The bare core 300 includes a top surface 301 and a bottom surface 302 that are disposed opposite to each other.

[0073] The bottom surface 302 is provided with a connection terminal 303. Here, the connection terminal 303 can be electrically connected to an external circuit through a conductive medium. For example, it can be an I / O (input / output) terminal, including an input terminal and an output terminal, usually in the form of a pad or a copper column.

[0074] The present embodiment includes two connection terminals 303. In other embodiments, the connection terminals 303 may be provided in other quantities.

[0075] The connection terminal 303 is electrically connected to the conductive substrate 100. The two connection terminals 303 can be electrically connected to the two wires 102 of the conductive substrate 100 respectively. Specifically, a connection layer 304 is provided at the position of the wire 102 corresponding to the connection terminal 303, and the connection terminal 303 is electrically connected to the wire 102 of the conductive substrate 100 through the connection layer 304. Each wire 102 corresponds to a connection layer 304, and each connection layer 304 corresponds to a connection terminal 303. That is, the number of the connection terminals 303 is equal to the number of the connection layers 304 and the wire 102, and they correspond one to one.

[0076] The connection layer 304 may be made of metal paste.

[0077] The conductive boss 400 is disposed on the conductive substrate 100 and spaced apart from the bare core 300. The conductive boss 400 is electrically connected to the wire 102 of the conductive substrate 100, and is electrically connected to the connection terminal 303 through the wire 102. The number of the conductive bosses 400 is the same as the number of the connection terminals 303, and they correspond one to one.

[0078] Based on this, each connection terminal 303 corresponds to a connection layer 304 , a wire 102 and a conductive boss 400 .

[0079] The conductive boss 400 may be made of metal material, such as copper, aluminum, nickel or other metal monomers or alloys thereof.

[0080] The dielectric layer 600 is disposed on the conductive boss 400 and the bare core 300. It should be understood that the dielectric layer 600 is formed after the conductive boss 400 and the bare core 300 in the manufacturing process, and is at least partially disposed on the conductive boss 400 and the bare core 300. Figure 7 As shown, it is more specifically arranged around the conductive boss 400 and the bare core 300, and the conductive boss 400 and the bare core 300 are buried in the package.

[0081] Furthermore, a conductive blind hole 501 is opened at a position of the dielectric layer 600 corresponding to the top of the conductive boss 400 , and the conductive blind hole 501 exposes the top of the conductive boss 400 .

[0082] The thickness of the conductive blind hole 501 is equal to the thickness of the dielectric layer 600 on the top of the conductive boss 400 , and based on this, it can be formed by laser drilling.

[0083] The fan-out terminal 401 is disposed in the conductive blind hole 501 and electrically connected to the conductive boss 400, and further extends outside the dielectric layer 600. In combination with the above description that the conductive boss 400 is electrically connected to the connection terminal 303 through the wire 102, it can be known that the connection terminal 303 can be fanned out through the conductive boss 400 and the fan-out terminal 401.

[0084] See also Figure 8 , Figure 8 FIG. 1 is a schematic diagram of the structure of another embedded chip provided in an embodiment of the present application. Figure 8 As shown, the embedded chip of this embodiment is different from the above Figure 7 The embedded chip shown differs in that: Figure 8 The conductive substrate 100 of the embedded chip shown is a multi-layer composite structure, specifically comprising a first conductive layer 103, an insulating layer 104 and a second conductive layer 105 stacked in sequence.

[0085] The first conductive layer 103 and the second conductive layer 105 can both be made of metal.

[0086] The conductive line 102 mentioned above may be formed by patterning at least a portion of the metal of the first conductive layer 103 .

[0087] The insulating layer 104 may be made of aluminum oxide ceramic material. In other words, the conductive substrate 100 may be a ceramic substrate.

[0088] The bare core 300 and the conductive boss 400 are disposed on the first conductive layer 103 and are electrically connected to the conductive wire 102 of the first conductive layer 103. The details are as described above and will not be repeated here.

[0089] See also Fig. 9 , Fig. 9 FIG. 1 is a schematic diagram of the structure of another embedded chip provided in an embodiment of the present application. Fig. 9 As shown, the embedded chip of this embodiment is different from the above Figure 7 The difference of the embedded chip shown is that the bare core 300 of this embodiment includes only one connection terminal 303. In order to ensure the electrical connectivity between the connection terminal 303 and the conductive boss 400, the conductive substrate 100 of this embodiment adopts a single-layer metal plate structure, which does not need to be provided with a wire 102 as in the previous text, and the entire conductive substrate 100 serves as a conductive route to electrically connect the connection terminal 303 and the conductive boss 400.

[0090] Therefore, in this embodiment, by providing a conductive boss 400 and a bare core 300 on a conductive substrate 100, a conductive blind hole 501 is provided on the top of the insulating layer 500 corresponding to the conductive boss 400, and a fan-out terminal 401 electrically connected to the conductive boss 400 is provided in the conductive blind hole 501, and the connection terminal 303 on the bottom surface of the bare core 300 can be electrically connected to the conductive boss 400 through the conductive substrate 100, and then fanned out to the outside of the insulating layer 500 through the conductive boss 400 and the fan-out terminal 401. Therefore, the thickness of the conductive blind hole 501 that needs to be opened does not need to be too thick, and only the thickness of the insulating layer corresponding to the top of the conductive boss 400 needs to be opened, which simplifies the process, avoids the situation where the laser cannot penetrate due to a thick package, and can also avoid the large vibration and low precision caused by mechanical drilling.

[0091] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for manufacturing an embedded chip, characterized in that: The manufacturing method comprises: A conductive substrate is provided; a frame is arranged on the conductive substrate, wherein the frame is provided with a first through slot and a second through slot spaced apart from each other; A bare core and at least one conductive boss are arranged on the conductive substrate, wherein the bare core comprises a top surface and a bottom surface arranged opposite to each other, a connecting terminal is arranged on the bottom surface, and the connecting terminal is electrically connected to the conductive substrate; the bare core is arranged in the first through groove, and the conductive boss is arranged in the second through groove, so that the bare core and the conductive boss are arranged at intervals; A first insulating layer is provided on the bare core and the conductive boss; wherein the first insulating layer further covers the surface of the frame, fills the gap between the bare core and the first through groove and the gap between the conductive boss and the second through groove, and the first insulating layer is cured so that the first insulating layer and the frame form an integral structure; the material of the frame is the same as that of the first insulating layer; wherein the thickness of the frame is greater than or equal to the thickness of the bare core and the thickness of the conductive boss; A conductive blind hole is set on the first insulating layer corresponding to the top of the conductive boss, and the conductive blind hole exposes the conductive boss. A fan-out terminal electrically connected to the conductive boss is further set in the conductive blind hole, and the bottom of the conductive boss is electrically connected to the connecting terminal through the conductive substrate, so that the connecting terminal fans out through the conductive boss and the fan-out terminal.

2. The manufacturing method according to claim 1, characterized in that: The conductive boss and the connecting terminal are both one, the conductive substrate is a single-layer metal plate, and the thickness of the metal plate is greater than 0.2 mm.

3. The manufacturing method according to claim 1, characterized in that: The conductive bosses and the connecting terminals each include at least two, and the number of the conductive bosses is the same as the number of the connecting terminals and corresponds one to one.

4. The manufacturing method according to claim 3, characterized in that: Providing a conductive substrate comprises: The conductive substrate is provided with a conductive wire for connecting the conductive boss and the connecting terminal.

5. The manufacturing method according to claim 4, characterized in that: The conductive substrate comprises a first conductive layer, a second insulating layer and a second conductive layer stacked in sequence; The step of providing a bare core and at least one conductive boss on the conductive substrate comprises: The conductive boss and the bare core are arranged on the first conductive layer, wherein the first conductive layer is provided with the conductive wire.

6. The manufacturing method according to claim 1, characterized in that: The step of arranging the bare core in the first through groove further comprises: A connection layer is disposed at a position of the conductive substrate corresponding to the first through groove, and the connection terminal is electrically connected to the conductive substrate through the connection layer.

7. The manufacturing method according to claim 6, characterized in that: The number of the connection layers is the same as the number of the connection terminals, and they correspond one to one.

8. The manufacturing method according to claim 1, characterized in that: The thickness of the frame is greater than or equal to the thickness of the bare core and the thickness of the conductive boss; The width of the first through-slot is greater than the width of the bare core, and the width of the second through-slot is greater than the width of the conductive boss.

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