Semiconductor device structure, Schottky diode and preparation method thereof

Abstract

The present invention provides a semiconductor device structure, a Schottky diode and a preparation method thereof. The preparation method of the Schottky diode comprises: providing a growth substrate with a groove structure, growing a first N-type gallium nitride layer and a second N-type gallium nitride layer, peeling off the growth substrate, and forming a cathode metal layer and an anode metal layer. The present invention forms a first N-type gallium nitride layer by lateral epitaxial growth on the growth substrate, which can improve the quality of gallium nitride crystals, improve surface flatness, reduce crystal defects, and make a vertical Schottky diode, which is conducive to bearing larger currents and voltages. In addition, setting the positive and negative electrodes parallel and staggered up and down is conducive to avoiding the direct impact of the two electrodes to penetrate the chip, improving the withstand voltage characteristics of the gallium nitride Schottky diode and reducing its leakage current.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology, and in particular relates to a semiconductor device structure, a Schottky diode and a preparation method thereof. Background Art

[0002] With the widespread use of high-power devices in various fields such as military and civilian applications, people's demand for Schottky diodes is increasing, and their performance requirements are getting higher and higher. For a long time, people have been using silicon-based Schottky diode devices, but with the development of silicon technology over the years, the performance of the corresponding silicon-based Schottky diodes has approached its theoretical limit. As the third-generation wide bandgap semiconductor material, gallium nitride has the characteristics of large bandgap width, large breakdown electric field, and high electron drift velocity. The Schottky diodes made of it also have excellent characteristics of high temperature resistance, high voltage resistance, and low on-resistance. It is an ideal material for making a new generation of Schottky diodes.

[0003] At present, in addition to the problems of GaN materials themselves, the reverse breakdown voltage and leakage current of GaN Schottky diodes are still far from the theoretical ideal values. Many international research groups are looking for different methods to solve and improve this problem from the structural or process perspectives, in order to improve the voltage resistance characteristics of GaN Schottky diodes and reduce their leakage current, so that the devices can operate at higher power.

[0004] Therefore, it is necessary to provide a semiconductor device structure, a Schottky diode and a manufacturing method thereof to solve the above-mentioned problems in the prior art. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a semiconductor device structure, a Schottky diode and a preparation method thereof, which are used to solve the problems in the prior art such as poor growth quality of gallium nitride crystals and difficulty in effectively improving the withstand voltage characteristics and leakage current of gallium nitride Schottky diodes.

[0006] To achieve the above object and other related objects, the present invention provides a method for preparing a Schottky diode, the method comprising the following steps:

[0007] Providing a growth substrate, wherein a plurality of groove structures are formed in the growth substrate;

[0008] forming a first N-type gallium nitride layer on the growth substrate, wherein the first N-type gallium nitride layer fills the groove structure and extends onto the growth substrate around the groove structure;

[0009] forming a second N-type gallium nitride layer on the first N-type gallium nitride layer, wherein the doping concentration of the second N-type gallium nitride layer is lower than the doping concentration of the first N-type gallium nitride layer;

[0010] Peeling off the growth substrate to form a connection surface on a side of the first N-type gallium nitride layer close to the growth substrate;

[0011] A cathode metal layer electrically connected to the first N-type gallium nitride layer is formed on the connection surface, and an anode metal layer electrically connected to the second N-type gallium nitride layer is formed on the second N-type gallium nitride layer.

[0012] Optionally, before peeling off the growth base, the step also includes: providing a temporary supporting substrate, transferring the structure formed with the second N-type gallium nitride layer to the temporary supporting substrate, the side of the second N-type gallium nitride layer away from the first N-type gallium nitride layer is in contact with the temporary supporting substrate, and the temporary supporting substrate is removed before forming the anode metal layer.

[0013] Optionally, the preparation method further comprises the step of forming a metal substrate between the connection surface and the cathode metal layer and electrically connected to both of them.

[0014] Optionally, the groove structures are arranged in parallel with equal intervals or arranged with periodic intervals.

[0015] Optionally, the distance between the groove structures is less than 10 μm, and the bottom width of the groove structure is between 0.1 μm and 3 μm.

[0016] Optionally, the growth base includes a semiconductor substrate and a sacrificial dielectric layer from bottom to top, wherein a plurality of openings exposing the semiconductor substrate are formed in the sacrificial dielectric layer, and the openings constitute the groove structure.

[0017] Optionally, a growth auxiliary layer is formed on the inner wall of the opening and the sacrificial dielectric layer around it, and the opposite surfaces of the growth auxiliary layer located in the opening constitute the groove structure.

[0018] Optionally, a buffer layer is further formed between the semiconductor substrate and the sacrificial dielectric layer, and the opening penetrates the buffer layer to expose the semiconductor substrate.

[0019] Optionally, after stripping the growth substrate and before forming the cathode metal layer, the method further includes the steps of: forming a dielectric layer on the connection surface, forming a connection portion opening in the dielectric layer to expose the connection surface, and forming a bonding metal layer at least in the connection portion opening, and the cathode metal layer is electrically connected to the first N-type gallium nitride layer through the bonding metal layer.

[0020] Optionally, the bonding metal layer located in the opening of the connecting portion is vertically parallel to the anode metal layer and is staggered accordingly.

[0021] The present invention further provides a semiconductor device structure, wherein the semiconductor device structure can be prepared by referring to the preparation method provided by the present invention, and of course, can also be prepared by other methods, and the semiconductor device structure includes:

[0022] A growth substrate, wherein a plurality of groove structures are formed in the growth substrate;

[0023] A first N-type gallium nitride layer is filled in the groove structure and extends onto the growth substrate around the groove structure; and

[0024] The second N-type gallium nitride layer is formed on the first N-type gallium nitride layer, and the doping concentration of the second N-type gallium nitride layer is lower than the doping concentration of the first N-type gallium nitride layer.

[0025] Optionally, the growth base includes a semiconductor substrate and a sacrificial dielectric layer from bottom to top, wherein a plurality of openings exposing the semiconductor substrate are formed in the sacrificial dielectric layer, and the openings constitute the groove structure.

[0026] Optionally, the sacrificial dielectric layer includes at least one of a SiO2 layer and a Si3N4 layer.

[0027] Optionally, a growth auxiliary layer is formed on the inner wall of the opening and the dielectric layer around it, and the opposite surfaces of the growth auxiliary layer located in the opening constitute the groove structure.

[0028] Optionally, a buffer layer is further formed between the semiconductor substrate and the sacrificial dielectric layer, and the opening penetrates the buffer layer to expose the semiconductor substrate.

[0029] Optionally, the buffer layer includes Al x Ga 1-x At least one of an N layer, a BN layer, and an AlN layer, wherein 0≤x≤0.5.

[0030] Optionally, the growth auxiliary layer includes an AlN layer.

[0031] Optionally, the groove structures are arranged in parallel with equal intervals or arranged with periodic intervals.

[0032] Optionally, the distance between the groove structures is less than 10 μm.

[0033] Optionally, the bottom width of the groove structure is between 0.1 μm and 3 μm.

[0034] The present invention further provides a Schottky diode, which can be prepared by referring to the preparation method provided by the present invention, or by other methods. The Schottky diode comprises:

[0035] A first N-type gallium nitride layer having a lower surface and an upper surface opposite to each other;

[0036] a second N-type gallium nitride layer, formed on an upper surface of the first N-type gallium nitride layer, wherein a doping concentration of the second N-type gallium nitride layer is lower than a doping concentration of the first N-type gallium nitride layer;

[0037] an anode metal layer, formed on the second N-type gallium nitride layer and electrically connected to the second N-type gallium nitride layer;

[0038] a dielectric layer and a bonding metal layer, wherein the dielectric layer is formed on the lower surface of the first N-type gallium nitride layer and is formed with a connection portion opening exposing the lower surface, and the bonding metal layer is at least formed in the connection portion opening;

[0039] A cathode metal layer is formed on a side of the bonding metal layer away from the first N-type gallium nitride layer and is electrically connected to the first N-type gallium nitride layer through the bonding metal layer.

[0040] Optionally, a metal substrate electrically connected to the bonding metal layer and the cathode metal layer is formed between the bonding metal layer and the cathode metal layer.

[0041] Optionally, the bonding metal layer located in the opening of the connecting portion is vertically parallel to the anode metal layer and is staggered accordingly.

[0042] As described above, the present invention forms a first N-type gallium nitride layer by lateral epitaxial growth on a growth substrate, which can improve the quality of gallium nitride crystals, improve surface flatness, reduce crystal defects, and produce a vertically structured Schottky diode, which is conducive to bearing larger currents and voltages. In addition, arranging the positive and negative electrodes to be parallel and staggered up and down is conducive to avoiding direct impact of the two electrodes to penetrate the chip, thereby improving the withstand voltage characteristics of the gallium nitride Schottky diode and reducing its leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 Shown is a flow chart for preparing a Schottky diode provided in Example 1 of the present invention.

[0044] Figure 2(a)-3 and Figure 5-12 The schematic diagram shows the structure obtained in each step of the Schottky diode preparation method provided in the first embodiment of the present invention, wherein: Fig.12 It is also a schematic structural diagram of an example of a Schottky diode in the third embodiment.

[0045] Figure 4 Display as Figure 3 Scanning electron microscopy image of the structure.

[0046] Component number description

[0047] 101 Growth substrate

[0048] 1011 Semiconductor Substrate

[0049] 1012 Buffer layer

[0050] 1013 Sacrificial dielectric layer

[0051] 1014 Growth Auxiliary Layer

[0052] 102 First N-type gallium nitride layer

[0053] 102a Connection surface

[0054] 103 Second N-type gallium nitride layer

[0055] 104 Temporary support substrate

[0056] 105 dielectric layer

[0057] 106 Bonding metal layer

[0058] 107 Metal substrate

[0059] 108 cathode metal layer

[0060] 109 Anode metal layer

[0061] 110, 111 Insulating dielectric barrier

[0062] Steps S1 to S5 DETAILED DESCRIPTION

[0063] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0064] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0065] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0066] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0067] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0068] Embodiment 1:

[0069] like Figure 1 As shown, the present invention provides a method for preparing a Schottky diode, and the preparation method comprises the following steps:

[0070] Providing a growth substrate, wherein a plurality of groove structures are formed in the growth substrate;

[0071] forming a first N-type gallium nitride layer on the growth substrate, wherein the first N-type gallium nitride layer fills the groove structure and extends onto the growth substrate around the groove structure;

[0072] forming a second N-type gallium nitride layer on the first N-type gallium nitride layer, wherein the doping concentration of the second N-type gallium nitride layer is lower than the doping concentration of the first N-type gallium nitride layer;

[0073] Peeling off the growth substrate to form a connection surface on a side of the first N-type gallium nitride layer close to the growth substrate;

[0074] A cathode metal layer electrically connected to the first N-type gallium nitride layer is formed on the connection surface, and an anode metal layer electrically connected to the second N-type gallium nitride layer is formed on the second N-type gallium nitride layer.

[0075] The preparation method of the present invention will be described in detail below with reference to the accompanying drawings.

[0076] like Figure 1 As shown in S1 in FIG. 2 (a) to (c), a growth substrate 101 is provided, and a plurality of groove structures 101a are formed in the growth substrate 101. The formation of the groove structures 101a is used for the subsequent growth preparation of the material layer. The growth substrate 101 can be a single material layer structure or a stacked structure composed of laminated materials, which can be selected according to actual needs, such as a silicon substrate, silicon oxide, silicon on insulator, etc.

[0077] As shown in FIG. 2( a ), an example of the growth substrate 101 is given. In this example, the growth substrate 101 includes a semiconductor substrate 1011 and a sacrificial dielectric layer 1013 from bottom to top, wherein a plurality of openings exposing the semiconductor substrate 1011 are formed in the sacrificial dielectric layer 1013. In one example, the openings are directly used as the groove structure 101a. In another example, a growth auxiliary layer 1014 may be formed on the inner wall of the opening and the sacrificial dielectric layer 1013 around the opening, and the relative surfaces of the growth auxiliary layer 1014 located in the opening constitute the groove structure 101a.

[0078] The semiconductor substrate 1011 can be selected according to actual needs. Preferably, the semiconductor substrate 1011 can be an Al2O3 substrate, a SiC substrate, a Si substrate, a ZnO substrate or a GaN substrate. The sacrificial dielectric layer 1013 can be a single material layer or a stacked structure composed of multiple material layers. The sacrificial dielectric layer 1013 can be formed on the semiconductor substrate 1011 by plasma enhanced chemical vapor deposition (PECVD), PVD or electron beam evaporation. In one example, the sacrificial dielectric layer 1013 includes at least one of a SiO2 layer and a Si3N4 layer, that is, it can be any one of the above material layers, and can be a stacked structure formed by stacking at least two of the above material layers. Further, optionally, the materials of adjacent material layers in the formed stacked structure are different. FIG. 2(a) schematically shows a stacked structure composed of a silicon oxide layer and a silicon nitride layer. In addition, the growth auxiliary layer 1014 can be formed by MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor phase epitaxy) or PVD (physical vapor deposition) process, and its material includes but is not limited to aluminum nitride (AlN), which can act as a buffer layer to provide a basis for the subsequent first N-type gallium nitride layer 102, and its thickness can be set to 10nm-100nm.

[0079] As shown in FIG. 2( a ), as an example, a buffer layer 1012 is formed between the semiconductor substrate 1011 and the sacrificial dielectric layer 1013, and the opening of the sacrificial dielectric layer 1013 penetrates the buffer layer 1012 to expose the semiconductor substrate 1011. Of course, as shown in FIG. 2( b ), the buffer layer 1012 may not be formed. As an example, the buffer layer 1012 may be Al x Ga 1-x N layer, where 0≤x≤0.5; it can also be a BN layer; it can also be an AlN layer, and the crystal orientation of the AlN layer is (0001). The buffer layer 1012 can be formed on the surface of the semiconductor substrate 1011 by MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor phase epitaxy) or PVD (physical vapor deposition) process. In addition, the thickness of the buffer layer 1011 can be set according to actual needs. Preferably, in this embodiment, the thickness of the buffer layer 1011 is 50 angstroms to 600 angstroms.

[0080] As an example, a protective layer (not shown in the figure) is formed on the upper surface of the buffer layer 1012. As an example, the protective layer can be formed on the upper surface of the buffer layer 1012 by evaporation or other processes; the protective layer may include a metal layer and / or a metal oxide layer, that is, the protective layer may be a metal layer, or at least two metal layers of different materials, or a metal oxide layer, or at least two metal oxide layers of different materials, or a laminated structure consisting of at least one metal layer and at least one metal oxide layer. Specifically, the material of the metal layer includes nickel (Ni) or titanium (Ti); the material of the metal oxide layer includes titanium oxide (TiOx) or indium tin oxide (ITO). In one example, the protective layer includes a titanium oxide layer and an indium tin oxide layer. As an example, the thickness of the protective layer can be set according to actual needs. Preferably, in this embodiment, the thickness of the protective layer can be 10 angstroms to 500 angstroms. If the thickness of the protective layer is too small, such as less than 10 angstroms, the protective effect will be very limited. If the thickness of the protective layer is too large, such as greater than 500 angstroms, it is easy to cause undercutting, thereby affecting the performance of the device. In the present invention, the thickness of the protective layer is set to 10 angstroms to 500 angstroms, which can ensure the protective effect of the protective layer and is not easy to be undercut during subsequent wet etching, thereby being able to well control the accuracy of the pattern.

[0081] As shown in FIG. 2(c) and FIG. 2(d), two examples of the arrangement of the groove structures 101a are provided, and the top view thereof is shown in the figure, wherein the groove structures 101a are arranged in parallel and at equal intervals, as shown in FIG. 2(c), or the groove structures 101a are arranged at periodic intervals, as shown in FIG. 2(d), so as to facilitate the subsequent formation of the first N-type gallium nitride layer 102. As an example, the distance between the groove structures 101a is less than 10 μm, such as 2 μm, 3 μm, etc., and the bottom width of the groove structure 101a is between 0.1 μm and 3 μm, such as 0.5 μm, 1 μm, 2 μm, etc. Among them, when each of the groove structures 101a is arranged in parallel with equal intervals, the longitudinal cross-sectional shape of the groove structure 101a can be a square, a rectangle or a trapezoid, etc., which can be formed into the shape of the subsequent first N-type gallium nitride layer 102 through lateral growth, and is arranged in a long strip shape and formed in the growth substrate 101. At this time, the distance between the groove structures 101a refers to the distance d1 between the two opposite sides of adjacent groove structures, and the bottom width of the groove structure 101a refers to the dimension w1 along the direction perpendicular to the extension of the single groove structure; when each of the groove structures 101a is arranged at periodic intervals, such as the hexagonal arrangement in the figure, the groove structure 101a can be a cylindrical structure or a square columnar structure, and the distance between the groove structures 101a refers to the distance d2 between the relative positions of adjacent groove structures in the hexagonal arrangement structure, and the bottom width of the groove structure 101a refers to the dimension w2 along the diameter direction, which is conducive to the subsequent formation of the first N-type gallium nitride layer 102.

[0082] like Figure 1 S2 and Figure 3-5 As shown, a first N-type gallium nitride layer 102 is formed on the growth substrate 101, and the first N-type gallium nitride layer 102 fills the groove structure 101a and extends to the growth substrate 101 around the groove structure 101a. In one example, the first N-type gallium nitride layer 102 is grown in the groove structure 101a using a MOCVD process, as shown in FIG. Figure 3 As shown, it is an example of the structure of the first N-type gallium nitride layer 102 during the growth process. During the formation of the first N-type gallium nitride layer 102, the lateral growth from the groove structure 101a to the surface of the growth substrate 101 can improve the quality of the obtained crystal, improve the surface flatness, and reduce crystal defects. The defects in the crystal will also be concentrated at the epitaxial closing interface due to the lateral growth, which is beneficial to improve the stability of the device. In addition, Figure 4 The first N-type gallium nitride layer 102 is shown in the growth process Figure 3In one example, after XRD testing, the 002 direction and 102 direction of the first N-type gallium nitride layer 102 crystal are both less than 50 arc seconds. Figure 5 As shown, in one example, when the first N-type gallium nitride layer 102 is grown in the groove structure 101a, it continues to grow until the surface is flat, that is, a portion of the first N-type gallium nitride layer 102 finally formed fills the groove structure 101a, and a portion is located on the growth substrate 101. In an optional example, a height d3 of the portion of the first N-type gallium nitride layer 102 located on the growth substrate 101 is between 1-2 microns.

[0083] like Figure 1 S3 and Figure 5 As shown, a second N-type gallium nitride layer 103 is formed on the first N-type gallium nitride layer 102, and the doping concentration of the second N-type gallium nitride layer 103 is lower than the doping concentration of the first N-type gallium nitride layer 102, wherein the first N-type gallium nitride layer 102 can be a heavily doped gallium nitride layer. 18 Atom / cm 3 -5*10 20 Atom / cm 3 The second N-type gallium nitride layer 103 may be a lightly doped gallium nitride layer, 15 Atom / cm 3 -5*10 16 Atom / cm 3 between.

[0084] like Figure 1 S4 and Figure 6-7As shown, the growth substrate 101 is peeled off to form a connection surface 102a on the side of the first N-type gallium nitride layer 102 close to the growth substrate 101, and the connection surface 102a is used to prepare a subsequent material layer. In one example, the side of the first N-type gallium nitride layer 102 close to the growth substrate is also flattened to obtain a flattened surface, which is used as the connection surface 102a and can be flattened by a chemical mechanical polishing process, so that the flattened surface is used as a connection surface for the subsequent preparation of the material layer to electrically lead out the first N-type gallium nitride layer 102. The growth substrate 101 may be stripped by chemical stripping. In one example, the growth substrate 101 includes the semiconductor substrate 1011 and the sacrificial dielectric layer 1013. The sacrificial dielectric layer 1013 includes a silicon oxide layer. Of course, other material layers may also be included. The silicon oxide layer may be corroded by a corrosive liquid to further achieve stripping between the growth substrate 101 and the first N-type gallium nitride layer 102. Of course, when other material layers exist between the semiconductor substrate 1011 and the first N-type gallium nitride layer 102, the other material layers may be corroded by a corrosive liquid to achieve stripping. For example, when the growth auxiliary layer 1014 exists, a step of removing the growth auxiliary layer 1014 by wet etching is also included.

[0085] like Figure 6 As shown, as an example, before peeling off the growth substrate 101, the steps are also included: providing a temporary support substrate 104, transferring the structure formed with the second N-type gallium nitride layer 103 to the temporary support substrate 104, the second N-type gallium nitride layer 103 is in contact with the temporary support substrate 104 on the side away from the first N-type gallium nitride layer 102, and removing the temporary support substrate 104 before the subsequent formation of the anode metal layer 109. Of course, the temporary support substrate 104 can also be used to support the preparation of other material layers. Among them, the temporary support substrate 104 can be selected as a metal substrate and a non-metal substrate, such as copper, molybdenum copper, tungsten copper, sapphire substrate, etc.

[0086] like Figure 1 S5 and Figure 8-12 As shown, a cathode metal layer 108 electrically connected to the first N-type gallium nitride layer 102 is formed on the connection surface 102a, and an anode metal layer 109 electrically connected to the second N-type gallium nitride layer 103 is formed on the second N-type gallium nitride layer 103. Wherein, an ohmic contact is formed between the cathode metal layer 108 and the first N-type gallium nitride layer 102, and a Schottky contact is formed between the anode metal layer 109 and the second N-type gallium nitride layer 103. Through the above scheme, the present invention prepares a vertical Schottky diode that can withstand large currents and large voltages. Wherein, Fig.11 In the example of forming the temporary supporting substrate 104, a step of removing the temporary supporting substrate 104 is shown. In addition, Fig.12 It shows a schematic diagram of a structure for forming the cathode metal layer 108 and the anode metal layer 109. In the illustrated example, it also includes an insulating dielectric barrier layer 111 formed around the cathode metal layer 108, and an insulating dielectric barrier layer 110 formed around the anode metal layer 109. The above-mentioned material layers can be formed by existing processes.

[0087] like Figure 8-9 As shown, as an example, after forming the connection surface 102a and before forming the cathode metal layer 108, the method further includes the steps of: forming a dielectric layer 105 on the connection surface 102a, and forming a connection portion opening 105a exposing the connection surface 102a in the dielectric layer 105, and forming a bonding metal layer 106 at least in the connection portion opening 105a, and the cathode metal layer 108 is electrically connected to the first N-type gallium nitride layer 102 through the bonding metal layer 106. In one example, the bonding metal layer 106 also extends to the surface of the dielectric layer 105, wherein, Figure 8 It is a schematic diagram showing the formation of a dielectric layer 105, Fig. 9 The structure diagram of forming the bonding metal layer 106 is shown. The material of the dielectric layer 105 includes but is not limited to silicon oxide and silicon nitride, and the material of the bonding metal layer 106 includes but is not limited to gold, tin, gold-tin alloy, nickel, tin, nickel-tin alloy, etc. The dielectric layer 105 can be formed by chemical vapor deposition and other processes, and the bonding metal layer 106 can be formed by E-BEAM evaporation. As an example, the bonding metal layer 106 located in the connection portion opening 105a is arranged in parallel with the anode metal layer 109. Further optionally, the corresponding positions of the two do not overlap, that is, the projections of the two in the plane parallel to them do not overlap and are staggered. In one example, the edges close to the two have a spacing s, so as to avoid direct collision of the two voltages and breakdown of the chip, thereby improving the withstand voltage characteristics of the gallium nitride Schottky diode and reducing its leakage current. In addition, the two staggered metal electrode layers are conducive to controlling the direction of the device current and preventing leakage current from forming at the defects of the first N-type gallium nitride layer 102 grown laterally in the present invention. During the lateral growth of the first N-type gallium nitride layer 102, the defects tend to concentrate on the epitaxial closure cross-section to form a defect wall. The bonding metal layer 106 located in the connection portion opening 105a and the anode metal layer 109 are staggered up and down, which is conducive to preventing leakage current from forming at the defect wall. Further optionally, at corresponding upper and lower positions, the cathode metal layer 108 simultaneously covers the anode metal layer 109 and the bonding metal layer 106 located in the connection portion opening 105 a .

[0088] like Fig.10 As shown, as an example, the method for preparing the Schottky diode further includes the step of forming a metal substrate 107 electrically connected to both the connection surface 102a and the cathode metal layer 108 between the connection surface 102a and the cathode metal layer 108. In one example, after forming the bonding metal layer 106, the metal substrate 107 is formed, wherein the metal substrate 107 can be formed by bonding, and the material of the metal substrate 107 can include but is not limited to copper, molybdenum copper, tungsten copper, etc., and the thickness of the metal substrate 107 is greater than 60 microns, preferably 80-120 microns.

[0089] Embodiment 2:

[0090] like Figure 5 As shown, the present invention further provides a semiconductor device structure, wherein the semiconductor device structure can be prepared by referring to the preparation method provided by the present invention, and of course, can also be prepared by other methods, and the semiconductor device structure can be used to prepare a Schottky diode, wherein the features and related descriptions of the semiconductor device structure in this embodiment can refer to the description of the related structure of the first embodiment, and will not be repeated here, the semiconductor device structure includes: a growth substrate 101, a first N-type gallium nitride layer 102 and a second N-type gallium nitride layer 103, wherein:

[0091] A plurality of groove structures 101a are formed in the growth substrate 101; the first N-type gallium nitride layer 102 is filled in the groove structure 101a and extends to the growth substrate 101 around the groove structure 101a; the second N-type gallium nitride layer 103 is formed on the first N-type gallium nitride layer 102, and the doping concentration of the second N-type gallium nitride layer 103 is lower than the doping concentration of the first N-type gallium nitride layer 102.

[0092] As an example, the groove structures 101a are arranged in parallel with equal intervals or arranged with periodic intervals.

[0093] As an example, the distance between the groove structures 101 a is less than 10 μm.

[0094] As an example, the bottom width of the groove structure 101 a is between 0.1 μm and 3 μm.

[0095] As an example, the growth base 101 includes a semiconductor substrate 1011 and a sacrificial dielectric layer 1013 from bottom to top, wherein a plurality of openings exposing the semiconductor substrate are formed in the sacrificial dielectric layer 1013 , and the openings constitute the groove structure 101 a .

[0096] As an example, the sacrificial dielectric layer 1013 includes at least one of a SiO 2 layer and a Si 3 N 4 layer.

[0097] As an example, a growth auxiliary layer 1014 is formed on the inner wall of the opening and the sacrificial dielectric layer 1013 around it, and the opposite surfaces of the growth auxiliary layer 1014 located in the opening constitute the groove structure 101 a .

[0098] As an example, the growth auxiliary layer includes an AlN layer.

[0099] As an example, a buffer layer 1012 is further formed between the semiconductor substrate 1011 and the sacrificial dielectric layer 1013 , and the opening penetrates the buffer layer 1012 to expose the semiconductor substrate 1011 .

[0100] As an example, the buffer layer includes Al x Ga 1-x At least one of an N layer, a BN layer, and an AlN layer, wherein 0≤x≤0.5.

[0101] Embodiment three:

[0102] like Fig.12 See Figure 1-11 The present invention further provides a Schottky diode, which can be prepared by referring to the preparation method provided by the present invention. Of course, it can also be prepared by other methods. The characteristics and related descriptions of the Schottky diode described in this embodiment can refer to the description of the related structure of the first embodiment, which will not be repeated here. The Schottky diode includes: a first N-type gallium nitride layer 102, a second N-type gallium nitride layer 103, an anode metal layer 109, a dielectric layer 105, a bonding metal layer 106 and a cathode metal layer 108, wherein:

[0103] The first N-type gallium nitride layer 102 has a lower surface and an upper surface opposite to each other;

[0104] The second N-type gallium nitride layer 103 is formed on an upper surface of the first N-type gallium nitride layer 102 , and a doping concentration of the second N-type gallium nitride layer 103 is lower than a doping concentration of the first N-type gallium nitride layer 102 ;

[0105] The anode metal layer 109 is formed on the second N-type gallium nitride layer 103 and is electrically connected to the second N-type gallium nitride layer 103;

[0106] The dielectric layer 105 is formed on the lower surface of the first N-type gallium nitride layer 102 and is formed with a connection opening 105a exposing the lower surface, and the bonding metal layer 106 is at least formed in the connection opening 105a;

[0107] The cathode metal layer 108 is formed on a side of the bonding metal layer 106 away from the first N-type gallium nitride layer 102 and is electrically connected to the first N-type gallium nitride layer 102 through the bonding metal layer 106 .

[0108] As an example, the bonding metal layer 106 and the anode metal layer 109 located in the connection portion opening 105 a are vertically parallel and correspondingly staggered.

[0109] As an example, a metal substrate 107 is formed between the bonding metal layer 106 and the cathode metal layer 108 and is electrically connected to both of them.

[0110] In summary, the present invention provides a semiconductor device structure, a Schottky diode and a method for preparing the same. In the scheme of the present invention, a first N-type gallium nitride layer is formed by lateral epitaxial growth on a growth substrate, which can improve the quality of gallium nitride crystals, improve surface flatness, reduce crystal defects, and make a vertically structured Schottky diode, which is conducive to bearing larger currents and voltages. In addition, the positive and negative electrodes are arranged to be staggered in parallel up and down, which is conducive to avoiding direct impact of the two electrodes on the chip, improving the withstand voltage characteristics of the gallium nitride Schottky diode and reducing its leakage current. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0111] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a Schottky diode, characterized in that: The preparation method comprises the following steps: Providing a growth substrate, wherein a plurality of groove structures are formed in the growth substrate, and the groove structures are arranged in parallel with equal intervals or arranged in periodic intervals; forming a first N-type gallium nitride layer on the growth substrate, wherein the first N-type gallium nitride layer fills the groove structure and extends onto the growth substrate around the groove structure; forming a second N-type gallium nitride layer on the first N-type gallium nitride layer, wherein the doping concentration of the second N-type gallium nitride layer is lower than the doping concentration of the first N-type gallium nitride layer; Peeling off the growth substrate to form a connection surface on a side of the first N-type gallium nitride layer close to the growth substrate; A dielectric layer is formed on the connection surface, wherein a connection portion opening for exposing the connection surface is formed in the dielectric layer, and a bonding metal layer is formed at least in the connection portion opening; forming a cathode metal layer electrically connected to the first N-type gallium nitride layer on the bonding metal layer, and forming an anode metal layer electrically connected to the second N-type gallium nitride layer on the second N-type gallium nitride layer; The bonding metal layer located in the opening of the connecting portion is vertically parallel to the anode metal layer and staggered correspondingly.

2. The method for preparing a Schottky diode according to claim 1, characterized in that: Before peeling off the growth substrate, the method also includes the steps of: providing a temporary supporting substrate, transferring the structure formed with the second N-type gallium nitride layer to the temporary supporting substrate, wherein a side of the second N-type gallium nitride layer away from the first N-type gallium nitride layer is in contact with the temporary supporting substrate, and removing the temporary supporting substrate before forming the anode metal layer.

3. The method for preparing a Schottky diode according to claim 1, characterized in that: The preparation method further comprises the step of: forming a metal substrate between the connection surface and the cathode metal layer and electrically connected to both of them.

4. The method for preparing a Schottky diode according to claim 1, characterized in that: The distance between the groove structures is less than 10 μm, and the bottom width of the groove structure is between 0.1 μm and 3 μm.

5. The method for preparing a Schottky diode according to claim 1, characterized in that: The growth base includes a semiconductor substrate and a sacrificial dielectric layer from bottom to top, wherein a plurality of openings exposing the semiconductor substrate are formed in the sacrificial dielectric layer, and the openings constitute the groove structure.

6. The method for preparing a Schottky diode according to claim 5, characterized in that: A growth auxiliary layer is formed on the inner wall of the opening and the sacrificial dielectric layer around it, and the relative surfaces of the growth auxiliary layer in the opening constitute the groove structure, and / or a buffer layer is also formed between the semiconductor substrate and the sacrificial dielectric layer, and the opening penetrates the buffer layer to expose the semiconductor substrate.

7. The method for preparing a Schottky diode according to any one of claims 1 to 6, characterized in that: The cathode metal layer is electrically connected to the first N-type gallium nitride layer through the bonding metal layer.

8. A semiconductor device structure, characterized in that: The semiconductor device structure is a structure manufactured by the manufacturing method according to any one of claims 1 to 7, and the semiconductor device structure comprises: A first N-type gallium nitride layer having a lower surface and an upper surface opposite to each other; A second N-type gallium nitride layer is formed on the first N-type gallium nitride layer, and the doping concentration of the second N-type gallium nitride layer is lower than the doping concentration of the first N-type gallium nitride layer; an anode metal layer, formed on the second N-type gallium nitride layer and electrically connected to the second N-type gallium nitride layer; a dielectric layer and a bonding metal layer, wherein the dielectric layer is formed on the lower surface of the first N-type gallium nitride layer and is formed with a connection portion opening exposing the lower surface, and the bonding metal layer is at least formed in the connection portion opening; The bonding metal layer located in the opening of the connecting portion is vertically parallel to the anode metal layer and staggered correspondingly.

9. A Schottky diode, characterized in that: The Schottky diode is a structure manufactured by the manufacturing method according to any one of claims 1 to 7, and the Schottky diode comprises: A first N-type gallium nitride layer having a lower surface and an upper surface opposite to each other; a second N-type gallium nitride layer, formed on an upper surface of the first N-type gallium nitride layer, wherein a doping concentration of the second N-type gallium nitride layer is lower than a doping concentration of the first N-type gallium nitride layer; an anode metal layer, formed on the second N-type gallium nitride layer and electrically connected to the second N-type gallium nitride layer; a dielectric layer and a bonding metal layer, wherein the dielectric layer is formed on the lower surface of the first N-type gallium nitride layer and is formed with a connection portion opening exposing the lower surface, and the bonding metal layer is at least formed in the connection portion opening; a cathode metal layer, formed on a side of the bonding metal layer away from the first N-type gallium nitride layer and electrically connected to the first N-type gallium nitride layer through the bonding metal layer; The bonding metal layer located in the opening of the connecting portion is vertically parallel to the anode metal layer and staggered correspondingly.

10. The Schottky diode according to claim 9, characterized in that: A metal substrate electrically connected to the bonding metal layer and the cathode metal layer is formed between the bonding metal layer and the cathode metal layer.

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