A deep trench MOS device for improving EMI and a manufacturing method thereof

Abstract

The present invention discloses a deep trench MOS device for improving EMI and a manufacturing method thereof. The device comprises a substrate, several layers of intermediate epitaxial layers and a surface epitaxial layer, wherein a trench is formed in the intermediate epitaxial layer and the surface epitaxial layer, wherein the bottom of the trench is arranged in the bottom intermediate epitaxial layer, wherein the trench is filled with impurities of the second conductive type, and a plurality of pillars of the first conductive type are formed on the upper side of each intermediate epitaxial layer on both sides of the trench, wherein the ends of the pillars of the first conductive type extend deep into the interior of the trench. The present invention arranges a plurality of pillars of the first conductive type on both sides of the trench, thereby changing the shape of the pillars of the second conductive type in the trench, so that during the switching process, the charging and discharging of the Coss will slow down, the switching oscillation will be reduced, the switching noise will be reduced, and the EMI performance will be improved; and since the overall EPI thickness and the mask layer are not increased, the cost will not increase.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a deep trench MOS device for improving EMI and a manufacturing method thereof. Background Art

[0002] The cross-section of a common DeepTrench super-junction MOS power tube has a vertically smooth P-pillar shape due to the characteristics of its process method. In power adapter applications with high EMI requirements, the smooth P-pillar shape will lead to fast Coss charging and discharging, large oscillation, high noise, and poor EMI performance during the MOS switching process. Therefore, it is necessary to make improvements. Summary of the invention

[0003] The object of the present invention is to provide a deep trench MOS device for improving EMI and a manufacturing method thereof in view of the deficiencies in the prior art.

[0004] To achieve the above object, in a first aspect, the present invention provides a method for manufacturing a deep trench MOS device for improving EMI, comprising the following steps:

[0005] Step 1, providing a substrate of a first conductivity type, forming a plurality of intermediate epitaxial layers on the substrate, implanting a heavily doped layer of the first conductivity type on the upper side of each intermediate epitaxial layer, and forming a surface epitaxial layer on the upper side of the uppermost intermediate epitaxial layer;

[0006] Step 2, growing a masking layer on the surface epitaxial layer, making a JEFT injection opening on the masking layer in the active area, and performing a JEFT injection operation on the surface epitaxial layer through the JEFT injection opening to form a JEFT injection area on the surface epitaxial layer;

[0007] Step 3, forming a trench opening on the masking layer, and forming a trench on the surface epitaxial layer and the intermediate epitaxial layer through the trench opening, wherein the bottom of the trench is arranged in the bottom intermediate epitaxial layer, and impurities of the second conductivity type are filled into the trench;

[0008] Step 4, performing an annealing operation to anneal the heavily doped layer to form a pillar of the first conductivity type with an end portion extending deep into the trench;

[0009] Step 5, growing an oxide layer on the surface epitaxial layer, the JEFT implantation area and the upper side of the trench, and removing the oxide layer in the active area, leaving only the oxide layer in the terminal area;

[0010] Step 6, growing a gate oxide layer on the upper side of the oxide layer and the surface epitaxial layer in the active area, depositing polycrystalline on the upper side of the gate oxide layer in the active area, and performing polycrystalline doping, and etching away the polycrystalline and gate oxide layer on the upper side of the trench and between the active area and the terminal area;

[0011] Step 7, performing impurity implantation and well-driving operations on the surface epitaxial layer and the polycrystal on both sides of the polycrystal in the active area to form a heavily doped region of the first conductivity type, and at the same time heavily doping the polycrystal;

[0012] Step 8, depositing a dielectric layer on the upper side of the surface epitaxial layer, the trench, the heavily doped region of the first conductivity type and the polycrystalline, and etching the dielectric layer to form a connecting hole;

[0013] Step 9, sputtering to form a metal layer on the upper side of the dielectric layer and in the connection hole, and etching the metal layer to form a gate region and a source region.

[0014] Furthermore, the implanted element of the heavily doped layer of the first conductivity type is phosphorus, the implanted energy is 60-80 KeV, and the implanted dose is 1E12-3E12.

[0015] Furthermore, the intermediate epitaxial layer includes 6 to 8 layers.

[0016] Furthermore, before the annealing operation in step 4, a junction region of the second conductivity type is implanted in the surface epitaxial layer around the trench, and the outer side of the upper end of the trench is connected to the junction region of the second conductivity type.

[0017] Furthermore, the resistivity of each intermediate epitaxial layer is 1-3Ω.cm, and the thickness thereof is 5-7um.

[0018] In a second aspect, the present invention further provides a deep trench MOS device for improving EMI, comprising a substrate of a first conductive type, wherein a plurality of intermediate epitaxial layers and a surface epitaxial layer are sequentially arranged on the upper side of the substrate, trenches are formed in the intermediate epitaxial layers and the surface epitaxial layers, the bottom of the trench is arranged in the bottom intermediate epitaxial layer, the trench is filled with impurities of a second conductive type, a plurality of pillars of the first conductive type are formed on the upper side of each intermediate epitaxial layer on both sides of the trench, the ends of the pillars of the first conductive type extend deep into the interior of the trench, JEFT injection regions are arranged on the surface epitaxial layers on both sides of the trench, and a surface outer surface of the terminal region is provided with a JEFT injection region. An oxide layer is grown on the upper side of the epitaxial layer, a gate oxide layer is grown on the upper side of the oxide layer and the surface epitaxial layer in the active area, polycrystals are deposited on the upper side of the gate oxide layer in the active area, and the gate oxide layer and polycrystals in the terminal area, the upper side of the groove, and between the active area and the terminal area are etched away, a heavily doped region of the first conductivity type is formed in the surface epitaxial layer on both sides of the polycrystal, and the polycrystals are heavily doped at the same time, a dielectric layer is deposited on the upper side of the surface epitaxial layer, the groove, the heavily doped region of the first conductivity type and the polycrystal, a connection hole is etched on the dielectric layer, a metal layer is sputtered on the upper side of the dielectric layer and in the connection hole, and the metal layer is etched to form a gate area and a source area.

[0019] Furthermore, the intermediate epitaxial layer includes 6 to 8 layers.

[0020] Furthermore, before the annealing operation, a junction region of the second conductivity type is implanted in the surface epitaxial layer around the trench, and the outer side of the upper end of the trench is connected to the junction region of the second conductivity type.

[0021] Furthermore, the resistivity of each intermediate epitaxial layer is 1-3Ω.cm, and the thickness thereof is 5-7um.

[0022] Furthermore, a passivation layer is deposited on the upper side of the metal layer and the dielectric layer, and an opening area of ​​a gate and a source is formed by etching on the passivation layer; Ti, Ni and Ag layers are evaporated in sequence on the lower side of the substrate.

[0023] Beneficial effect: The present invention arranges a plurality of pillars of the first conductive type on both sides of the groove, and the ends of the pillars of the first conductive type penetrate into the pillars of the second conductive type in the groove, thereby changing the shape of the pillars of the second conductive type in the groove, so that during the switching process, the charging and discharging of the Coss will be slowed down, the switching oscillation will be reduced, the switching noise will be reduced, and the EMI performance will be improved; and since the overall EPI thickness and the mask layer are not increased, the cost will not increase. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1It is a schematic structural diagram of a substrate, an intermediate epitaxial layer and a surface epitaxial layer according to an embodiment of the present invention;

[0025] Figure 2 is a schematic diagram of the structure after performing a JEFT operation on the surface epitaxial layer;

[0026] Figure 3 is a schematic diagram of the structure after the trench is etched and backfilled;

[0027] Figure 4 is a schematic diagram of the structure after the annealing operation is performed;

[0028] Figure 5 It is a schematic diagram of the structure after the oxide layer is provided in the terminal area;

[0029] Figure 6 It is a schematic diagram of the structure after the gate oxide layer is long and polycrystalline is deposited;

[0030] Figure 7 It is a schematic diagram of the structure after the dielectric layer is deposited and carved to form a connection;

[0031] Figure 8 It is a schematic diagram of the structure after sputtering metal. DETAILED DESCRIPTION

[0032] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments. The embodiments are implemented based on the technical solution of the present invention. It should be understood that these embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention.

[0033] like Figures 1 to 8 As shown, an embodiment of the present invention provides a method for manufacturing a deep trench MOS device for improving EMI, comprising the following steps:

[0034] Step 1, provide a substrate 1 of the first conductivity type, make several layers of intermediate epitaxial layers 2 on the substrate 1, and form a heavily doped layer 3 of the first conductivity type by injection on the upper side of each intermediate epitaxial layer 2, and make a surface epitaxial layer 4 on the upper side of the uppermost intermediate epitaxial layer 2. Among them, the substrate 1 is heavily doped with the first conductivity type, and the resistivity of the substrate 1 is generally 0.001-0.005Ω.cm. Different device withstand voltages can be obtained by selecting different epitaxial resistivities and thicknesses. Both the intermediate epitaxial layer 2 and the surface epitaxial layer 4 are lightly doped with the first conductivity type. When making the intermediate epitaxial layer 2, first grow a layer of epitaxial with a thickness of 5-7um on the upper side of the substrate 1, and perform a general injection of impurities of the first conductivity type. The injection element of the heavily doped layer 3 of the first conductivity type is preferably phosphorus, the injection energy is 60-80KeV, and the injection dose is 1E12-3E12. Then repeat the epitaxial growth and impurity injection operations, generally repeat 5 to 7 times, and 6 to 8 layers of heavily doped layers 3 of the first conductivity type can be produced. The resistivity of the surface epitaxial layer 4 is 1-3Ω.cm, and the thickness is preferably 5um. The total thickness of the intermediate epitaxial layer 2 and the surface epitaxial layer 4 is preferably 45-60um, and the device withstand voltage can reach 500V-800V.

[0035] Step 2, grow a masking layer 5 on the surface epitaxial layer 4, make a JEFT injection opening 6 on the masking layer 5 in the active area, and perform a JEFT injection operation on the surface epitaxial layer 4 through the JEFT injection opening 6 to form a JEFT injection area 7 on the surface epitaxial layer 4. Specifically, the JEFT injection opening 6 is formed by sequentially coating, exposing and etching on the masking layer 5. In order not to affect the subsequent process, after completing the JEFT injection operation, the glue applied in this step needs to be removed. JEFT injection energy: 60Kev-80Kev, injection dose: 1E12-3E12, injection element: phosphorus element.

[0036] Step 3, a trench opening 8 is made on the masking layer 5, and a trench 9 is made on the surface epitaxial layer 4 and the intermediate epitaxial layer 2 through the trench opening 8, the bottom of the trench 9 is set in the bottom intermediate epitaxial layer 2, and the second conductivity type impurities are filled into the trench 9. The trench opening 8 and the trench 9 are also formed by coating, exposing and etching. In order not to affect the subsequent process, after the impurities are filled into the trench 9, the glue applied in this step should be removed.

[0037] Step 4: performing an annealing operation to anneal the heavily doped layer 3 to form a pillar 10 of the first conductivity type with an end portion extending deep into the trench 9. Annealing temperature: 1100° C., annealing time: 30-180 minutes.

[0038] Step 5, grow an oxide layer 11 on the surface epitaxial layer 4, the JEFT implantation area 7 and the upper side of the trench 9, and remove the oxide layer 11 in the active area, leaving only the oxide layer 11 in the terminal area. The thickness of the grown oxide layer 11 is preferably 8000-12000 angstroms.

[0039] Step 6, a gate oxide layer 12 is grown on the upper side of the oxide layer 11 and the surface epitaxial layer 4 in the active area, polycrystalline 13 is deposited on the upper side of the gate oxide layer 12 in the active area, and polycrystalline doping is performed, and the polycrystalline 13 and the gate oxide layer 12 in the terminal area, the upper side of the groove 9, and between the active area and the terminal area are etched away. Wherein, the thickness of the gate oxide layer 12 is preferably 700-1200 angstroms, and the thickness of the polycrystalline 13 is preferably 6000-8000 angstroms. The doping of the polycrystalline 13 in this step is performed by a diffusion furnace.

[0040] Step 7, perform impurity implantation and well-driving operation on the surface epitaxial layer 4 and the polycrystalline 13 on both sides of the polycrystalline 13 in the active area to form a heavily doped region 14 of the first conductivity type, and at the same time heavily dope the polycrystalline 13. The implantation dose of the heavily doped region 14 of the first conductivity type is: 5E15-1E16, the implantation energy is: 60Kev-120Kev, the implantation element is: arsenic, the well-driving temperature is: 950°C, and the well-driving time is: 30 minutes.

[0041] Step 8, deposit a dielectric layer 15 on the upper side of the surface epitaxial layer 4, the trench 9, the heavily doped region 14 of the first conductivity type and the polycrystalline 13, and etch the dielectric layer 15 to form a connection hole 16. The dielectric layer 15 is preferably BPSG (boron phospho-silicate glass), and the thickness of the dielectric layer 15 is preferably 10000 angstroms.

[0042] Step 9: sputtering to form a metal layer 17 on the upper side of the dielectric layer 15 and in the connection hole 16, and etching the metal layer 17 to form a gate region and a source region. The metal layer 17 is preferably an aluminum layer, and its thickness is preferably 4 um.

[0043] Before the annealing operation in step 4, a junction region 18 of the second conductivity type may be formed by implantation in the surface epitaxial layer 4 around the trench 9, and the outer side of the upper end of the trench 9 is connected to the junction region 18 of the second conductivity type. The implantation amount of the junction region 18 is 4E13-6E13, the implantation energy is 100Kev-140Kev, and the implantation element is boron.

[0044] The following steps can also be selectively performed as in the prior art:

[0045] Step 10: deposit a passivation layer on the upper side of the metal layer 17, and etch the passivation layer to form opening regions of the gate and the source.

[0046] Step 11, thinning is performed from the bottom side of the substrate 1, and the remaining thickness of the device is 200um-300um. Ti, Ni and Ag (titanium, nickel and silver) are evaporated in sequence on the bottom side of the substrate 1.

[0047] Combination Figures 1 to 8 Based on the above embodiments, those skilled in the art can understand that the present invention also provides a deep trench MOS device for improving EMI, comprising a substrate 1 of a first conductivity type, wherein the substrate 1 is heavily doped with the first conductivity type, and the resistivity of the substrate 1 is generally 0.001-0.005Ω.cm. By selecting different epitaxial resistivity and thickness, different device withstand voltages can be obtained.

[0048] Several layers of intermediate epitaxial layers 2 and surface epitaxial layers 4 are arranged in sequence on the upper side of the substrate 1, and both the intermediate epitaxial layers 2 and the surface epitaxial layers 4 are lightly doped with the first conductivity type. When making the intermediate epitaxial layer 2, first grow a layer of epitaxial with a thickness of 5-7um on the upper side of the substrate 1, and then perform a general injection of impurities of the first conductivity type to form a heavily doped layer 3 of the first conductivity type. The injected element of the heavily doped layer 3 of the first conductivity type is preferably phosphorus, the injected energy is 60-80KeV, and the injected dose is 1E12-3E12. Then repeat the epitaxial growth and impurity general injection operations, generally repeated 5 to 7 times, and 6 to 8 layers of heavily doped layers 3 of the first conductivity type can be produced. The resistivity of the surface epitaxial layer 4 is 1-3Ω.cm, and the thickness is preferably 5um. The total thickness of the intermediate epitaxial layer 2 and the surface epitaxial layer 4 is preferably 45-60um, and the device withstand voltage can reach 500V-800V.

[0049] A trench 9 is formed in the middle epitaxial layer 2 and the surface epitaxial layer 4. The bottom of the trench 9 is set in the bottom middle epitaxial layer 2. The trench 9 is filled with impurities of the second conductivity type. A plurality of pillars 10 of the first conductivity type are formed on the upper side of each middle epitaxial layer 2 on both sides of the trench 9. The pillars 10 of the first conductivity type are formed by annealing the heavily doped layer 3 of the first conductivity type. The annealing temperature is 1100° C. and the annealing time is 30-180 minutes. The ends of the pillars 10 of the first conductivity type extend deep into the trench 9. The surface epitaxial layers on both sides of the trench 9 are provided with JEFT implantation regions 7. The JEFT implantation regions 7 are formed by JEFT implantation operations. The energy injected by the JEFT operation is 60Kev-80Kev, the implantation dose is 1E12-3E12, and the implantation element is phosphorus.

[0050] An oxide layer 11 is grown on the upper side of the surface epitaxial layer 4 in the terminal area, and the thickness of the oxide layer 11 is preferably 8000-12000 angstroms. A gate oxide layer 12 is grown on the upper side of the oxide layer 11 and the surface epitaxial layer 4 in the active area, and the thickness of the gate oxide layer 12 is preferably 700-1200 angstroms. Polycrystalline 13 is deposited on the upper side of the gate oxide layer 12 in the active area, and the thickness of the polycrystalline 13 is preferably 6000-8000 angstroms. The gate oxide layer 12 and the polycrystalline 13 in the terminal area, the upper side of the groove 9, and between the active area and the terminal area are etched away, and a heavily doped region 14 of the first conductivity type is formed in the surface epitaxial layer 4 on both sides of the polycrystalline 13, and the polycrystalline 13 is heavily doped at the same time. A heavily doped region 14 of the first conductivity type is formed on the surface epitaxial layer 4 and the two ends of the upper side of the groove 9 without the gate oxide layer 11 in the active area. The implantation dose of the heavily doped region 14 of the first conductivity type is 5E15-1E16, the implantation energy is 60Kev-120Kev, the implantation element is arsenic, the well-driving temperature is 950°C, and the well-driving time is 30 minutes. A dielectric layer 15 is deposited on the upper side of the surface epitaxial layer 4, the groove 9, the heavily doped region 14 of the first conductivity type and the polycrystalline 12. The dielectric layer 15 is preferably BPSG (boron phospho-silicate glass), and the thickness of the dielectric layer 15 is preferably 10000 angstroms. A connection hole 16 is etched on the dielectric layer 15, and a metal layer 17 is sputtered on the upper side of the dielectric layer 15 and in the connection hole 16, and the metal layer 17 is etched to form the gate region and source region of the MOS device. The metal layer 17 is preferably an aluminum layer, and its thickness is preferably 4um.

[0051] Before the annealing operation, a junction region 18 of the second conductivity type can be formed by implantation in the surface epitaxial layer 4 around the trench 9, and the outer side of the upper end of the trench 9 is connected to the junction region 18 of the second conductivity type. The implantation amount of the junction region 18 is 4E13-6E13, the implantation energy is 100Kev-140Kev, and the implantation element is boron.

[0052] A passivation layer may also be deposited on the upper side of the metal layer 17 and the dielectric layer 15, and an opening area with a gate and a source may be etched on the passivation layer. Ti, Ni and Ag layers may also be evaporated in sequence on the lower side of the substrate 1. Before evaporating the Ti, Ni and Ag layers, the bottom side of the substrate 1 is thinned first, and the remaining thickness of the device is 200um-300um.

[0053] The above is only a preferred embodiment of the present invention. It should be noted that for ordinary technicians in this technical field, other parts not specifically described belong to the prior art or common knowledge. Several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims

1. A method for manufacturing a deep trench MOS device for improving EMI, characterized in that: The following steps are involved: Step 1, providing a substrate of a first conductivity type, forming a plurality of intermediate epitaxial layers on the substrate, implanting a heavily doped layer of the first conductivity type on the upper side of each intermediate epitaxial layer, and forming a surface epitaxial layer on the upper side of the uppermost intermediate epitaxial layer; Step 2, growing a masking layer on the surface epitaxial layer, making a JEFT injection opening on the masking layer in the active area, and performing a JEFT injection operation on the surface epitaxial layer through the JEFT injection opening to form a JEFT injection area on the surface epitaxial layer; Step 3, forming a trench opening on the masking layer, and forming a trench on the surface epitaxial layer and the intermediate epitaxial layer through the trench opening, wherein the bottom of the trench is arranged in the bottom intermediate epitaxial layer, and impurities of the second conductivity type are filled into the trench; Step 4, performing an annealing operation to anneal the heavily doped layer to form a pillar of the first conductivity type with an end portion extending deep into the trench; Step 5, growing an oxide layer on the surface epitaxial layer, the JEFT implantation area and the upper side of the trench, and removing the oxide layer in the active area, leaving only the oxide layer in the terminal area; Step 6, growing a gate oxide layer on the upper side of the oxide layer and the surface epitaxial layer in the active area, depositing polycrystalline on the upper side of the gate oxide layer, and performing polycrystalline doping, and etching away the polycrystalline and gate oxide layer in the terminal area, the upper side of the trench, and between the active area and the terminal area; Step 7, performing impurity implantation and well-driving operations on the surface epitaxial layer and the polycrystal on both sides of the polycrystal in the active area to form a heavily doped region of the first conductivity type, and at the same time heavily doping the polycrystal; Step 8, depositing a dielectric layer on the upper side of the surface epitaxial layer, the trench, the heavily doped region of the first conductivity type and the polycrystalline, and etching the dielectric layer to form a connecting hole; Step 9, sputtering to form a metal layer on the upper side of the dielectric layer and in the connection hole, and etching the metal layer to form a gate region and a source region.

2. The method for manufacturing a deep trench MOS device for improving EMI according to claim 1, characterized in that: The implanted element of the heavily doped layer of the first conductivity type is phosphorus, the implanted energy is 60-80 KeV, and the implanted dose is 1E12-3E12.

3. The method for manufacturing a deep trench MOS device for improving EMI according to claim 1, characterized in that: The intermediate epitaxial layer includes 6 to 8 layers.

4. The method for manufacturing a deep trench MOS device for improving EMI according to claim 1, characterized in that: Before the annealing operation in step 4, a junction region of the second conductivity type is formed by implantation in the surface epitaxial layer around the trench, and the outer side of the upper end of the trench is connected to the junction region of the second conductivity type.

5. The method for manufacturing a deep trench MOS device for improving EMI according to claim 1, characterized in that: The resistivity of each intermediate epitaxial layer is 1-3Ω.cm and its thickness is 5-7um.

6. A deep trench MOS device with improved EMI manufactured by the method for manufacturing a deep trench MOS device with improved EMI according to claim 1, characterized in that: The invention comprises a substrate of a first conductive type, wherein a plurality of intermediate epitaxial layers and a surface epitaxial layer are sequentially arranged on the upper side of the substrate, a groove is formed in the intermediate epitaxial layer and the surface epitaxial layer, the bottom of the groove is arranged in the bottom intermediate epitaxial layer, the groove is filled with impurities of a second conductive type, a plurality of pillars of the first conductive type are formed on the upper side of each intermediate epitaxial layer on both sides of the groove, the ends of the pillars of the first conductive type extend into the interior of the groove, a JEFT injection region is arranged on the surface epitaxial layer on both sides of the groove, an oxide layer is grown on the upper side of the surface epitaxial layer in the terminal region, and an impurity is formed between the oxide layer and the impurity. A gate oxide layer is grown on the upper side of the surface epitaxial layer in the source region, polycrystal is deposited on the upper side of the gate oxide layer in the active region, and the gate oxide layer and polycrystal in the terminal region, the upper side of the groove, and between the active region and the terminal region are etched away, a heavily doped region of the first conductivity type is formed in the surface epitaxial layer on both sides of the polycrystal, and the polycrystal is heavily doped at the same time, a dielectric layer is deposited on the upper side of the surface epitaxial layer, the groove, the heavily doped region of the first conductivity type, and the polycrystal, a connection hole is etched on the dielectric layer, a metal layer is sputtered on the upper side of the dielectric layer and in the connection hole, and the metal layer is etched to form a gate region and a source region; A passivation layer is deposited on the upper side of the metal layer and the dielectric layer, and an opening area of ​​a gate and a source is formed by etching on the passivation layer; Ti, Ni and Ag layers are evaporated in sequence on the lower side of the substrate.

7. The deep trench MOS device for improving EMI according to claim 6, characterized in that: The intermediate epitaxial layer includes 6 to 8 layers.

8. The deep trench MOS device for improving EMI according to claim 6, characterized in that: Before the annealing operation, a junction region of the second conductivity type is implanted in the surface epitaxial layer around the trench, and the outer side of the upper end of the trench is connected to the junction region of the second conductivity type.

9. The deep trench MOS device for improving EMI according to claim 6, characterized in that: The resistivity of each intermediate epitaxial layer is 1-3Ω.cm and its thickness is 5-7um.

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