Method and related device for determining binary convolution acceleration index

Abstract

The present disclosure provides a method, device, electronic device and computer-readable medium for determining a binary convolution acceleration index, which relates to the field of artificial intelligence technology. The method includes: obtaining an effective digit acceleration index of a binary convolution of a target device; obtaining an operation acceleration index of a binary convolution of the target device; obtaining a floating-point convolution acceleration index; determining the binary convolution acceleration index according to the effective digit acceleration index of the binary convolution, the operation acceleration index and the floating-point convolution acceleration index, so as to determine the binary neural network of the neural network in the target device according to the binary convolution acceleration index. The technical solution provided by the embodiments of the present disclosure can determine the acceleration index of a binary convolution relative to a floating-point convolution, so as to determine a binary neural network in a neural network.

Description

Technical Field

[0001] The present disclosure relates to the field of artificial intelligence technology, and in particular to a method and device for determining a binary convolution acceleration index, an electronic device, and a computer-readable medium. Background Art

[0002] Currently, floating-point convolution is the most widely used in neural networks. However, floating-point convolution takes up a lot of memory and runs relatively slowly. For some tasks that need to increase the running speed to the target speed, floating-point convolution can be replaced by binary convolution.

[0003] In actual operation, if you want to replace the floating-point convolution in the neural network with binary convolution to achieve the target running speed, you need to determine the acceleration index of the binary convolution relative to the floating-point convolution to implement the design of the neural network. The acceleration index can be, for example, the acceleration ratio of the binary convolution relative to the floating-point convolution.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] In view of this, the present disclosure provides a method and apparatus, an electronic device and a computer-readable medium for determining a binary convolution acceleration index, which can provide an acceleration index of a target device performing binary convolution compared to performing floating-point convolution.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0007] According to a first aspect of an embodiment of the present disclosure, a method for determining a binary convolution acceleration index is proposed, the method comprising: obtaining an effective number of digits acceleration index of a binary convolution of a target device; obtaining an operational acceleration index of the binary convolution of the target device; obtaining a floating-point convolution acceleration index; determining the binary convolution acceleration index based on the effective number of digits acceleration index of the binary convolution, the operational acceleration index and the floating-point convolution acceleration index, so as to determine the binary neural network of the neural network in the target device based on the binary convolution acceleration index.

[0008] In some embodiments, obtaining an effective number of bits acceleration index for binary convolution of a target device includes: obtaining the number of bits of floating-point data processed by a single instruction when the target device performs a floating-point convolution operation; obtaining the number of bits of binary data processed by a single instruction when the target device performs a binary convolution operation; and determining the effective number of bits acceleration index based on the number of bits of floating-point data processed by the single instruction and the number of bits of binary data processed by the single instruction.

[0009] In some embodiments, obtaining an operation acceleration index of the binary convolution of the target device includes: obtaining the running time of the target device to perform a binary multiplication and addition operation and the running time of a floating-point multiplication and addition operation; and determining the operation acceleration index according to the running time of the binary multiplication and addition operation and the running time of the floating-point multiplication and addition operation.

[0010] In some embodiments, obtaining a floating-point convolution acceleration index includes: determining an acceleration method for the floating-point convolution, and determining the floating-point convolution acceleration index according to the acceleration method.

[0011] In some embodiments, the binary convolution acceleration index may be determined according to the following formula:

[0012] θ=Num*α*β / γ

[0013] Among them, θ represents the binary convolution acceleration index, α represents the effective number of digits acceleration index, β represents the operation acceleration index, γ represents the floating-point convolution acceleration index, and Num is a constant.

[0014] In some embodiments, the method for determining the binary convolution acceleration index also includes: obtaining all floating-point operation times and all binary operation times in the neural network; and determining the complexity of the neural network based on the floating-point operation times and the binary operation times.

[0015] In some embodiments, the method for determining a binary convolution acceleration index further includes: further including: obtaining all floating point operation times and all binary operation times in the neural network;

[0016] An acceleration index including the neural network is determined according to the floating-point operation time, the binary operation time and the binary convolution acceleration index.

[0017] According to a second aspect of an embodiment of the present disclosure, a device for determining a binary convolution acceleration index is proposed, the device comprising: an effective number of digits acceleration index determination module, configured to obtain the effective number of digits acceleration index of the binary convolution of a target device; an operation acceleration index determination module, configured to obtain the operation acceleration index of the binary convolution of the target device; a convolution acceleration index determination module, configured to obtain a floating-point convolution acceleration index; a binary convolution acceleration index determination module, configured to determine the binary convolution acceleration index based on the effective number of digits acceleration index of the binary convolution, the operation acceleration index and the floating-point convolution acceleration index, so as to determine the binary neural network of the neural network in the target device based on the binary convolution acceleration index.

[0018] According to a third aspect of an embodiment of the present disclosure, an electronic device is proposed, comprising: one or more processors; a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement any of the above-described methods for determining a binary convolution acceleration index.

[0019] According to a fourth aspect of an embodiment of the present disclosure, a computer-readable medium is proposed, on which a computer program is stored, characterized in that when the program is executed by a processor, a method for determining a binary convolution acceleration index as described in any one of the above items is implemented.

[0020] According to the method, device, electronic device and computer-readable medium for determining a binary convolution acceleration index provided in certain embodiments of the present disclosure, a binary convolution acceleration index is determined by obtaining an effective bit number acceleration index, an operation acceleration index and a floating-point convolution acceleration index, so as to facilitate the design of a binary neural network in a neural network according to the binary acceleration index.

[0021] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. The drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work.

[0023] Figure 1 A schematic diagram of an exemplary system architecture of a method for determining a binary convolution acceleration index or an apparatus for determining a binary convolution acceleration index applied to an embodiment of the present disclosure is shown.

[0024] Figure 2 It is a flowchart of a method for determining a binary convolution acceleration index according to an embodiment of the present disclosure.

[0025] Figure 3 It is a flowchart of another method for determining a binary convolution acceleration index according to an embodiment of the present disclosure.

[0026] Figure 4 It is a flowchart of another method for determining a binary convolution acceleration index according to an embodiment of the present disclosure.

[0027] Figure 5 It is a flowchart of another method for determining a binary convolution acceleration index according to an embodiment of the present disclosure.

[0028] Figure 6 It is a flowchart of another method for determining a binary convolution acceleration index according to an embodiment of the present disclosure.

[0029] Figure 7 The invention is a block diagram of a device for determining a binary convolution acceleration index according to an exemplary embodiment.

[0030] Figure 8 The invention is a block diagram of another device for determining a binary convolution acceleration index according to an exemplary embodiment.

[0031] Fig. 9 It is a block diagram of yet another device for determining a binary convolution acceleration index according to an exemplary embodiment.

[0032] Fig.10 It is a block diagram of another device for determining a binary convolution acceleration index according to an exemplary embodiment.

[0033] Fig.11 It is a block diagram of another device for determining a binary convolution acceleration index according to an exemplary embodiment.

[0034] Fig.12 The diagram is a structural diagram of a computer system applied to an apparatus for determining a binary convolution acceleration index according to an exemplary embodiment. DETAILED DESCRIPTION

[0035] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0036] The described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring various aspects of the present disclosure.

[0037] The accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some block diagrams shown in the accompanying drawings do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0038] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and steps, nor must they be executed in the order described. For example, some steps can be decomposed, and some steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0039] In this specification, the terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising", "including" and "having" are used to express an open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0040] The exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0041] Figure 1 A schematic diagram of an exemplary system architecture of a method for determining a binary convolution acceleration index or an apparatus for determining a binary convolution acceleration index that can be applied to an embodiment of the present disclosure is shown.

[0042] like Figure 1 As shown, the system architecture 100 may include terminal devices 101, 102, 103, a network 104 and a server 105. The network 104 is used to provide a medium for communication links between the terminal devices 101, 102, 103 and the server 105. The network 104 may include various connection types, such as wired, wireless communication links or optical fiber cables, etc.

[0043] Users can use terminal devices 101, 102, 103 to interact with server 105 through network 104 to receive or send messages, etc. Terminal devices 101, 102, 103 can be various electronic devices with display screens and supporting web browsing, including but not limited to smart phones, tablet computers, laptop computers, desktop computers, etc.

[0044] The server 105 may be a server that provides various services, such as a background management server that provides support for devices operated by users using the terminal devices 101, 102, and 103. The background management server may analyze and process the received request data, and feed back the processing results to the terminal device.

[0045] The server 105 can, for example, obtain an effective number of digits acceleration index of the binary convolution of the target device; obtain an operational acceleration index of the binary convolution of the target device; obtain a floating-point convolution acceleration index; determine the binary convolution acceleration index based on the effective number of digits acceleration index of the binary convolution, the operational acceleration index and the floating-point convolution acceleration index, so as to determine the binary neural network of the neural network in the target device based on the binary convolution acceleration index.

[0046] It should be understood that Figure 1 The number of terminal devices, networks and servers in the figure is only for illustration. The server 105 may be a physical server or may be composed of multiple servers. According to actual needs, it may have any number of terminal devices, networks and servers.

[0047] In the related art, a binary neural network is a neural network that binarizes floating-point weights W and hidden layer floating-point activation values.

[0048] At present, the implementation of binary networks is a relatively difficult task, because bit operations need to be used instead of floating-point operations in convolution, which is quite different from the process of ordinary networks. In the relevant technology, there has been no suitable implementation method to make people understand the true speed of binary networks. Many people start from the point that a 64-bit CPU can perform 64-bit bit operations at a time, and believe that the time it takes for the CPU to perform a floating-point operation is equivalent to the time it takes to perform a 64-bit bit operation. Therefore, the binary operation of the CPU has a 64-fold acceleration ratio relative to floating-point operations. However, the above method does not take into account the differences between binary convolution and floating-point convolution in the calculation process.

[0049] In the related art, the calculation formula of floating-point convolution can be expressed by formula (1):

[0050] sum f =∑ i x if *w if (1)

[0051] Among them, sum f represents the floating point convolution sum, x if represents the i-th input data, w if Represents the weight of the i-th input data. From formula (1), it can be seen that floating-point convolution calculation includes operations such as addition and multiplication.

[0052] In the related art, the calculation formula of binary convolution can be expressed by Formula 2:

[0053] sum t =sum t +bitcount(xnor(x jt *w jt )) (2)

[0054] Among them, sum t represents the binary convolution sum, bitcount can calculate the number of 1s in the binary system, and xnor represents the exclusive-or-not operation. jf represents the jth input data, w jf Represents the weight of the jth input data. From Formula 2, it can be seen that binary convolution not only includes addition operations but also logical operations.

[0055] In addition, floating-point convolution can also improve the running speed through some acceleration methods, which can be, for example, a fast calculation algorithm. Due to the importance of floating-point multiplication and addition operations, current CPUs (Central Processing Units) generally support fused multiply-add operations, that is, using one instruction to complete multiplication and addition, which will further reduce the gap between the speed of floating-point convolution and binary convolution. In some embodiments, the fast calculation algorithm can be, for example, Winograd algorithm and FFT (Fast Fourier Transformation).

[0056] In summary, it is inaccurate to determine the speedup ratio of binary convolution relative to floating-point convolution based solely on the number of floating-point data that can be run in the CPU and the number of binary data that can be run in the CPU.

[0057] In some embodiments, it is necessary to implement the design of the neural network based on the acceleration index of the binary convolution relative to the floating-point convolution, and the acceleration index may be a speedup ratio.

[0058] For example, there is a neural network that only includes floating-point convolutions, but its speed does not meet the requirements, and now it needs to be accelerated. At this time, replacing some floating-point convolutions with binary convolutions would be a feasible way. However, binary convolutions will reduce the accuracy of the network, so consider using multiple binary convolutions to replace floating-point convolutions. At this time, it is necessary to understand the real acceleration index of binary convolution relative to floating-point convolution, which can be, for example, the real speedup ratio of binary convolution relative to floating-point convolution.

[0059] Figure 2The method provided by the embodiment of the present disclosure can be processed by any electronic device with computing processing capabilities, such as the above-mentioned Figure 1 The server 105 and / or terminal devices 102 and 103 in the embodiment are described by taking the server 105 as the execution subject in the following embodiment, but the present disclosure is not limited to this.

[0060] Reference Figure 2 The method for determining the binary convolution acceleration index provided by the embodiment of the present disclosure may include the following steps.

[0061] Step S201, obtaining an effective number of digits acceleration index of binary convolution of a target device.

[0062] In some embodiments, the effective number of bits acceleration index of the binary convolution may be a speedup ratio of the binary convolution relative to the floating-point convolution.

[0063] Step S202, obtaining a binary convolution operation acceleration index of the target device.

[0064] Step S203, obtaining a floating-point convolution acceleration index.

[0065] Step S204, determining the binary convolution acceleration index according to the effective number of bits acceleration index of the binary convolution, the calculation acceleration index and the floating-point convolution acceleration index, so as to determine the binary neural network of the neural network in the target device according to the binary convolution acceleration index.

[0066] In this embodiment, the acceleration index of binary convolution relative to floating-point convolution is determined by obtaining the effective number of digits acceleration index, the calculation acceleration index and the floating-point convolution acceleration index. The design of the binary neural network in the neural network can be implemented based on the acceleration index of the binary convolution relative to the floating-point convolution.

[0067] Figure 3 is a flowchart of another method for determining a binary convolution acceleration index according to an exemplary embodiment. Figure 2 The method for obtaining the effective number of bits acceleration index of binary convolution of the target device shown in the embodiment may include: Figure 3 Steps shown.

[0068] Step S2011, obtaining the number of bits of floating-point data processed by a single instruction when the target device performs a floating-point convolution operation.

[0069] In some embodiments, the target device may refer to any electronic device with computing and processing capabilities, such as a server, a computer, and a mobile phone.

[0070] In some embodiments, for a neural network that needs to replace floating-point convolution with binary convolution, when judging the acceleration of the binary convolution relative to the replaced floating-point convolution, the number of bits of floating-point data processed by a single instruction when the target device performs a binary convolution operation can be first obtained.

[0071] For example, assuming that the CPU of the target device has 64-bit memory, the data to be processed is 4 32-bit floating-point data, and a single instruction of the CPU of the target device can process 2 32-bit floating-point data, then the number of bits of floating-point data processed by a single instruction when the target device performs a floating-point convolution operation is 64. In actual operations, since floating-point data occupies more bits, general floating-point operations can occupy all registers.

[0072] Of course, if in the above example, the data to be processed is only one 32-bit floating-point data, and a single instruction of the CPU of the target device can only process one 32-bit floating-point data, then the number of bits of the floating-point data processed by a single instruction when the target device performs a floating-point convolution operation is 32.

[0073] Step S2012, obtaining the number of bits of binary data processed by a single instruction when the target device performs a binary convolution operation.

[0074] In some embodiments, for a neural network that needs to replace floating-point convolution with binary convolution, when judging the acceleration of the binary convolution relative to the replaced floating-point convolution, it is also necessary to obtain the number of bits of binary data processed by a single instruction when the target device performs a binary convolution operation.

[0075] For example, before performing binary convolution, it is necessary to first binarize the floating-point data, and then obtain the number of bits of binary data that can be processed by a single instruction when the CPU of the target device uses binary convolution to process the binarized data. For example, assuming that the CPU of the target device is a 64-bit CPU, the data to be processed is 4 32-bit floating-point data, and the data to be processed becomes 4 binary data after binarization, which only occupies 4 bits of memory. A single instruction of the CPU of the target device can process the above 4 binary data, so the number of bits of binary data processed by a single instruction when the target device performs a binary convolution operation is 4. Of course, if in the above example, the data to be processed has 80 32-bit floating-point data, and the data to be processed becomes 80 binary data after binarization, the single instruction of the CPU of the target device can only process 64 binary data, and the number of bits of binary data processed by a single instruction when the target device performs a binary convolution operation is 64.

[0076] Step S2013, determining the effective number of bits acceleration index according to the number of bits of the floating-point data processed by the single instruction and the number of bits of the binary data processed by the single instruction.

[0077] In some embodiments, determining the effective number of bits acceleration index based on the number of bits of binary data processed by the single instruction and the number of bits of floating-point data processed by the single instruction may refer to: determining the effective number of bits acceleration ratio based on the number of bits of binary data processed by the single instruction and the number of bits of floating-point data processed by the single instruction.

[0078] In some embodiments, when the target device performs a floating-point convolution operation, the number of bits of floating-point data processed by a single instruction is generally equal to the CPU bit size of the target device (because floating-point data occupies more bits).

[0079] In some embodiments, when the target device performs a binary convolution operation, the number of bits of binary data processed by a single instruction may be less than or equal to the CPU bit size of the target device (because the binary data only occupies one bit of memory).

[0080] In some embodiments, since the amount of data to be processed is usually large, the number of bits of floating-point data processed by a single instruction of the target device and the number of bits of binary data processed by a single instruction can be equal, so the effective bit number acceleration index is generally equal to 1.

[0081] The method for determining a binary convolution acceleration index provided in this embodiment takes into account the memory actually occupied by each instruction of the target device in actual operation, and can effectively determine an effective bit number acceleration index of a binary convolution.

[0082] Figure 4 is a flowchart of another method for determining a binary convolution acceleration index according to an exemplary embodiment. Figure 2 The example shown in the embodiment may include obtaining the binary convolution operation acceleration index of the target device as follows: Figure 4 Steps shown.

[0083] Step S2021, obtaining the running time of the target device for performing a binary multiplication-addition operation and the running time of the target device for performing a floating-point multiplication-addition operation.

[0084] In some embodiments, the running time of a binary multiplication and addition operation may refer to the sum of the time taken by the target device to perform a binary multiplication operation and a binary addition operation. Referring to formula (2), the addition operation and the bitcount operation in the binary convolution calculation formula may be regarded as a binary addition operation, and the logical operation xnor operation may be regarded as a binary multiplication operation. In some embodiments, the above-mentioned logical operation may include any one of the logical operations such as XOR operation, XOR operation or XNOR operation.

[0085] In some embodiments, the running time of a floating-point multiplication-addition operation may refer to the sum of the operation time required for the target device to perform a floating-point multiplication and the running time required to perform a floating-point addition.

[0086] Step S2022: determining the operation acceleration index according to the running time of the binary multiplication-addition operation and the running time of the floating-point multiplication-addition operation.

[0087] In some embodiments, the multiplication-addition operation acceleration index may be determined according to the following formula:

[0088]

[0089] Where β represents the multiplication-addition operation speedup ratio, T two-a represents the running time of the above binary addition, T two-m represents the running time of the above binary multiplication operation, T float-a represents the running time of the above floating-point addition, T float-m represents the running time of the above floating-point multiplication.

[0090] The method for determining the binary convolution acceleration index shown in this embodiment obtains the time used by the target device to perform a binary multiplication and addition operation and the time used by the target device to perform a floating-point multiplication and addition operation, determines the time used by the target device to perform binary operations and the time used to perform floating-point multiplication and addition operations, and determines the acceleration index of the binary operation time relative to the floating-point multiplication and addition operation time.

[0091] In some embodiments, Figure 2 The embodiment shown in the figure shows that determining the operation acceleration index according to the running time of the binary operation and the running time of the floating-point operation may include: determining an acceleration method of the floating-point convolution, and determining the floating-point convolution acceleration index according to the acceleration method.

[0092] In some embodiments, the floating point convolution acceleration method may refer to some fast algorithms for floating point convolution, which can greatly reduce the amount of calculation and greatly improve the actual speed, such as Winograd algorithm and FFT. In some embodiments, the use of Winograd algorithm can accelerate floating point operations by 2 to 3 times. However, binary convolution can only enjoy the acceleration of bit operations, so binary convolution cannot use these fast convolution algorithms.

[0093] In some embodiments, the fast algorithms used in floating-point convolution may be first determined, and then the degree to which the floating-point convolution is accelerated by these fast algorithms may be determined to determine the floating-point convolution acceleration index.

[0094] This embodiment determines the speed-up of floating-point convolution after using the acceleration method.

[0095] In some embodiments, the binary convolution acceleration index may be determined according to the following formula:

[0096] θ=Num*α*β / γ (4)

[0097] Among them, θ represents the binary convolution acceleration index, α represents the effective number of digits acceleration index, β represents the operation acceleration index, γ represents the floating-point convolution acceleration index, and Num is a constant.

[0098] In some embodiments, Num is equal to the size of the number of bits of floating point data that the target device can process. For example, if the target device can process 32-bit floating point data, then Num is equal to 32, and if it can process 64-bit floating point data, then Num is equal to 64.

[0099] In some other embodiments, Figure 2 The method for determining the binary convolution acceleration index shown in the illustrated embodiment may also include: Figure 5 Steps shown.

[0100] Step S205, obtaining all floating-point operation times and all binary operation times in the neural network.

[0101] In some embodiments, a neural network may include both floating-point convolution and binary convolution. In some embodiments, the time required for all multiplication and addition operations performed by the neural network when performing floating-point convolution and the time required for all binary operations performed by the neural network when performing binary convolution may be obtained.

[0102] Step S206, determining the complexity of the neural network according to the floating-point operation time and the binary operation time.

[0103] In some embodiments, the complexity of the neural network may be determined according to the following formula:

[0104] OP s =f+b / S conv (5)

[0105] Among them, OP s represents the complexity of the neural network, f represents the time required for all multiplication and addition operations performed by the neural network when running floating-point convolution, b represents the time required for all binary operations performed by the neural network when running binary convolution, and S conv Represents the binary convolution acceleration index.

[0106] The method for determining the binary convolution acceleration index provided in this embodiment maps the complexity of the binary convolution to the floating-point convolution domain when determining the complexity of the neural network so that the complexity finally obtained is in the same domain.

[0107] In some other embodiments, Figure 2 The method for determining the binary convolution acceleration index shown in the illustrated embodiment may also include: Figure 6 Steps shown.

[0108] In some embodiments, part of the floating-point convolutions in a neural network including floating-point convolutions may be replaced with binary convolutions, and the speedup of the neural network in which the floating-point convolutions are replaced with binary convolutions relative to the neural network in which the floating-point convolutions are not replaced with binary convolutions can be determined based on the acceleration index of the neural network.

[0109] Step S207, obtaining all floating point operation times and all binary operation times in the neural network.

[0110] In some embodiments, a neural network may include both floating-point convolution and binary convolution. In some embodiments, the time required for all multiplication and addition operations performed by the neural network when performing floating-point convolution and the time required for all binary operations performed by the neural network when performing binary convolution may be obtained.

[0111] Step S208, determining an acceleration index including the neural network according to the floating-point operation time, the binary operation time and the binary convolution acceleration index.

[0112] In some embodiments, the acceleration index of the neural network can be determined according to the following formula.

[0113]

[0114] Among them, S net represents the complexity of the neural network, f represents the time required for all multiplication and addition operations performed by the neural network when running floating-point convolution, b represents the time required for all binary operations performed by the neural network when running binary convolution, and S conv Represents the binary convolution acceleration index.

[0115] According to the method provided in this embodiment, the acceleration index of the neural network can be determined, and the acceleration index of the neural network can make an accurate judgment on the speed-up of the neural network after replacing part of the floating-point convolution with the binary convolution.

[0116] Figure 7 is a block diagram of a device for determining a binary convolution acceleration index according to an exemplary embodiment. Figure 7 The device 700 provided in this embodiment may include an effective number of digits acceleration index determination module 701, an operation acceleration index determination module 702, a convolution acceleration index determination module 703 and a binary convolution acceleration index determination module 704.

[0117] Among them, the effective number of digits acceleration index determination module 701 can be configured to obtain the effective number of digits acceleration index of the binary convolution of the target device. The operation acceleration index determination module 702 can be configured to obtain the operation acceleration index of the binary convolution of the target device. The convolution acceleration index determination module 703 can be configured to obtain the floating-point convolution acceleration index. The binary convolution acceleration index determination module 704 can be configured to determine the binary convolution acceleration index according to the effective number of digits acceleration index of the binary convolution, the operation acceleration index and the floating-point convolution acceleration index, so as to determine the binary neural network of the neural network in the target device according to the binary convolution acceleration index.

[0118] In some embodiments, Figure 7 In the embodiment shown, the effective number of bits acceleration index determination module 701 may include the following: Figure 8 The illustrated embodiment shows a binary data bit number determination unit 7011 and a floating point data bit number determination unit 7012 .

[0119] The binary data bit number determination unit 7011 may be configured to obtain the number of bits of binary data processed by a single instruction when the target device performs the binary convolution operation.

[0120] The floating-point data bit number determination unit 7012 may be configured to obtain the number of bits of floating-point data processed by a single instruction when the target device performs a floating-point convolution operation.

[0121] In some embodiments, Figure 7 The computing acceleration index determination module 702 in the illustrated embodiment may include: Fig. 9 The illustrated embodiment shows a running time determination unit 7021 and an operation index determination unit 7022 .

[0122] The runtime determining unit 7021 may be configured to obtain the runtime of the target device for performing binary operations and the runtime of the target device for performing floating-point operations.

[0123] The operation index determination unit 7022 may be configured to determine the operation acceleration index according to the running time of the binary operation and the running time of the floating-point operation.

[0124] In some embodiments, Figure 7 The convolution acceleration index determination module 703 in the illustrated embodiment may also be configured to determine an acceleration method for the floating-point convolution, and determine the floating-point convolution acceleration index according to the acceleration method.

[0125] In some embodiments, the binary convolution acceleration index may be determined according to the following formula:

[0126] θ=Num*α*β / γ (7)

[0127] Among them, θ represents the binary convolution acceleration index, α represents the effective number of digits acceleration index, β represents the operation acceleration index, γ represents the floating-point convolution acceleration index, and Num is a constant.

[0128] In some embodiments, Figure 7 The device 700 may also include: Fig.10 The first operation time determination module 705 and the neural network complexity determination module 706.

[0129] The first operation time determination module 705 may be configured to obtain all floating point operation times and all binary operation times in the neural network.

[0130] The neural network complexity determination module 706 may be configured to determine the complexity of the neural network according to the sum of the floating point operation time and the binary operation time.

[0131] In some embodiments, Figure 7 The device 700 may also include: Fig.11 The second operation time determination module 707 and the neural network acceleration index determination module 708.

[0132] The second operation time determination module 707 may be configured to obtain all floating point operation times and all binary operation times in the neural network.

[0133] The neural network acceleration index determination module 708 may be configured to determine an acceleration index including the neural network according to the floating-point operation time, the binary operation time and the binary convolution acceleration index.

[0134] Since the functional modules of the apparatus 700 for determining a binary convolution acceleration index in the example embodiment of the present disclosure correspond to the steps of the example embodiment of the method for determining a binary convolution acceleration index described above, they will not be described in detail here.

[0135] Reference below Fig.12 , which shows a schematic diagram of the structure of a computer system 1200 of a terminal device suitable for implementing an embodiment of the present application. Fig.12 The terminal device shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0136] like Fig.12As shown, the computer system 1200 includes a central processing unit (CPU) 1201, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1202 or a program loaded from a storage part 1208 into a random access memory (RAM) 1203. In the RAM 1203, various programs and data required for the operation of the system 1200 are also stored. The CPU 1201, the ROM 1202, and the RAM 1203 are connected to each other via a bus 1204. An input / output (I / O) interface 1205 is also connected to the bus 1204.

[0137] The following components are connected to the I / O interface 1205: an input section 1206 including a keyboard, a mouse, etc.; an output section 1207 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1208 including a hard disk, etc.; and a communication section 1209 including a network interface card such as a LAN card, a modem, etc. The communication section 1209 performs communication processing via a network such as the Internet. A drive 1210 is also connected to the I / O interface 1205 as needed. A removable medium 1211, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1210 as needed, so that a computer program read therefrom is installed into the storage section 1208 as needed.

[0138] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part 1209, and / or installed from a removable medium 1211. When the computer program is executed by a central processing unit (CPU) 1201, the above-mentioned functions defined in the system of the present application are executed.

[0139] It should be noted that the computer-readable medium shown in the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0140] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the above-mentioned module, program segment or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0141] The units involved in the embodiments described in the present application may be implemented by software or hardware. The units described may also be set in a processor, for example, it may be described as: a processor includes a sending unit, an acquiring unit, a determining unit, and a first processing unit. The names of these units do not constitute limitations on the units themselves in some cases.

[0142] As another aspect, the present application also provides a computer-readable medium, which may be included in the device described in the above embodiment; or it may exist independently without being assembled into the device. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by a device, the device can implement functions including: obtaining an effective digit acceleration index of the binary convolution of the target device; obtaining an operation acceleration index of the binary convolution of the target device; obtaining a floating-point convolution acceleration index; determining the binary convolution acceleration index according to the effective digit acceleration index of the binary convolution, the operation acceleration index and the floating-point convolution acceleration index, so as to determine the binary neural network of the neural network in the target device according to the binary convolution acceleration index.

[0143] Through the description of the above implementation methods, it is easy for those skilled in the art to understand that the example implementation methods described here can be implemented by software, or by combining software with necessary hardware. Therefore, the technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.), including a number of instructions for a computing device (which can be a personal computer, a server, a mobile terminal, or a smart device, etc.) to execute the method according to the embodiment of the present disclosure, for example Figure 2 One or more of the steps shown.

[0144] In addition, the above-mentioned figures are only schematic illustrations of the processes included in the method according to the exemplary embodiments of the present disclosure, and are not intended to be limiting. It is easy to understand that the processes shown in the above-mentioned figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0145] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the disclosure disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not applied for by the present disclosure. The specification and embodiments are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

[0146] It should be understood that the present disclosure is not limited to the detailed structures, drawings or implementations shown herein, but rather the present disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A method for determining a binary convolution acceleration index, characterized in that: include: Obtaining an effective number of digits acceleration index of binary convolution of a target device; wherein the effective number of digits acceleration index is determined according to the number of bits of binary data processed by a single instruction of the target device and the number of bits of floating-point data processed by a single instruction of the target device; Obtaining an operation acceleration index of a binary convolution of the target device; the operation acceleration index is determined according to a running time of a binary multiplication-addition operation of the target device and a running time of a floating-point multiplication-addition operation of the target device; Obtaining a floating-point convolution acceleration index; the floating-point convolution acceleration index is determined according to the acceleration method of the floating-point convolution; The binary convolution acceleration index is determined according to the effective number of bits acceleration index of the binary convolution, the operation acceleration index and the floating-point convolution acceleration index, so as to be used for designing the binary neural network of the neural network in the target device according to the binary convolution acceleration index.

2. The method according to claim 1, characterized in that: Get the effective number of bits acceleration index of binary convolution of the target device, including: Obtaining the number of bits of floating-point data processed by a single instruction when the target device performs a floating-point convolution operation; Obtaining the number of bits of binary data processed by a single instruction when the target device performs a binary convolution operation; The effective number of bits acceleration index is determined according to the number of bits of floating-point data processed by the single instruction and the number of bits of binary data processed by the single instruction.

3. The method according to claim 1, characterized in that: Obtaining the binary convolution operation acceleration index of the target device, including: Obtaining the running time of the target device for performing one binary multiplication-addition operation and one floating-point multiplication-addition operation; The operation acceleration index is determined according to the running time of the binary multiplication and addition operation and the running time of the floating-point multiplication and addition operation.

4. The method according to claim 1, characterized in that: Get floating-point convolution acceleration indicators, including: An acceleration method for the floating-point convolution is determined, and an acceleration index for the floating-point convolution is determined according to the acceleration method.

5. The method according to claim 1, characterized in that: The binary convolution acceleration index can be determined according to the following formula: θ=Num*α*β / γ Among them, θ represents the binary convolution acceleration index, α represents the effective number of digits acceleration index, β represents the operation acceleration index, γ represents the floating-point convolution acceleration index, and Num is a constant.

6. The method according to claim 1, characterized in that: Also includes: Obtain all floating-point operation times and all binary operation times in the neural network; The complexity of the neural network is determined according to the sum of the floating-point operation time and the binary operation time.

7. The method according to claim 1, characterized in that: Also includes: Obtain all floating-point operation times and all binary operation times in the neural network; An acceleration index including the neural network is determined according to the floating-point operation time, the binary operation time and the binary convolution acceleration index.

8. A device for determining a binary convolution acceleration index, characterized in that: include: An effective digit acceleration index determination module is configured to obtain an effective digit acceleration index of a binary convolution of a target device; wherein the effective digit acceleration index is determined according to the number of bits of binary data processed by a single instruction of the target device and the number of bits of floating-point data processed by a single instruction of the target device; an operation acceleration index determination module, configured to obtain an operation acceleration index of a binary convolution of the target device; the operation acceleration index is determined according to a running time of a binary multiplication and addition operation of the target device and a running time of a floating-point multiplication and addition operation of the target device; A convolution acceleration index determination module is configured to obtain a floating-point convolution acceleration index; the floating-point convolution acceleration index is determined according to the acceleration method of the floating-point convolution; a binary convolution acceleration index determination module is configured to determine the binary convolution acceleration index according to the effective number of digits acceleration index of the binary convolution, the operation acceleration index and the floating-point convolution acceleration index, so as to design a binary neural network for determining the neural network in the target device according to the binary convolution acceleration index.

9. An electronic device, characterized in that: include: one or more processors; a storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 7.

10. A computer readable medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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