Cascade Devices

Abstract

The present invention discloses a cascade device, the cascade device includes a substrate, an epitaxial structure located on the substrate, a plurality of passivation layers located on the epitaxial structure, and a plurality of electrodes, the epitaxial structure includes a channel layer located on the substrate and a barrier layer located on the channel layer, the epitaxial structure is provided with an enhancement region and a depletion region, the electrodes include a source, a drain, an intermediate electrode, a first gate, and a second gate located on the epitaxial structure, the second gate is electrically connected to the source, and the source, the drain, and the first gate serve as the source, the drain, and the gate of the cascade device, respectively. The present invention effectively separates the interaction between the low-voltage enhancement-type part and the high-voltage depletion-type part in the cascade device by introducing an intermediate electrode in the cascade device; suppresses the problem of increased gate leakage current caused by dry etching of the low-voltage part gate, improves the overall withstand voltage of the device, and enables it to be suitable for high-voltage application scenarios.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a cascade device. Background Art

[0002] Aluminum Gallium Nitride / GaN high electron mobility transistors have gradually attracted attention in different application scenarios due to their excellent power switching characteristics. In 2018, Anker released the first fast-charging product based on GaN power devices, which kicked off the application of GaN power devices in consumer electronics. Compared with traditional silicon-based solutions, fast-charging solutions based on GaN power devices are smaller in size, higher in power, higher in efficiency, and lower in heat generation. These characteristics are all due to the lower on-resistance and parasitic capacitance of GaN devices. However, commercial GaN power devices at this stage are over-designed due to device reliability considerations and have not fully utilized the advantages of their materials.

[0003] Traditional GaN power devices rely on p-type gate technology to achieve enhancement mode operation. In the process of realizing p-type gate, a two-step method is usually adopted: first, dry etching or selective growth is used to define the p-type GaN or AlGaN portion of the gate region; then the gate metal region is defined by the second step of mask lithography. This method brings many problems to devices and processes: first, the two-step mask lithography process requires over-design of the p-type GaN or AlGaN in the gate region, that is, the line width of the p-type GaN or AlGaN needs to be greater than the gate metal line width, which leads to an increase in the device on-resistance and gate capacitance; secondly, during the etching and opening process of the gate metal in the second step, the p-type GaN surface in the gate region will be damaged, which may cause an increase in the gate leakage current of the device or cause reliability problems to the device; finally, from a process perspective, the two-step mask lithography process will challenge the accuracy of lithography and increase the cost of the process.

[0004] In response to the above problems, EPC of the United States proposed a GaN enhancement device based on self-aligned gate technology. Unlike the traditional two-step method, this technology first plates the gate metal on the entire device epitaxy, and then defines the gate metal and the underlying p-type GaN or AlGaN in one step through etching, thereby achieving self-alignment of p-type GaN or AlGaN with the gate metal. This process technology can effectively reduce the device gate width and maximize the advantages of GaN enhancement devices based on p-type gate technology; at the same time, the process cost is saved due to the reduction of process steps. However, since the dry etching process is still required in the process of defining the gate metal and p-type GaN or AlGaN, the gate of the device, especially the drain side, will still be inevitably damaged by etching. Compared with the traditional p-type gate technology based on the two-step method, the gate metal of the device based on the self-aligned technology directly contacts the edge of the p-type GaN or AlGaN etching damage, so the gate leakage current is also greater than that of the traditional device. For this reason, in practical applications, GaN enhancement-mode devices based on self-aligned gate technology cannot be suitable for high-voltage (650V) applications.

[0005] Therefore, in view of the above technical problems, it is necessary to provide a cascade device. Summary of the invention

[0006] The object of the present invention is to provide a cascade device to improve the overall withstand voltage of a gallium nitride enhancement mode device based on self-aligned gate technology and enable the use of the device in high-voltage application scenarios.

[0007] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

[0008] A cascade device, the cascade device comprises a substrate, an epitaxial structure located on the substrate, a plurality of passivation layers located on the epitaxial structure, and a plurality of electrodes, the epitaxial structure comprises a channel layer located on the substrate and a barrier layer located on the channel layer, an enhancement region and a depletion region are provided on the epitaxial structure, the electrodes comprise a source located on the epitaxial structure, a drain, an intermediate electrode located between the source and the drain and between the enhancement region and the depletion region, a first gate located on the enhancement region and between the source and the intermediate electrode, and a second gate located on the depletion region and between the intermediate electrode and the drain, the second gate being electrically connected to the source, the source, the drain, and the first gate serving as the source, the drain, and the gate of the cascade device, respectively.

[0009] In one embodiment, the passivation layer comprises:

[0010] A first passivation layer is located above the epitaxial structure and the source, drain and intermediate electrodes;

[0011] A second passivation layer is located above the first passivation layer, and the thickness of the second passivation layer is less than the thickness of the first passivation layer;

[0012] A plurality of third passivation layers are located above the second passivation layer and the first gate and the second gate.

[0013] In one embodiment, the first passivation layer is a combination of one or more silicon nitride layers or silicon oxide layers, with a thickness of 50nm to 250nm; the second passivation layer is a combination of one or more silicon nitride layers, aluminum oxide layers, and silicon oxide layers, with a thickness of 10nm to 100nm; the third passivation layer is a combination of one or more silicon nitride layers or silicon oxide layers, and each layer has a thickness of 50nm to 1000nm.

[0014] In one embodiment, the enhancement region includes a first groove running through the entire first passivation layer and a p-type doped layer located in the first groove, and the first gate is located on the p-type doped layer; the depletion region includes a second groove running through the entire first passivation layer, and the second passivation layer is filled between the second gate and the second groove.

[0015] In one embodiment, the first gate and the p-type doped layer are formed based on a self-aligned gate technology, the first gate is located directly above the p-type doped layer, and a cross-sectional shape of the first gate is completely identical to a cross-sectional shape of the p-type doped layer.

[0016] In one embodiment, the p-type doped layer is a p-type gallium nitride layer or a p-type aluminum gallium nitride layer.

[0017] In one embodiment, the cascade device further includes one or more metal connection layers electrically connected to the first gate and the source of the cascade device.

[0018] In one embodiment, the substrate is a combination of one or more of silicon, sapphire, and silicon carbide; and the channel layer and the barrier layer are group III nitrides.

[0019] In one embodiment, the channel layer is a gallium nitride layer, and the barrier layer is an aluminum gallium nitride layer.

[0020] In one embodiment, the epitaxial structure further includes a buffer layer located between the channel layer and the substrate, and the buffer layer is a combination of one or more of an aluminum nitride layer, a gallium nitride layer, and an aluminum gallium nitride layer.

[0021] Compared with the prior art, the present invention has the following advantages:

[0022] The present invention effectively separates the interaction between the low-voltage enhancement-type part and the high-voltage depletion-type part in the cascade device by introducing an intermediate electrode in the cascade device.

[0023] Combined with the characteristics of the cascade device, the depletion-type part shields and protects the enhancement-type part, so that the enhancement-type part will not be affected by high voltage, thereby suppressing the problem of increased gate leakage current caused by dry etching of the low-voltage part gate, and improving the overall voltage resistance of the device, making it suitable for high-voltage application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 It is a structural schematic diagram of a cascade device in a specific embodiment of the present invention;

[0026] Figure 2 FIG. 4 is an equivalent circuit diagram of a cascade device in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0027] The present invention will be described in detail below in conjunction with the various embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0028] Ginseng Figure 1 As shown, a cascade device in a specific embodiment of the present invention mainly includes a monolithically integrated low-voltage enhancement-mode device 110 and a high-voltage depletion-mode device 120 .

[0029] Specifically, the cascade device includes a substrate 210, an epitaxial structure located on the substrate, a plurality of passivation layers located on the epitaxial structure, and a plurality of electrodes.

[0030] The epitaxial structure includes a channel layer 230 located on the substrate 210 and a barrier layer 240 located on the channel layer 230 . Preferably, the epitaxial structure in this embodiment further includes a buffer layer 220 located between the channel layer 230 and the substrate 210 .

[0031] Specifically, the substrate 210 is a combination of one or more of silicon, sapphire, silicon carbide, etc.; the buffer layer 220 is a combination of one or more of an aluminum nitride layer, a gallium nitride layer, an aluminum gallium nitride layer, etc.; the channel layer 230 and the barrier layer 230 are group III nitrides, preferably, the channel layer is a gallium nitride layer, and the barrier layer is an aluminum gallium nitride layer.

[0032] The passivation layer in this embodiment includes:

[0033] A first passivation layer 251 is located above the epitaxial structure and the source, drain and intermediate electrode. Preferably, the first passivation layer is a combination of one or more silicon nitride layers or silicon oxide layers, etc., with a thickness of 50 nm to 250 nm.

[0034] The second passivation layer 252 is located above the first passivation layer, and the thickness of the second passivation layer is less than the thickness of the first passivation layer. Preferably, the second passivation layer is a combination of one or more of a silicon nitride layer, an aluminum oxide layer, a silicon oxide layer, etc., and the thickness is 10nm to 100nm;

[0035] Several third passivation layers 253 are located above the second passivation layer and the first gate and the second gate. Preferably, the third passivation layer is a combination of one or more silicon nitride layers or silicon oxide layers, and the thickness of each layer is 50nm to 1000nm. In this embodiment, one layer of the third passivation layer is taken as an example for description.

[0036] In this embodiment, the epitaxial structure is provided with an enhancement region and a depletion region, and the electrodes include a source 261, a drain 262 and an intermediate electrode 264 located on the epitaxial structure, a first gate 263 located on the enhancement region and between the source and the intermediate electrode, and a second gate 265 located on the depletion region and between the intermediate electrode and the drain, and the second gate 265 is electrically connected to the source 261.

[0037] In this embodiment, the source, drain and gate of the low voltage enhancement mode device 110 are respectively the source 261, the middle electrode 264 and the first gate 263, and the source, drain and gate of the high voltage depletion mode device 120 are respectively the middle electrode 264, the drain 262 and the second gate 265. The source S, drain D and gate G of the entire cascade device are respectively the source 261, the drain 262 and the first gate 263.

[0038] In this embodiment, the middle electrode 264 serves as both the drain of the low-voltage enhancement-mode device 110 and the source of the high-voltage depletion-mode device 120 .

[0039] The drain and source of the low-voltage enhancement mode device can be a metallization structure that does not contain Au, such as Ti / Al / TiN, or a metallization structure based on Au, such as Ti / Al / Ni / Au; the gate can be a metallization structure that does not contain Au, such as TiN / Al / TiN, or a metallization structure based on Au, such as Ti(Ni) / Au.

[0040] The enhancement region in the low-voltage enhancement mode device includes a first groove (unnumbered) that passes through the entire first passivation layer 251 and a p-type doped layer 270 located in the first groove, the p-type doped layer is a p-type gallium nitride layer or a p-type aluminum gallium nitride layer, the first gate 263 is arranged in contact with the p-type doped layer 270, and the first gate is a structure based on p-type gallium nitride or p-type aluminum gallium nitride to realize the enhancement mode of operation.

[0041] The low voltage part in this embodiment is a gallium nitride enhancement device based on self-aligned gate technology. The first gate and the p-type doped layer are formed based on the self-aligned gate technology. The first gate is located directly above the p-type doped layer and the cross-sectional shape of the first gate is exactly the same as the cross-sectional shape of the p-type doped layer.

[0042] The drain and source of the high-voltage depletion-mode device can be a metallization structure that does not contain Au, such as Ti / Al / TiN, or a metallization structure based on Au, such as Ti / Al / Ni / Au; the gate metal can be a metallization structure that does not contain Au, such as TiN / Al / TiN, or a metallization structure based on Au, such as Ti(Ni) / Au.

[0043] The depletion region in the high-voltage depletion-mode device includes a second groove (unnumbered) that runs through the entire first passivation layer 251, and a second passivation layer 252 is filled between the second gate and the second groove. The gate can realize a depletion-mode operation mode by a structure based on a metal-insulating layer-semiconductor, wherein the dielectric layer is a second passivation layer, and the material is silicon nitride, aluminum oxide or silicon oxide, etc., with a thickness of 10nm to 100nm.

[0044] In this embodiment, the second gate 265 of the high-voltage depletion-mode device is electrically connected to the source 261 of the low-voltage enhancement-mode device through one or more metal connection layers 2651. The metal connection layer can be a metallization structure that does not contain Au, such as Ti / Al / TiN, or a metallization structure based on Au, such as Ti(Ni) / Au. In addition, the high-voltage depletion-mode device can also include one or more source field plates, with one or more metal connection layers serving as field plate metals.

[0045] Ginseng Figure 2 FIG. 1 is an equivalent circuit diagram of the cascade device in this embodiment, which includes:

[0046] A low voltage enhancement mode device 110 and a high voltage depletion mode device 120, wherein the low voltage enhancement mode device 110 comprises a first gate 1101, a first source 1102 and a first drain 1103, and the high voltage depletion mode device 120 comprises a second gate 1201, a second source 1202 and a second drain 1203, and the first drain 1103 of the low voltage depletion mode device 110 is electrically connected to the second source 1202 of the high voltage depletion mode device 120, as an intermediate electrode A (i.e. Figure 1264), the first source 1102 of the low voltage enhancement mode device 110 is electrically connected to the second gate 1201 of the high voltage depletion mode device 120, serving as the source S of the cascade circuit, the first gate 1101 of the low voltage enhancement mode device 120 serves as the gate G of the cascade circuit, and the second drain 1203 of the high voltage depletion mode device 120 serves as the drain D of the cascade circuit.

[0047] In the prior art, gallium nitride enhancement-mode devices based on self-aligned gate technology are difficult to use in high-voltage (650V level) applications due to unavoidable etching damage and other process reasons. The present invention combines the classic cascade structure and realizes the protection of enhancement-mode devices based on self-aligned gate technology through monolithic integrated high-voltage depletion-mode devices, thereby reducing the latter's withstand voltage requirements.

[0048] Moreover, compared with the traditional monolithically integrated dual-gate structure, the present invention introduces an additional intermediate electrode between the two gates of the low-voltage enhancement-mode device and the high-voltage depletion-mode device, which together serve as the drain of the low-voltage enhancement-mode device and the source of the high-voltage depletion-mode device. The introduction of the intermediate electrode can effectively isolate the interaction between the low-voltage enhancement-mode device and the high-voltage depletion-mode device, optimize the electric field distribution between the two gates in the traditional dual-gate structure, and further improve the stability of the cascade device.

[0049] Through the above structure, the cascade device in the present invention only needs to have a withstand voltage of less than 30V, and the entire device can work normally in high-voltage (650V) applications, greatly reducing the impact of process problems such as etching damage on devices based on self-aligned gate technology. This structure can also fully utilize the advantages of self-aligned gate technology, and compared with traditional gallium nitride enhancement devices and dual-gate structures, it can achieve smaller parasitic capacitance and higher switching speed.

[0050] It can be seen from the above technical solutions that the present invention has the following beneficial effects:

[0051] The present invention effectively separates the interaction between the low-voltage enhancement-type part and the high-voltage depletion-type part in the cascade device by introducing an intermediate electrode in the cascade device.

[0052] Combined with the characteristics of the cascade device, the depletion-type part shields and protects the enhancement-type part, so that the enhancement-type part will not be affected by high voltage, thereby suppressing the problem of increased gate leakage current caused by dry etching of the low-voltage part gate, and improving the overall voltage resistance of the device, making it suitable for high-voltage application scenarios.

[0053] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0054] In addition, it should be understood that although the present specification is described according to embodiments, not every embodiment contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation methods that those skilled in the art can understand.

Claims

1. A cascade device, characterized in that: The cascade device includes a substrate, an epitaxial structure located on the substrate, a plurality of passivation layers located on the epitaxial structure, and a plurality of electrodes. The epitaxial structure includes a channel layer located on the substrate and a barrier layer located on the channel layer. An enhancement region and a depletion region are provided on the epitaxial structure. The electrodes include a source, a drain, an intermediate electrode located between the source and the drain and between the enhancement region and the depletion region, a first gate located on the enhancement region and between the source and the intermediate electrode, and a second gate located on the depletion region and between the intermediate electrode and the drain. The source, the drain, and the intermediate electrode all penetrate the barrier layer and extend into the channel layer. The second gate is electrically connected to the source. The source, the drain, and the first gate serve as the source, the drain, and the gate of the cascade device, respectively.

2. The cascade device according to claim 1, characterized in that: The passivation layer comprises: A first passivation layer is located above the epitaxial structure and the source, drain and intermediate electrodes; A second passivation layer is located above the first passivation layer, and the thickness of the second passivation layer is less than the thickness of the first passivation layer; A plurality of third passivation layers are located above the second passivation layer and the first gate and the second gate.

3. The cascade device according to claim 2, characterized in that: The first passivation layer is a combination of one or more silicon nitride layers or silicon oxide layers, with a thickness of 50nm~250nm; the second passivation layer is a combination of one or more silicon nitride layers, aluminum oxide layers, and silicon oxide layers, with a thickness of 10nm~100nm; the third passivation layer is a combination of one or more silicon nitride layers or silicon oxide layers, and each layer has a thickness of 50nm~1000nm.

4. The cascade device according to claim 2, characterized in that: The enhancement region includes a first groove running through the entire first passivation layer and a p-type doped layer located in the first groove, and the first gate is located on the p-type doped layer; the depletion region includes a second groove running through the entire first passivation layer, and the second gate and the second groove are filled with a second passivation layer.

5. The cascade device according to claim 4, characterized in that: The first gate and the p-type doping layer are formed based on a self-aligned gate technology. The first gate is located directly above the p-type doping layer and the cross-sectional shape of the first gate is completely the same as the cross-sectional shape of the p-type doping layer.

6. The cascade device according to claim 4, characterized in that: The p-type doped layer is a p-type gallium nitride layer or a p-type aluminum gallium nitride layer.

7. The cascade device according to claim 1, characterized in that: The cascade device further includes one or more metal connection layers electrically connected to the first gate and the source of the cascade device.

8. The cascade device according to claim 1, characterized in that: The substrate is a combination of one or more of silicon, sapphire and silicon carbide; the channel layer and the barrier layer are group III nitrides.

9. The cascade device according to claim 8, characterized in that: The channel layer is a gallium nitride layer, and the barrier layer is an aluminum gallium nitride layer.

10. The cascade device according to claim 1, characterized in that: The epitaxial structure further includes a buffer layer located between the channel layer and the substrate, and the buffer layer is a combination of one or more of an aluminum nitride layer, a gallium nitride layer, and an aluminum gallium nitride layer.

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