Memory system

Abstract

An embodiment of the present invention provides a nonvolatile semiconductor memory device and a memory system capable of improving processing capability. The memory system (1) of the embodiment includes a first nonvolatile semiconductor memory device (10) and a controller (100). The first nonvolatile semiconductor memory device (10) includes: a first circuit (60) connected to a first terminal receiving a second signal REn; and a second circuit (52) controlling the first circuit (60) according to a first signal ODTEN. The second circuit (52) turns off the first and second switching elements (61) and (62) when the second signal REn is at a first logic ("H") level when the logic level of the first signal ODTEN is switched, and turns on the first and second switching elements (61) and (62) when the second signal REn is at a second logic ("L") level.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application. The parent application is an invention patent application filed on March 11, 2016, with application number 201610140470.7 and title “Non-volatile Semiconductor Storage Device and Memory System.”

[0003] [Related Applications]

[0004] This application claims the benefit of priority from Japanese Patent Application No. 2015-213299 (filing date: October 29, 2015), the entire contents of which are incorporated herein by reference. Technical Field

[0005] Embodiments of the present invention relate to a nonvolatile semiconductor memory device and a memory system. Background Art

[0006] As a nonvolatile semiconductor storage device, a NAND (Not AND) type flash memory is known. Summary of the Invention

[0007] Embodiments of the present invention provide a nonvolatile semiconductor memory device and a memory system capable of improving processing capabilities.

[0008] A memory system according to an embodiment includes a first nonvolatile semiconductor memory device and a controller. The controller is capable of transmitting a first signal and a second signal for controlling the timing of reading data during a read operation to the first nonvolatile semiconductor memory device. The first nonvolatile semiconductor memory device includes: a first terminal connected to the controller and receiving a second signal; a first circuit including first and second resistors connected to the first terminal, a first switch electrically connecting the first resistor to a power supply voltage line, and a second switch electrically connecting the second resistor to a ground voltage line; and a second circuit controlling the first circuit using the first signal. The second circuit turns off the first and second switches when the second signal is at the first logic level during switching of the logic levels of the first signal, and turns on the first and second switches when the second signal is at the second logic level. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a block diagram of the memory system according to the first embodiment.

[0010] Figure 2 This is a cross-sectional view of the nonvolatile semiconductor memory device according to the first embodiment.

[0011] Figure 3This is a block diagram of the nonvolatile semiconductor memory device according to the first embodiment.

[0012] Figure 4 This is a circuit diagram schematically showing the connection between input / output terminals and an input / output control circuit in the nonvolatile semiconductor memory device according to the first embodiment.

[0013] Figure 5 This is a circuit diagram schematically showing the connection between input / output terminals and a logic circuit in the nonvolatile semiconductor memory device according to the first embodiment.

[0014] Figure 6 This is a flowchart showing control of the ODT circuit in the memory system according to the first embodiment.

[0015] Figure 7 This is a diagram showing the relationship between the control mode of the ODT circuit and the logical states of various control signals in the memory system according to the first embodiment.

[0016] Figure 8 This is a timing chart of various signals when the Feature is set in the memory system according to the first embodiment.

[0017] Figure 9 This is a timing chart of various signals during a write operation in the memory system according to the first embodiment.

[0018] Figure 10 This is a timing chart of various signals during a read operation in the memory system according to the first embodiment.

[0019] Figure 11 This is a timing chart showing the relationship between various control signals and the operation timing of the ODT circuit in the memory system according to the first embodiment.

[0020] Figure 12 It is a cross-sectional view of the nonvolatile semiconductor memory device according to the second embodiment.

[0021] Figure 13 This is a block diagram of a memory chip in the nonvolatile semiconductor memory device according to the second embodiment.

[0022] Figure 14 This is a diagram showing the relationship between the control mode of the ODT circuit and the logical states of various control signals in the memory system according to the third embodiment.

[0023] Figure 15 This is a timing chart of various signals during a write operation in the memory system according to the third embodiment.

[0024] Figure 16 This is a timing chart of various signals during a read operation in the memory system according to the third embodiment.

[0025] Figure 17 This is a timing chart showing the relationship between various control signals and the operation timing of the ODT circuit in the memory system according to the third embodiment.

[0026] Figure 18 This is a diagram showing the relationship between the control mode of the ODT circuit and the logical states of various control signals in the memory system according to the fourth embodiment.

[0027] Figure 19 This is a timing chart showing the relationship between various control signals and the operation timing of the ODT circuit in the memory system according to the fourth embodiment.

[0028] Figure 20 This is a table showing the relationship between the operating state and the write protection signal of the nonvolatile semiconductor memory device of the first example of the fifth embodiment.

[0029] Figure 21 This is a diagram showing the relationship between the control mode of the ODT circuit and the logical states of various control signals in the memory system of the second example of the fifth embodiment.

[0030] Figure 22 This is a timing chart of various signals during a write operation in the memory system of the second example of the fifth embodiment.

[0031] Figure 23 This is a timing chart of various signals during a read operation in the memory system of the second example of the fifth embodiment.

[0032] Figure 24 This is a timing chart showing the relationship between various control signals and the operation timing of the ODT circuit in the memory system of the second example of the fifth embodiment.

[0033] Figure 25 This is a diagram showing the relationship between the control mode of the ODT circuit and the logical states of various control signals in the memory system according to the sixth embodiment.

[0034] Figure 26 This is a timing chart from when the ODT circuit in the memory system is turned off to when the state transitions to the write protection state according to the sixth embodiment.

[0035] Figure 27 This is a diagram showing the relationship between the first operation and the second operation in the memory system according to the seventh embodiment.

[0036] Figure 28 This is an explanatory diagram showing an operation target of ODT in the memory system according to the eighth embodiment. DETAILED DESCRIPTION

[0037] Hereinafter, the embodiment will be described with reference to the accompanying drawings. In this description, common reference numerals are given to common parts in all the drawings.

[0038] 1. First Implementation

[0039] A nonvolatile semiconductor memory device and a memory system according to Embodiment 1 will be described. Hereinafter, a NAND flash memory will be described as an example of a nonvolatile semiconductor memory device.

[0040] 1.1 About composition

[0041] 1.1.1 Overall Structure of the Memory System

[0042] First, use Figure 1 The overall configuration of the memory system according to this embodiment will be described.

[0043] like Figure 1 As shown, the memory system 1 includes, for example, a plurality of memories 10 ( 10_0 , 10_1 , 10_2 , . . . ) and one controller 100 .

[0044] Multiple memories 10 are connected to the controller 100 via a NAND bus. The memory 10 is a non-volatile semiconductor memory device, for example, a NAND flash memory. The memory 10 can include multiple memory chips. Here, the memory 10 can use any memory chip, more specifically, for example, all types of NAND flash memory chips can be used. In addition, Figure 1 In the embodiment, three memories 10 are arranged, but the number is not limited to 3 and can be changed as appropriate. In addition, in this embodiment, a NAND flash memory is used as the nonvolatile semiconductor storage device, but the present invention is not limited to this.

[0045] The controller 100 is connected to the host device 200. The controller 100 controls each memory 10 and transmits and receives data, for example, based on a command from the host device 200.

[0046] 1.1.2 About the composition of memory

[0047] Secondly, use Figure 2 and Figure 3 The following describes the configuration of the memory 10. Memory 10_0 will be described below, but other memories 10 (10_1, 10_2, ...) also have the same configuration.

[0048] First, the cross-sectional structure of the memory 10_0 will be described.

[0049] like Figure 2As shown, the memory 10_0 includes a package substrate 40, an interface chip 20, and a plurality of (eg, 8) memory chips 30 (30a-30f). For example, the interface chip 20 and the plurality of memory chips 30 are sealed on the package substrate 40 using a mold resin (not shown).

[0050] The package substrate 40 mounts the interface chip 20 and the memory chip 30. The package substrate 40 supplies, for example, a power supply voltage VCC and a ground voltage VSS to the memory chip 30 and the interface chip 20. The package substrate 40 also transmits data between the controller 100 and the interface chip 20.

[0051] The interface chip 20 transmits data and the like between the package substrate 40 and each memory chip 30 .

[0052] The memory chip 30 stores data from the controller 100 and the like. Figure 2 In FIG. 8 , eight memory chips 30 ( 30 a to 30 f ) are stacked, but the number is not limited to eight and can be changed appropriately.

[0053] Next, the cross-sectional structure of the memory 10_0 will be described in more detail.

[0054] Bumps 41 are provided on the lower surface of a package substrate (semiconductor substrate) 40 . When the nonvolatile semiconductor memory device is a BGA (Ball Grid Array) package, the bumps 41 are solder balls. The package substrate 40 is electrically connected to the controller 100 via the bumps 41 .

[0055] An interface chip (semiconductor chip) 20 is provided on the upper surface of the package substrate 40 .

[0056] Eight memory chips 30 (30a to 30f) are arranged above the upper surface of the interface chip 20 and the package substrate 40. The eight memory chips 30a to 30h are stacked in sequence from the bottom side. Each of the memory chips 30a to 30g, except the top memory chip 30h, is provided with a through electrode (TSV: throughsilicon via) 31 extending from its top surface to its bottom surface. Moreover, between two adjacent memory chips 30, a bump 32 is provided to electrically connect the TSV 31 of each memory chip 30. In addition, the top memory chip 30h may also include TSV 31.

[0057] On the lower surface of the lowermost memory chip 30a, wiring 33 is provided. Bumps 21 are provided between the wiring 33 and the interface chip 20. Bumps 42 are provided between the wiring 33 and the package substrate 40.

[0058] Next, the configurations of the interface chip 20 and the memory chip 30 will be described.

[0059] like Figure 3 As shown, the interface chip 20 and each memory chip 30 are connected via TSVs 31. Furthermore, each memory chip 30 transmits and receives data with the controller via the interface chip 20.

[0060] The memory chip 30 includes a memory cell array 53 for storing data, etc. For example, the memory chip 30 may be a planar NAND flash memory including a memory cell array 53 in which memory cells are two-dimensionally arranged on a semiconductor substrate, or a three-dimensional stacked NAND flash memory including a memory cell array 53 in which memory cells are three-dimensionally arranged above a semiconductor substrate.

[0061] In addition, the structure of the memory cell array 53 in the three-dimensional stacked NAND flash memory is described in, for example, U.S. patent application No. 12 / 407,403, entitled "THREE DIMENSIONAL STACKED NONVOLATILESEMICONDUCTOR MEMORY," filed on March 19, 2009. Furthermore, the present invention is described in U.S. Patent Application No. 12 / 406,524, filed on March 18, 2009, entitled "Three-Dimensional Stacked Nonvolatile Semiconductor Memory," U.S. Patent Application No. 12 / 679,991, filed on March 25, 2010, entitled "Non-Volatile Semiconductor Storage Device and Method of Manufacturing the Same," and U.S. Patent Application No. 12 / 532,030, filed on March 23, 2009, entitled "Semiconductor Memory and Method for Manufacturing the Same." The entire contents of these patent applications are incorporated herein by reference.

[0062] Interface chip 20 includes input / output control circuitry 50, logic circuitry 51, and on-die termination (ODT) control circuitry 52. ​​Interface chip 20 is used to transmit and receive signals containing data with an external device (controller 100) and includes multiple terminals corresponding to 8-bit data lines DQ[7:0], clock signals DQS and DQSn, read enable signals RE and REn, chip enable signal CEn, command latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, write protect signal WPn, and ODT enable signal ODTEN.

[0063] The logic circuit 51 receives various control signals from the controller 100, such as the read enable signals RE and REn, the chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, the write protect signal WPn, and the ODT enable signal ODTEN. The logic circuit 51 is connected to a plurality of terminals corresponding to the plurality of control signals. The logic circuit 51 includes an ODT circuit (not shown) connected to a terminal that receives, for example, the read enable signals RE and REn (details will be described below). The ODT circuit is a circuit that terminates the reflection of signals generated between the controller 100 and the outside (controller 100) during signal input and output. In addition, the logic circuit 51 transmits the received signal to the ODT control circuit 52.

[0064] The chip enable signal CEn is a signal used to enable the memory 10 and is asserted at a low ("L") level. The command latch enable signal CLE is a signal indicating that the input / output signal I / O is a command and is asserted at a high ("H") level. The address latch enable signal ALE is a signal indicating that the input / output signal I / O is an address and is asserted at an "H" level. The write enable signal WEn is a signal used to capture the received signal into the memory 10 and is asserted at an "L" level whenever a command, address, data, etc. is received from the controller 100. Thus, each time WEn is triggered, the signal is captured into the memory 10. The read enable signals RE and REn are signals used to cause the controller 100 to read each data from the memory 10. The read enable signal REn is an inverted signal of the signal RE. For example, the read enable signal REn is asserted at an "L" level. The write protect signal WPn is a signal used to instruct the prohibition of the write operation and is asserted at an "L" level. The ODT enable signal ODTEN is a signal that controls the ON / OFF state of the ODT circuit in the memory 10 and is asserted at an “H” level.

[0065] The input / output control circuit 50 is connected to the terminals corresponding to the data line DQ[7:0] and the clock signals DQS and DQSn. The input / output control circuit 50 includes an ODT circuit connected to the terminals corresponding to the data line DQ[7:0] and the clock signals DQS and DQSn. The input / output control circuit 50 controls the input and output of the 8-bit input / output data signal IO[7:0] and the clock signals DQS and DQSn received and sent between the controller 100 and the memory 10 via the data line DQ[7:0]. The input / output data signal IO[7:0] is an 8-bit data signal that includes various instructions, addresses, data, etc. In addition, the input / output data signal IO is not limited to 8 bits and can be set appropriately. The clock signals DQS and DQSn are clock signals used when inputting and outputting data, and the clock signal DQSn is an inverted signal of the clock signal DQS.

[0066] Hereinafter, unless otherwise specified, various signals are transmitted and received via a signal line (hereinafter referred to as a “common signal line”) that commonly connects the controller 100 and each memory 10 .

[0067] In addition, in this embodiment, for the chip enable signal CEn, the instruction latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, and the ODT enable signal ODTEN, either a common signal line or a signal line that individually connects the controller 100 and each memory 10 (hereinafter referred to as "individual signal line") can be used.

[0068] The ODT control circuit 52 includes a parameter storage unit 54. The ODT control circuit 52 controls the ODT circuits included in the I / O control circuit 50 and the logic circuit 51 based on the parameter settings stored in the parameter storage unit 54 and the ODT enable signal and other signals sent from the logic circuit 51.

[0069] The parameter storage unit 54 stores parameters related to the ODT circuit. In addition, the ODT control circuit 52 may not include a storage area, and may store the parameters in another storage area.

[0070] 1.1.3 About the composition of ODT circuit

[0071] Secondly, use Figure 4 and Figure 5 The configuration of the ODT circuit will be described.

[0072] First, the ODT circuit included in the input / output control circuit 50 will be described.

[0073] like Figure 4As shown, the input / output control circuit 50 includes an ODT circuit 60 , an input receiver 64 , and an output driver 65 for each corresponding terminal.

[0074] The input receiver 64 functions as, for example, a buffer, converting an input signal from the controller 100 into an appropriate voltage level for processing in the memory 10 and transmitting the signal to other circuits in the interface chip 20 and the memory chip 30 .

[0075] The output driver 65 functions as, for example, a buffer, converts a signal transmitted from the memory chip 30 into an appropriate voltage level, and outputs the converted signal to the controller 100 .

[0076] The ODT circuit 60 is provided between the terminal and the input receiver 64. The ODT circuit 60 includes a p-channel MOS (Metal Oxide Semiconductor) transistor 61, an n-channel MOS transistor 62, and variable resistance elements 63a and 63b.

[0077] P-channel MOS transistor 61 has a gate to which signal ODTSn is input, a source to which power supply voltage VCC is applied, and a drain connected to one end of variable resistor 63a. P-channel MOS transistor 61 functions as a first switching element for connecting a voltage line (power supply voltage line) to which power supply voltage VCC is applied and variable resistor 63a.

[0078] The other end of the variable resistor 63a is connected to a wiring connecting a terminal to an input receiver and one end of the variable resistor 63b. The ODT control circuit 52 sets the resistance values ​​of the variable resistors 63a and 63b based on the parameters written when setting the feature.

[0079] N-channel MOS transistor 62 has a gate to which signal ODTS is input, a drain connected to the other end of variable resistor 63b, and a source to which ground voltage VSS is applied. N-channel MOS transistor 62 functions as a second switching element for connecting a voltage line (ground voltage line) to which ground voltage VSS is applied to variable resistor 63b.

[0080] Signals ODTS and ODTSn are signals supplied from the ODT control circuit 52 to control the ODT circuit 60. Signal ODTSn is an inverted signal of signal ODTS. When the ODT control circuit 52 turns on the ODT circuit 60, it sets signal ODTS to an "H" level and signal ODTSn to an "L" level.

[0081] Next, the ODT circuit 60 included in the logic circuit 51 will be described.

[0082] like Figure 5 As shown, the logic circuit 51 is for each corresponding terminal ( Figure 5 The ODT circuit 60 is provided between the terminals corresponding to the read enable signals REn and RE and the input receiver 64.

[0083] Furthermore, the ODT circuit 60 connected to the terminals corresponding to the read enable signals REn and RE may not be provided, and the ODT circuit 60 connected to other terminals may be provided, and any setting can be made.

[0084] 1.2 About the operation of ODT circuit

[0085] Next, the operation of the ODT circuit 60 will be described. The ODT control circuit 52 has two control modes, namely "DIN mode" and "DOUT mode". The ODT control circuit 52 selects the ODT circuit 60 to be turned on according to each control mode. The DIN mode is a mode selected when the controller 100 outputs data when any memory 10 performs a data write operation. On the other hand, the DOUT mode is a mode selected when the target memory 10 outputs data when any memory 10 performs a data read operation. Below, in this embodiment, the following case will be described, that is, in the DIN mode, the ODT circuit 60 corresponding to the data line DQ[7:0] and the clock signals DQS and DQSn is turned on, and in the DOUT mode, the ODT circuit 60 corresponding to the data line DQ[7:0], the clock signals DQS and DQSn, and the read enable signals REn and RE is turned on.

[0086] 1.2.1 About the control flow of ODT circuit

[0087] First, use Figure 6 The control flow of the ODT circuit 60 will be described.

[0088] like Figure 6 As shown, the control of the ODT circuit 60 can be roughly divided into two operations. First, in the first operation, the controller 100 sets the parameters of the ODT circuit 60 (step S1). Hereinafter, the parameter writing operation is referred to as "SetFeature." During SetFeature, various parameters other than those of the ODT circuit 60 are also written.

[0089] More specifically, after power is turned on, the controller 100 executes the Set Feature command in the first action to set various parameters. At this point, the controller 100 sets whether the ODT circuit 60 is used in the interface chip 20 of each memory 10. For example, the controller 100 sets the ODT circuit 60 only in the interface chip 20 of the memory 10 whose signal line (NAND bus) connecting the controller 100 to the memory 10 is the longest, while the interface chips 20 of the other memories 10 do not use the ODT circuit 60. The controller 100 then sets the resistance values ​​of the variable resistor elements 63a and 63b in the DIN mode and DOUT mode, respectively, for the interface chips 20 that use the ODT circuit 60. The ODT control circuit 52 of each interface chip 20 stores parameter information related to whether the ODT circuit 60 can be used and the resistance values ​​of the variable resistor elements 63a and 63b in the parameter storage unit 54.

[0090] Next, in the second operation, the controller 100 sends the ODT enable signal ODTEN. The ODT control circuit 52 of the interface chip 20 of each memory 10 controls the on / off state of the ODT circuit 60 based on the parameter information set in the first operation and the ODT enable signal ODTEN.

[0091] More specifically, first, the controller 100 sets the ODT enable signal ODTEN to the “H” level and transmits it to each memory 10 (step S2 ).

[0092] When the ODT circuit 60 is enabled in step S1 (step S3_Yes), the ODT control circuit 52 of each memory 10 that has received the ODT enable signal selects a control mode for the ODT circuit 60. On the other hand, when the ODT circuit 60 is disabled (step S3_No), the control operation of the ODT circuit 60 after step S3 is omitted.

[0093] When the write operation is executed in any of the memories 10 (step S4_Yes), the ODT control circuit 52 selects the DIN mode.

[0094] Next, the ODT control circuit 52 turns on the ODT circuits 60 corresponding to the data lines DQ[7:0] and the clock signals DQS and DQSn (step S5). More specifically, the ODT control circuit 52 turns on the signal ODTS of the corresponding ODT circuit 60 to an "H" level and the signal ODTSn to an "L" level. This turns on transistors 61 and 62, and the ODT circuit 60 is turned on.

[0095] On the other hand, when no write operation is performed on any memory 10, that is, in the case of a read operation, the ODT control circuit 52 selects the DOUT mode and turns on the ODT circuit 60 corresponding to the data line DQ[7:0], the clock signals DQS and DQSn, and the read enable signals REn and RE (step S6).

[0096] Next, the controller 100 sets the ODT enable signal ODTEN to “L” level, and in response thereto, the ODT control circuit 52 turns off the ODT circuit 60 (step S7 ).

[0097] The controller 100 controls the ODT circuit 60 by repeating the second operation in accordance with the writing and reading operations without changing parameters.

[0098] 1.2.2 About the control mode selection of ODT circuit

[0099] Secondly, use Figure 7 Selection of the control mode of the ODT circuit 60 will be described.

[0100] like Figure 7 As shown, the memory 10 (ODT control circuit 52) ​​latches the read enable signal REn at the timing when the ODT enable signal ODTEN switches from "L" to "H." Then, when the read enable signal REn is at "H," the memory 10 selects the DIN mode and turns on the corresponding ODT circuit 60. On the other hand, when the read enable signal REn is at "L," the memory 10 selects the DOUT mode and turns on the corresponding ODT circuit 60. That is, during a write operation, the controller 100 sets the read enable signal REn to "H" and switches the ODT enable signal ODTEN from "L" to "H." During a read operation, the controller sets the read enable signal REn to "L" and switches the ODT enable signal ODTEN from "L" to "H."

[0101] Furthermore, while the ODT enable signal ODTEN is at the “L” level, the memory 10 turns off the ODT circuit 60 .

[0102] 1.2.3 About Set Feature

[0103] Secondly, use Figure 8 The transmission and reception of signals between the controller 100 and each memory 10 when the Set Feature is executed will be described.

[0104] like Figure 8 As shown, first, the controller 100 asserts the chip enable signal CEn (“L” level).

[0105] Next, the controller 100 issues a command notifying execution of Set Feature, for example, “D5h,” and asserts the command latch enable signal CLE (“H” level).

[0106] Next, the controller 100 issues address data "xxh" and "yyh" and asserts the address latch enable signal ALE ("H" level). For example, address data "xxh" is address data related to the setting of the Set Feature, and "yyh" is address data indicating the corresponding memory 10. The details of the address data and the number of cycles are not particularly limited.

[0107] These instructions and addresses are stored in the corresponding memory 10 each time the write enable signal WEn is triggered.

[0108] Next, the controller 100 transmits clock signals DQS and DQSn and issues data "W-B0" through "W-B3." For example, "W-B0" indicates whether the ODT circuit 60 is usable and the settings of the variable resistor elements 63a and 63b, while data "W-B1" through "W-B3" indicate data related to other parameters. The number of data cycles can be arbitrarily set based on the required parameters.

[0109] The memory 10 starts writing parameters and enters a busy state. During the busy state, the memory 10 sends a ready / busy signal R / Bn to the controller 100 at an "L" level, indicating that the memory 10 is not accepting various signals.

[0110] When the memory 10 completes the write operation, the ready / busy signal R / Bn returns to the "H" level.

[0111] 1.2.4 Regarding the control of the ODT circuit during writing

[0112] Next, regarding the transmission and reception of signals between the controller 100 and each memory 10 during the write operation, the control of the ODT circuit 60 in the non-selected memory 10 is particularly focused on. Figure 9 In Figure 9 In the figure, the command latch enable signal CLE, address latch enable signal ALE, etc. are omitted.

[0113] like Figure 9 As shown, first, the controller 100 asserts the chip enable signal CEn ("L" level). Furthermore, during a write operation, the controller 100 maintains the read enable signal REn at "H" level.

[0114] Next, the controller 100 issues a command, such as "80h," and address data "AD1," "AD2," "AD3," "AD4," and "AD5," notifying the execution of a write operation. For example, the address data "AD1" and "AD2" represent column addresses in the memory chip 30, while the address data "AD3," "AD4," and "AD5" represent row addresses. Whenever the write enable signal WEn is activated in the selected memory 10, the command and address data are stored in the memory 10.

[0115] The number of cycles of the address data is not limited to 5 and can be set arbitrarily. Furthermore, the address data may include an address specifying the memory 10 or a chip address (CADD) specifying the memory chip 30 within the memory 10. Furthermore, the row address may include a block address or a page address. Furthermore, the page address may include information related to, for example, a word line WL, odd / even bit lines (E / O), a string address, or lower-order / middle-order / high-order page (L / M / U).

[0116] The structure of the page address is described, for example, in U.S. Patent Application No. 13 / 784,753, entitled "Nonvolatile Semiconductor Memory Device and Control Method Thereof," filed on March 4, 2013. The entire contents of this patent application are incorporated herein by reference.

[0117] Next, the controller 100 sets the ODT enable signal ODTEN to "H." At this point, in non-selected memories 10 where the ODT circuit 60 can be used, i.e., where the parameters of the ODT circuit 60 have been set using the first action (Set Feature), the read enable signal REn is at "H," so the ODT control circuit 52 selects the DIN mode and turns on the corresponding ODT circuit 60. On the other hand, in non-selected memories 10 where the ODT circuit 60 is not used, i.e., where the parameters of the ODT circuit 60 have not been set using the first action (Set Feature), the ODT control circuit 52 does not turn on the ODT circuit 60 regardless of the ODT enable signal ODTEN.

[0118] Next, the controller 100 transmits the clock signals DQS and DQSn and issues write data “WD”.

[0119] When the write operation in the selected memory 10 is completed, the controller 100 sets the chip enable signal CEn to "H" level and the ODT enable signal ODTEN to "L" level. The non-selected memories 10 that can use the ODT circuit 60 turn off the ODT circuit 60 when the ODT enable signal ODTEN is set to "L" level.

[0120] 1.2.5 Control of the ODT Circuit During Readout

[0121] Next, regarding the transmission and reception of signals between the controller 100 and each memory 10 during the read operation, the control of the ODT circuit 60 in the non-selected memory 10 is particularly focused on. Figure 10 In Figure 10 In the figure, the command latch enable signal CLE, address latch enable signal ALE, etc. are omitted.

[0122] like Figure 10 As shown, the controller 100 asserts the chip enable signal CEn (“L” level).

[0123] Next, the controller 100 sequentially issues a command notifying the execution of a read operation, such as "05h," address data "AD1" to "AD5," and a command to execute the read operation, such as "E0h." Whenever the write enable signal WEn is activated in the selected memory 10, the command and address data are stored in the memory 10.

[0124] Next, the controller 100 sets the read enable signal REn to the "L" level for a certain period. Furthermore, during this period, the controller 100 changes the ODT enable signal ODTEN from the "L" level to the "H" level. At this time, in non-selected memories 10 that can use the ODT circuit 60, since the read enable signal REn is at the "L" level, the ODT control circuit 52 selects the DOUT mode and turns on the corresponding ODT circuit 60. On the other hand, in non-selected memories 10 that do not use the ODT circuit 60, the ODT control circuit 52 does not turn on the ODT circuit 60 regardless of the ODT enable signal ODTEN.

[0125] Next, a read operation is performed on the selected memory 10, and read data "RD" and clock signals DQS and DQSn are output in response to the activation of read enable signals REn and RE.

[0126] When the read operation in the selected memory 10 is completed, the controller 100 sets the chip enable signal CEn to "H" level and the ODT enable signal ODTEN to "L" level. The non-selected memories 10 that can use the ODT circuit 60 turn off the ODT circuit 60 when the ODT enable signal ODTEN is set to "L" level.

[0127] 1.2.6 About the operation timing of the ODT circuit

[0128] Secondly, use Figure 11 The timing of switching the ODT enable signal ODTEN and the ODT circuit 60 between on and off will be described.

[0129] like Figure 11 As shown, the memory 10 is set in such a manner that, after the write enable signal WEn switches from "L" to "H" level, various signals including the read enable signal REn are not accepted during a predetermined period. Alternatively, the controller 100 can also be set in such a manner that various signals are not spontaneously issued during this period. Hereinafter, the predetermined period, that is, the standby period from the time when the write enable signal WEn switches from "L" to "H" level to the time when the read enable signal REn can be accepted, is referred to as "tWHR". For example, in a write operation, after inputting the address data "AD5" ( Figure 9 ) Set the standby period tWHR. In the read operation, after inputting the command "30h" ( Figure 10 ) sets the standby period tWHR.

[0130] After the standby period tWHR has elapsed, the memory 10 receives the read enable signal REn (read enable signal REn becomes active). For a period of at least 25 nsec after the end of the standby period tWHR, the controller 100 maintains the read enable signal REn at an "H" level during a write operation and at an "L" level during a read operation (hereinafter referred to as the "REn maintain period"). The controller 100 switches the ODT enable signal ODTEN from "L" to "H" level after a period of at least 5 nsec from the start of the REn maintain period (i.e., the end of the standby period tWHR) until the end of the REn maintain period (e.g., a period of 20 nsec). In other words, the controller 100 can switch the ODT enable signal ODTEN asynchronously with other signals as long as at least 5 nsec has passed since the start of the REn maintain period.

[0131] At the timing when the ODT enable signal ODTEN switches from "L" to "H," the ODT control circuit 52 latches the read enable signal REn and selects the control mode of the ODT circuit 60. Furthermore, the ODT control circuit 52 turns on the corresponding ODT circuit 60, for example, 25 nsec after the ODT enable signal ODTEN switches from "L" to "H." Furthermore, the ODT control circuit 52 turns off the corresponding ODT circuit 60, for example, 25 nsec after the ODT enable signal ODTEN switches from "H" to "L."

[0132] 1.3 Effects of this Implementation

[0133] The configuration of this embodiment can improve processing capacity. This effect will be described below.

[0134] In a memory system 1 in which a controller 100 and multiple memories 10 are commonly connected via a bus, reflections of signals from non-selected memories 10 are transmitted to the selected memory 10 or the controller 100, which is the input destination of the signal. Therefore, this reflected signal becomes interference in the input signal. Therefore, a method of suppressing signal reflection using an ODT circuit 60 is known.

[0135] For example, there is a method in which, when the non-selected memory 10 controls the on / off operation of the ODT circuit 60, a command (and address data) notifying the non-selected memory 10 of the start and end of use of the ODT circuit 60 is sent before and after a write or read operation. However, in this case, since notification to the non-selected memory 10 is required separately from the write or read operation, the processing time of the write and read operation is increased, and the processing capacity of the memory system 1 is reduced.

[0136] Furthermore, the states of signals sent and received between the controller 100 and the selected memory 10 differ between write and read operations. More specifically, for example, during read operations, data is read in response to the activation of the read enable signal REn. In contrast, during write operations, the read enable signal REn remains at an "H" level. Therefore, the ODT circuit 60 corresponding to the read enable signal REn is preferably used during read operations rather than during write operations. Thus, the on / off state of the ODT circuit 60 must be controlled according to the operating state of the memory system.

[0137] In contrast, in the configuration of this embodiment, the controller 100 can issue a signal (ODT enable signal ODTEN) for controlling the ODT circuit 60. Furthermore, the controller 100 can send the ODT enable signal ODTEN to each memory device 10 during write and read operations. Furthermore, each memory device 10 can control the ODT circuit 60 based on the ODT enable signal ODTEN. This allows the controller 100 to omit notifications regarding the ODT circuit 60 to non-selected memories 10 before and after write or read operations. This shortens the processing time for write and read operations, thereby improving the processing capacity of the memory system.

[0138] Furthermore, in the configuration of this embodiment, the ODT control mode can be switched according to the read enable signal REn. More specifically, when the ODT enable signal ODTEN switches from "L" to "H" level, the memory 10 can select the DIN mode when the read enable signal REn is at "H" level, and can select the DOUT mode when the read enable signal REn is at "L" level. As a result, the memory 10 can select the optimal control state of the ODT circuit 60 during write and read operations. This effectively reduces interference caused by signal reflection, thereby improving signal quality. Therefore, it is possible to suppress malfunctions caused by signal degradation, thereby improving the reliability of the memory system.

[0139] 2. Second Implementation

[0140] Next, the second embodiment will be described. The difference from the first embodiment lies in the configuration of the memory 10 and the inclusion of an ODT circuit in each memory chip. Only the differences from the first embodiment will be described below.

[0141] 2.1 About the composition of memory

[0142] use Figure 12 and Figure 13 The configuration of the memory 10 of this embodiment will be described. Memory 10_0 will be described below, but the other memories 10 (10_1, 10_2, ...) also have the same configuration.

[0143] First, the cross-sectional structure of the memory 10 will be described.

[0144] like Figure 12 As shown, the memory 10_0 includes a package substrate 40 and eight memory chips 70 (70a to 70h). For example, the plurality of memory chips 70 are sealed on the package substrate 40 by a mold resin (not shown). In addition, the memory 10_0 in this embodiment does not utilize the first embodiment. Figure 2 and Figure 3 The interface chip 20 is illustrated.

[0145] The memory chip 70 is used in conjunction with the first embodiment. Figure 2 and Figure 3 The memory chip 30 described above similarly stores data from the controller 100. Furthermore, although eight memory chips 70 (70a-60f) are stacked, this number is not limited to eight and can be modified as appropriate. Each memory chip 70 has multiple terminals 71 on its top surface for transmitting and receiving signals to and from the outside (controller 100, etc.).

[0146] Memory chips 70a to 70h are stacked sequentially from the bottom on the upper surface of package substrate 40 with their centers offset, for example, in a stepwise manner, with terminals 71 exposed. Terminals 71 of each memory chip 70 are electrically connected to package substrate 40 using, for example, gold wiring.

[0147] Next, the configuration of the memory chip 70 will be described. Memory chip 70a will be described below, but the other memory chips 70b to 70h also have the same configuration.

[0148] like Figure 13 As shown, the memory chip 70a includes the first embodiment of the utilization Figure 3 The interface chip 20 includes an input / output control circuit 50, a logic circuit 51, and an ODT control circuit 52, and the memory cell array 53 included in the memory chip 30. Furthermore, the memory chip 70a includes terminals corresponding to the read enable signals RE and REn, the chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, the write protect signal WPn, and the ODT enable signal ODTEN. Thus, similar to the first embodiment, the input / output control circuit 50 of the memory chip 70a includes an ODT circuit 60 connected to terminals corresponding to the data lines DQ[7:0] and the clock signals DQS and DQSn, and the logic circuit 51 includes an ODT circuit 60 connected to terminals corresponding to the read enable signals REn and REn.

[0149] 2.2 About the operation of ODT circuit

[0150] Next, the operation of the ODT circuit 60 included in each memory chip 70 will be described. The control flow of the ODT circuit 60 is the same as that of the first embodiment. Figure 6 However, in the first operation, when the controller 100 executes Set Feature, the parameters related to the ODT circuit 60 are set for each memory 10 (interface chip 20) in the first embodiment. In contrast, in this embodiment, the parameters related to the ODT circuit 60 are set for each memory chip 70. Furthermore, in the second operation, the ODT control circuit 52 of each memory chip 70 controls the operation of the ODT circuit 60 based on signals transmitted to and from the controller 100.

[0151] 2.3 Effects of this Implementation

[0152] According to the configuration of this embodiment, the same effects as those of the first embodiment can be obtained.

[0153] Furthermore, in the configuration of this embodiment, each memory chip 70 includes an ODT circuit 60. Therefore, the ODT circuit 60 can be configured for each memory chip 70. This allows the memory system 1 to make more detailed settings for suppressing reflected signals. This effectively reduces interference caused by signal reflections, thereby improving signal quality.

[0154] 3. Third Implementation Method

[0155] Next, the third embodiment will be described. The difference from the first and second embodiments is that the chip enable signal CEn is also used to determine the control mode of the ODT circuit 60. Only the differences from the first and second embodiments will be described below.

[0156] 3.1 The overall structure of the memory system

[0157] First, the overall structure of the memory system 1 will be described. In the memory system 1 of this embodiment, the controller 100 and each memory device 10 (10_0, 10_1, 10_2, ...) are connected via separate signal lines regarding the chip enable signal CEn. In other words, the controller 100 can use separate signal lines to send a different chip enable signal CEn to each memory device 10. Hereinafter, the case where the controller 100 sends the chip enable signal CEn using separate signal lines, i.e., the case where multiple chip enable signals CEn are displayed, is referred to as the chip enable signal "CEnx."

[0158] Furthermore, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, and the ODT enable signal ODTEN may use a common signal line or individual signal lines.

[0159] 3.2 About the control mode selection of ODT circuit

[0160] First, use Figure 14 Selection of the control mode of the ODT circuit 60 will be described.

[0161] like Figure 14As shown, in this embodiment, the ODT control circuit 52 latches the chip enable signal CEnx and the read enable signal REn at the timing when the ODT enable signal ODTEN switches from the "L" level to the "H" level. Then, when the chip enable signal CEnx and the read enable signal REn are both at the "H" level, the ODT control circuit 52 selects the DIN mode and turns on the corresponding ODT circuit 60. In addition, when the chip enable signal CEnx is at the "H" level and the read enable signal REn is at the "L" level, the ODT control circuit 52 selects the DOUT mode and turns on the corresponding ODT circuit 60. In addition, when the chip enable signal CEnx is at the "L" level, the ODT control circuit 52 turns off the ODT circuit 60 regardless of the read enable signal REn.

[0162] Furthermore, while the ODT enable signal ODTEN is at “L” level, the ODT control circuit 52 turns off the ODT circuit 60 .

[0163] 3.3 Control of the ODT Circuit During Write Operation

[0164] Secondly, use Figure 15 The transmission and reception of signals between the controller 100 and each memory 10 during a write operation will be described.

[0165] like Figure 15 As shown, first, the controller 100 asserts the chip enable signal CEnx ("L" level) in the selected memory 10. Furthermore, the controller 100 maintains the chip enable signal CEnx in the non-selected memory 10 at "H" level during the write operation.

[0166] Next, after issuing the command and address data required for the write operation, the controller 100 sets the ODT enable signal ODTEN to "H." At this point, in the non-selected memories 10 where the ODT circuits 60 can be used, the chip enable signal CEnx and the read enable signal REn are both "H." Therefore, the ODT control circuit 52 selects the DIN mode and turns on the corresponding ODT circuits 60.

[0167] When the write operation in the selected memory 10 is completed, the controller 100 sets the chip enable signal CEn of the selected memory 10 to "H" level and the ODT enable signal ODTEN to "L" level. The non-selected memories 10 that can use the ODT circuit 60 turn off the ODT circuit 60 when the ODT enable signal ODTEN is set to "L" level.

[0168] 3.4 Control of the ODT Circuit During Readout Operation

[0169] Secondly, use Figure 16The transmission and reception of signals between the controller 100 and each memory 10 during the read operation will be described.

[0170] like Figure 16 As shown, first, the controller 100 asserts the chip enable signal CEnx ("L" level) in the selected memory 10. Furthermore, the controller 100 maintains the chip enable signal CEnx in the non-selected memory at "H" level during the read period.

[0171] Next, after issuing the command and address data required for the read operation, the controller 100 sets the read enable signal REn to "L" level during the REn hold period. Furthermore, during this period, the controller 100 sets the ODT enable signal ODTEN to "H" level. In non-selected memories 10 capable of using the ODT circuit 60, since the chip enable signal CEnx is at "H" level and the read enable signal REn is at "L" level, the ODT control circuit 52 selects the DOUT mode and turns on the corresponding ODT circuit 60.

[0172] When the read operation in the selected memory 10 is completed, the controller 100 sets the chip enable signal CEnx of the selected memory 10 to "H" level and the ODT enable signal ODTEN to "L" level. The non-selected memories 10 that can use the ODT circuit 60 turn off the ODT circuit 60 when the ODT enable signal ODTEN is set to "L" level.

[0173] 3.5 About the operation timing of the ODT circuit

[0174] Secondly, use Figure 17 The timing of switching the ODT enable signal ODTEN and the ODT circuit 60 between on and off will be described.

[0175] like Figure 17 As shown, after a standby period tWHR, for example, with the chip enable signal CEnx in an active state (a state in which the memory 10 can receive various signals), the controller 100 sets the chip enable signal CEnx of the non-selected memory 10 to an "H" level. Thereafter (for example, after 10 nsec), the controller 100 maintains the read enable signal REn at an "H" level during a write operation. On the other hand, during a read operation, the controller 100 sets the read enable signal REn to an "L" level and maintains the "L" level for the REn maintenance period (25 nsec or longer).

[0176] In addition, the controller 100 switches the ODT enable signal ODTEN from "L" to "H" level after 5 nsec or more from the start of the REn sustain period (i.e., the end of the standby period tWHR) until the end of the REn sustain period. Figure 17 In the example, 10 nsec after the chip enable signal CEnx becomes active enters the REn sustain period, and 5 nsec after that (15 nsec after the chip enable signal CEnx becomes active), the ODT enable signal ODTEN is set to "H" level.

[0177] The ODT control circuit 52 latches the chip enable signal CEnx and the read enable signal REn at the timing when the ODT enable signal ODTEN switches from "L" to "H" level, selects the control mode of the ODT circuit 60, and turns on the corresponding ODT circuit 60 after, for example, 25 nsec.

[0178] 3.6 Effects of this Implementation

[0179] This embodiment can be applied to the first and second embodiments. Therefore, the same effects as those of the first and second embodiments can be obtained.

[0180] In addition, in the configuration of this embodiment, the controller 100 sends a different chip enable signal CEnx to each memory 10. Moreover, the ODT control circuit 52 can select the control mode of the ODT circuit 60 based on the chip enable signal CEnx and the read enable signal REn. Therefore, the ODT control circuit 52 can operate the ODT circuit 60 only when the corresponding memory 10 (or memory chip 70) is in a non-selected state (the chip enable signal CEnx is at the "H" level). In other words, the memory system 1 can better control the ODT circuit 60 according to the selected memory 10. As a result, the interference caused by signal reflection can be more effectively reduced, thereby improving the signal quality.

[0181] 4. Fourth Implementation Method

[0182] Next, the fourth embodiment will be described. The fourth embodiment differs from the third embodiment in that the ODT circuit 60 is turned on when the ODT enable signal ODTEN and the chip enable signal CEnx are at "H" level. Only the differences from the third embodiment will be described below.

[0183] 4.1 About the control mode selection of ODT circuit

[0184] First, use Figure 18 Selection of the control mode of the ODT circuit 60 will be described.

[0185] like Figure 18As shown, when both the chip enable signal CEnx and the ODT enable signal ODTEN are at an "H" level, if the read enable signal REn is at an "H" level, the ODT control circuit 52 selects the DIN mode and turns on the corresponding ODT circuit 60. On the other hand, if the read enable signal REn is at an "L" level, the ODT control circuit 52 selects the DOUT mode and turns on the corresponding ODT circuit 60. The ODT control circuit 52 latches the read enable signal REn when the ODT circuit 60 is turned on. Therefore, even if the read enable signal REn changes from an "H" level to an "L" level or from an "L" level to an "H" level while the ODT circuit 60 is turned on, the ODT control circuit 52 maintains the DIN mode or the DOUT mode until it turns off the ODT circuit 60.

[0186] Furthermore, when at least one of the chip enable signal CEnx and the ODT enable signal ODTEN is at “L” level, the ODT control circuit 52 turns off the ODT circuit 60 regardless of the read enable signal REn.

[0187] 4.2 About the operation timing of the ODT circuit

[0188] Secondly, use Figure 19 The timing of switching the ODT enable signal ODTEN and the ODT circuit 60 on / off will be described. Figure 19 In the example, a case will be described in which the chip enable signal CEnx of the non-selected memory 10 is maintained at the “H” level while the ODT enable signal ODTEN is at the “H” level.

[0189] like Figure 19 As shown in FIG. 2 , similarly to the third embodiment, when the chip enable signal CEnx is in the active state (the memory 10 is able to receive various signals), the controller 100 sets the chip enable signal CEnx of the non-selected memory 10 to the "H" level. Thereafter, the controller 100 switches the ODT enable signal from the "L" level to the "H" level after a period of 5 nsec or more has passed since the start of the REn sustain period and until the end of the REn sustain period.

[0190] When both the chip enable signal CEnx and the ODT enable signal ODTEN are at the "H" level, the ODT control circuit 52 latches the read enable signal REn and selects the control mode for the ODT circuit 60. Furthermore, after, for example, 25 nsec after the ODT enable signal ODTEN switches from the "L" level to the "H" level, the ODT control circuit 52 turns on the corresponding ODT circuit 60.

[0191] Next, the controller 100 switches the ODT enable signal ODTEN from "H" to "L." Furthermore, the controller 100 maintains the chip enable signal CEnx at "H" until, for example, 15 nsec or more has passed since the ODT enable signal ODTEN was switched from "H" to "L." The ODT control circuit 52 disconnects the corresponding ODT circuit 60, for example, 25 nsec after the ODT enable signal ODTEN is switched from "H" to "L."

[0192] In addition, the controller 100 may switch the ODT enable signal ODTEN from "L" to "H" before the chip enable signal CEnx becomes active. Furthermore, the controller 100 may switch the chip enable signal CEnx from "H" to "L" before the ODT enable signal ODTEN.

[0193] 4.3 Effects of this Implementation

[0194] This embodiment can be applied to the first and second embodiments, and therefore, the same effects as those of the first and second embodiments can be obtained.

[0195] In addition, with the configuration of this embodiment, the same effects as those of the third embodiment can be obtained.

[0196] Furthermore, in the configuration of this embodiment, the ODT control circuit 52 can turn on the ODT circuit 60 when both the chip enable signal CEnx and the ODT enable signal ODTEN are at the “H” level.

[0197] 5. Fifth Implementation Method

[0198] Next, the fifth embodiment will be described. This embodiment differs from the first to fourth embodiments in that the write-protect signal WPn functions as both a write-protect control signal and a control signal for the ODT circuit 60. This embodiment will describe two examples. The following describes only the differences from the first to fourth embodiments.

[0199] 5.1 Example 1

[0200] First, a first example of this embodiment will be described. In this example, the effect of a signal input from a terminal differs before and after setting a parameter using Set Feature.

[0201] 5.1.1 Overall Structure of the Memory System

[0202] The overall structure of the memory system 1 is described. In the memory system 1 of this embodiment, the controller 100 uses individual signal lines to send different write protection signals WPn to each memory 10 (10_0, 10_1, 10_2, ...). Hereinafter, the write protection signal sent by the controller 100 to each memory 10 is referred to as the write protection signal "WPnx", and the terminal of each memory 10 corresponding to the write protection signal WPnx is referred to as the "WPnx terminal". Therefore, in this embodiment, the following structure is formed, that is, in the first embodiment Figure 3 and Figure 5 Or the second embodiment Figure 13 In the embodiment, the write protection signal WPn is renamed as WPnx, and the terminal corresponding to the ODT enable signal ODTEN is abolished.

[0203] Furthermore, the chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal WEn may use either a common signal line or individual signal lines.

[0204] 5.1.2 Signals of the WPnx Terminal

[0205] First, use Figure 20 The relationship between the signal of the WPnx terminal and the memory 10 will be described.

[0206] like Figure 20 As shown, the signal of the WPnx terminal (write protection signal WPnx) functions as a write protection control signal before the parameters related to the ODT circuit 60 are set by Set Feature (before the first action), and functions as a control signal of the ODT circuit 60 (ODT enable signal ODTEN) after the parameters are set.

[0207] More specifically, when the memory 10 is started (powered on), the controller 100 sets the write-protect signal WPnx to an "L" level to prevent write operations when the power supply voltage is unstable. The write-protect signal WPnx is then processed as a write-protect control signal. While the write-protect signal WPnx is at an "L" level, the memory 10 prohibits write operations (enabling write protection).

[0208] After the power supply voltage is established (stable), the controller 100 sets the write protection signal WPnx to "H" level. The write protection signal WPnx at this time is processed as a write protection control signal, and the memory 10 releases the prohibition of the write operation.

[0209] Next, the controller 100 executes the Set Feature command to set parameters related to the ODT circuit 60. After setting the parameters (executing the Set Feature command), the memory 10 processes the write-protect signal WPnx as the ODT enable signal ODTEN. More specifically, when the write-protect signal WPnx is at an "L" level, the ODT control circuit 52 controls the ODT circuit 60 to be turned on. On the other hand, when the write-protect signal WPnx is at an "H" level, the ODT control circuit 52 controls the ODT circuit 60 to be turned off.

[0210] 5.1.3 About the control mode selection of ODT circuit

[0211] Regarding the control mode of the ODT circuit 60 in this example, the control modes described in the first, third, and fourth embodiments can be applied. Figure 7 、 Figure 14 ,and Figure 18 In this case, it is sufficient to replace the ODT enable signal ODTEN with the write protection signal WPnx.

[0212] 5.2 Case 2

[0213] Next, the second example of this embodiment will be described. In the second example, after executing SetFeature in the first example, the write protect signal WPnx also functions as a write protect control signal. Only the differences from the first example will be described below.

[0214] 5.2.1 Overall Structure of the Memory System

[0215] The overall structure of the memory system 1 will be described. In the memory system 1 of this example, the controller 100 sends different write protection signals WPnx and chip enable signals CEnx to each memory 10 (10_0, 10_1, 10_2, ...) using separate signal lines.

[0216] In addition, the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal WEn may use a common signal line or individual signal lines.

[0217] 5.2.2 About the control mode selection of ODT circuit

[0218] First, use Figure 21 Selection of the control mode of the ODT circuit 60 will be described.

[0219] like Figure 21As shown, the ODT control circuit 52 latches the chip enable signal CEnx (for each memory 10), the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, and the read enable signal REn at the timing when the write protect signal WPnx switches from "H" to "L." Furthermore, when the chip enable signal CEnx and the write enable signal WEn are at an "H" level and the command latch enable signal CLE and the address latch enable signal ALE are at an "L" level, the ODT control circuit 52 determines the write protect signal WPnx as the control signal for the ODT circuit 60. Then, when the read enable signal REn is at an "H" level, the ODT control circuit 52 selects the DIN mode and turns on the corresponding ODT circuit 60. On the other hand, when the read enable signal REn is at an "L" level, the ODT control circuit 52 selects the DOUT mode and turns on the corresponding ODT circuit 60.

[0220] When the chip enable signal CEnx, command latch enable signal CLE, address latch enable signal ALE, and write enable signal WEn are not in the above combinations, the ODT control circuit 52 turns off the ODT circuit 60. The memory 10 determines that the write protect signal WPnx is a write protect control signal and prohibits write operations.

[0221] Furthermore, while the write protect signal WPnx is at the “H” level, the ODT control circuit 52 turns off the ODT circuit 60 .

[0222] 5.2.3 Control of the ODT Circuit During Write Operation

[0223] Secondly, use Figure 22 The transmission and reception of signals between the controller 100 and each memory 10 during a write operation will be described. Figure 22 In the example, a case where the command latch enable signal CLEx, the address latch enable signal ALEx, and the write enable signal WEnx are different for each memory 10 will be described.

[0224] like Figure 22 As shown, during the write operation, the controller 100 maintains the chip enable signal CEnx and the write enable signal WEnx in the non-selected memory 10 at the "H" level, and maintains the command latch enable signal CLEx and the address latch enable signal ALEx at the "L" level.

[0225] After issuing the command and address data required for a write operation, the controller 100 sets the write protect signal WPnx to an "L" level. At this point, in the non-selected memories 10 where the ODT circuits 60 can be used, the chip enable signal CEnx, the write enable signal WEn, and the read enable signal REn are set to "H" levels, and the command latch enable signal CLE and the address latch enable signal ALE are set to "L". Therefore, the ODT control circuit 52 selects the DIN mode and turns on the corresponding ODT circuits 60.

[0226] When the write operation in the selected memory 10 is completed, the controller 100 sets the chip enable signal CEn of the selected memory 10 to "H" level and sets the write protection signal WPnx to "H" level. In the non-selected memories 10 where the ODT circuit 60 can be used, if the write protection signal WPnx is set to "H", the ODT control circuit 52 turns off the ODT circuit 60.

[0227] 5.2.4 Control of the ODT Circuit During Readout

[0228] Secondly, use Figure 23 The transmission and reception of signals between the controller 100 and each memory 10 during the read operation will be described. Figure 23 In the example, Figure 22 Similarly, a description will be given of a case where the command latch enable signal CLEx, the address latch enable signal ALEx, and the write enable signal WEnx are different for each memory 10 .

[0229] like Figure 23 As shown, during the read operation, the controller 100 maintains the chip enable signal CEnx and the write enable signal WEnx in the non-selected memory 10 at "H" level, and maintains the command latch enable signal CLEx and the address latch enable signal ALEx at "L" level.

[0230] After issuing the command and address data required for a read operation, the controller 100 sets the read enable signal REn to an "L" level during the REn hold period. Furthermore, the controller 100 sets the write protect signal WPnx to an "L" level during this period. In non-selected memories 10 capable of using the ODT circuit 60, since the chip enable signal CEnx and the write enable signal WEn are set to "H" levels, and the command latch enable signal CLE, the address latch enable signal ALE, and the read enable signal REn are set to "L" levels, the ODT control circuit 52 selects the DOUT mode and turns on the corresponding ODT circuit 60.

[0231] When the read operation in the selected memory 10 is completed, the controller 100 sets the chip enable signal CEnx of the selected memory 10 to "H" level and sets the write protect signal WPnx to "H" level. In non-selected memories 10 where the ODT circuit 60 can be used, if the write protect signal WPnx is set to "H", the ODT control circuit 52 turns off the ODT circuit 60.

[0232] 5.2.5 About the operation timing of the ODT circuit

[0233] Secondly, use Figure 24 The timing of switching between ON and OFF of the write protect signal WPnx and the ODT circuit 60 will be described.

[0234] like Figure 24 As shown, after the standby period tWHR, for example, with various signals active (memory 10 is able to receive various signals), controller 100 sets chip enable signal CEnx, write enable signal WEnx, and read enable signal REn of non-selected memory 10 to "H" level, and sets command latch enable signal CLEx and address latch enable signal ALEx to "L" level. Then, after a period of 5 nsec or more from the start of the REn maintenance period until the end of the REn maintenance period, controller 100 switches write protect signal WPnx from "H" to "L".

[0235] The ODT control circuit 52 latches the chip enable signal CEnx, the command latch enable signal CLEx, the address latch enable signal ALEx, the write enable signal WEnx, and the read enable signal REn at the timing when the write protection signal WPnx switches to the "H" level. Figure 24 In the example shown, since chip enable signal CEnx and write enable signal WEnx are set to "H" level, and command latch enable signal CLEx and address latch enable signal ALEx are set to "L" level, ODT control circuit 52 processes write protect signal WPnx as a control signal for ODT circuit 60 and selects the DIN / DOUT mode based on the "H" / "L" level of read enable signal REn. Then, after the signal at the WPnx terminal switches from "H" to "L" level, for example, 25 nsec later, the corresponding ODT circuit 60 is turned on.

[0236] Next, the controller 100 switches the write protect signal WPnx from “L” to “H” level. The ODT control circuit 52 turns off the corresponding ODT circuit 60 after, for example, 25 nsec has passed since the write protect signal WPnx switched from “L” to “H” level.

[0237] 5.3 Effects of this Implementation

[0238] With the configuration of this embodiment, the same effects as those of the first to fourth embodiments can be obtained.

[0239] Furthermore, in this embodiment, the write-protect signal WPnx can function as both a write-protect control signal and a control signal for the ODT circuit 60. In other words, the write-protect signal WPn can be shared with the ODT enable signal ODTEN. This eliminates the need for terminals corresponding to the ODT enable signal ODTEN and data lines for transmitting and receiving the ODT enable signal ODTEN in the controller 100 and the memory 10. This minimizes increases in the number of terminals and data lines in the memory system, thereby reducing chip area.

[0240] Furthermore, in this embodiment, after the parameters of the ODT circuit 60 are set using Set Feature, a single signal is also configured to function as both a write protection control signal and a control signal for the ODT circuit 60. More specifically, the memory 10 latches the chip enable signal CEnx, the instruction latch enable signal CLEx, the address latch enable signal ALEx, the write enable signal WEnx, and the read enable signal REn at the timing when the write protection signal WPnx switches from the "H" level to the "L" level. Furthermore, the memory 10 can determine whether the write protection signal WPnx is a write protection control signal or a control signal for the ODT circuit 60 based on the state of each signal. By using the chip enable signal CEnx, the instruction latch enable signal CLEx, the address latch enable signal ALEx, the write enable signal WEnx, and the read enable signal REn for determination, malfunction of the write protection or ODT circuit 60 can be prevented. This can improve the reliability of the memory system.

[0241] In addition, in this embodiment, the chip enable signal CEnx, the instruction latch enable signal CLEx, the address latch enable signal ALEx, and the write enable signal WEnx are used to determine whether the signal at the WPnx terminal is the write protection signal WPnx or the ODT enable signal ODTENx, but the type of signal used for determination and the combination of the logic levels of the signal are not limited to this.

[0242] Furthermore, the write protect signal WPnx is made to function as the ODT enable signal ODTEN, but the function is not limited to the write protect signal WPnx.

[0243] 6. Sixth Implementation Method

[0244] Next, the sixth embodiment will be described. This sixth embodiment relates to a case where the chip enable signal CEnx, command latch enable signal CLEx, address latch enable signal ALEx, and write enable signal WEnx are not latched as in the second example of the fifth embodiment. Below, only the differences from the second example of the fifth embodiment will be described.

[0245] 6.1 The overall structure of the memory system

[0246] First, the overall configuration of the memory system 1 will be described. In the memory system 1 of this embodiment, the write protect signal WPnx, the command latch enable signal CLEx, the address latch enable signal ALEx, and the write enable signal WEnx are transmitted from the controller 100 to each memory 10 using separate signal lines.

[0247] 6.2 About the control mode selection of ODT circuit

[0248] Secondly, use Figure 25 Selection of the control mode of the ODT circuit 60 will be described.

[0249] like Figure 25 As shown, when the chip enable signal CEnx and the write enable signal WEnx are at "H" level, and the command latch enable signal CLEx, the address latch enable signal ALEx, and the write protect signal WPnx are at "L" level, if the read enable signal REn is at "H" level, the ODT control circuit 52 selects the DIN mode and turns on the ODT circuit 60. On the other hand, if the read enable signal REn is at "L" level, the ODT control circuit 52 selects the DOUT mode and turns on the ODT circuit 60. The ODT control circuit 52 latches the read enable signal REn when the ODT circuit 60 is turned on. Therefore, even if the read enable signal REn changes from "H" to "L" level or from "L" to "H" level while the ODT circuit 60 is turned on, the ODT control circuit 52 maintains the DIN mode or DOUT mode until the ODT circuit 60 is turned off.

[0250] Furthermore, when at least one of the chip enable signal CEnx, the command latch enable signal CLEx, the address latch enable signal ALEx, and the write enable signal WEnx is not at the aforementioned logic level, and when the write protect signal WPnx is at an "L" level, the ODT control circuit 52 turns off the ODT circuit 60. The memory 10 then enters the write-protected state, and writing is prohibited. Therefore, when the logic level of at least one of the chip enable signal CEnx, the command latch enable signal CLEx, the address latch enable signal ALEx, and the write enable signal WEnx is inverted while the ODT circuit 60 is on, the memory 10 also turns off the ODT circuit 60 and enters the write-protected state.

[0251] When the write protection signal WPnx is at “H” level, the ODT control circuit 52 turns off the ODT circuit 60 .

[0252] 6.3 Transition from the ODT Circuit Control State to the Write Protect State

[0253] Secondly, use Figure 26 The timing of transition from the control state of the ODT circuit 60 to the write protection state will be described.

[0254] like Figure 26 As shown, when the chip enable signal CEnx and the write enable signal WEnx are at the "H" level and the instruction latch enable signal CLEx and the address latch enable signal ALEx are at the "L" level, if the write protection signal WPnx changes from the "H" level to the "L" level, the ODT control circuit 52 turns on the ODT circuit 60.

[0255] In this state, if the write enable signal WEnx changes from "H" to "L", for example, the ODT control circuit 52 turns off the ODT circuit 60. Then, the memory 10 transitions to the write protection state after, for example, 100 nsec after the ODT circuit is turned off.

[0256] In addition, Figure 26 In the example, the write enable signal WEnx is switched from "H" to "L" level, but the logic level of any one of the chip enable signal CEnx, the command latch enable signal CLEx, and the address latch enable signal ALEx may be switched.

[0257] 6.3 Effects of this Implementation

[0258] With the configuration of this embodiment, the same effects as those of the first to fifth embodiments can be obtained.

[0259] Furthermore, in this embodiment, by changing the logic level of any one of the chip enable signal CEnx, the instruction latch enable signal CLEx, the address latch enable signal ALEx, and the write enable signal WEnx when the ODT circuit 60 is connected, the disconnection action of the ODT circuit 60 and the transition to the write protection state can be continuously performed.

[0260] 7. Seventh Implementation Method

[0261] Next, the seventh embodiment will be described. The difference from the first to sixth embodiments is that, during SetFeature, the control mode of the ODT circuit 60 is set to either the DIN mode or the DOUT mode. Only the differences from the first to sixth embodiments will be described below.

[0262] 7.1 About the Control Process of ODT Circuit

[0263] use Figure 27 The control flow of the ODT circuit 60 will be described.

[0264] like Figure 27 As shown, first, when executing Set Feature (first action), the controller 100 selects either the DIN mode or the DOUT mode and sets parameters.

[0265] Next, the controller 100 sets the ODT enable signal ODTEN from "L" to "H" during a write or read operation. While the ODT enable signal ODTEN is at "H", the ODT control circuit 52 turns on the corresponding ODT circuit 60 in the DIN mode or DOUT mode preset by the Set Feature.

[0266] 7.2 Effects of this Implementation

[0267] According to the configuration of this embodiment, the same effects as those of the first to sixth embodiments can be obtained.

[0268] Furthermore, in this embodiment, by presetting either the DIN mode or the DOUT mode using the Set Feature, the ODT control circuit 52 can control the operation of the ODT circuit 60 without selecting the control mode of the ODT circuit 60. This simplifies the configuration of the ODT control circuit 52 and reduces its circuit area. Consequently, an increase in chip area can be suppressed.

[0269] 8. 8th Implementation Method

[0270] Next, the eighth embodiment will be described. The eighth embodiment selects memory chips 70a to 70h for turning on the ODT circuit 60 based on chip address data CADD in the second embodiment. Only the differences from the second embodiment will be described below.

[0271] 8.1 Selection of Memory Chips

[0272] use Figure 28 The selection of the memory chips 70a to 70h will be briefly described. Figure 28 This simply represents the second embodiment. Figure 12 In addition, Figure 28 In the example, the highest-order memory chip 70h is selected, but the present invention is not limited thereto. Furthermore, a plurality of memory chips 70 may be selected.

[0273] like Figure 28 As shown, during a write or read operation, the ODT control circuit 52 of each memory chip 70 (70a-70h) determines the location of the mounted memory chip 70 in each memory 10 based on the chip address data CADD sent from the controller 100. Furthermore, in the case of the highest-order memory chip 70h, for example, the ODT control circuit 52 turns on the corresponding ODT circuit 60 based on the ODT enable signal ODTEN.

[0274] 8.2 Effects of this Implementation

[0275] According to the configuration of this embodiment, the same effects as those of the second embodiment can be obtained.

[0276] Furthermore, in this embodiment, only the memory chips 70 that effectively reduce reflection signals can be selected from each memory 10 based on the chip address data CADD, and the ODT circuit 60 can be activated. This allows for further optimal control of the ODT circuit 60, more effectively reducing interference caused by signal reflection, and thus improving signal quality.

[0277] Furthermore, in this embodiment, the memory chip 70 to be written or read can be identified based on the chip address data CADD, thereby enabling the operation of the ODT circuit 60 to be controlled according to the target memory chip 70. This allows for better control of the ODT circuit 60, more effectively reducing interference caused by signal reflection, and thus improving signal quality.

[0278] Furthermore, in this embodiment, even if the ODT enable signal ODTEN is common to all memory chips 70, the memory chip 70 to which the ODT circuit 60 is to be turned on can be selected based on the chip address data CADD. This allows the signal line for the ODT enable signal connecting the controller 100 and each memory 10 to be a common signal line. This simplifies the memory system configuration and reduces the increase in chip area.

[0279] 9. Modifications, etc.

[0280] The memory system of the embodiment includes a first nonvolatile semiconductor memory device ( Figure 1 10) and the controller ( Figure 1 The controller can combine the first signal with the second signal ( Figure 3 The first nonvolatile semiconductor memory device includes: a first terminal connected to the controller and receiving the second signal; a first circuit ( Figure 3 60), including first and second resistance elements ( Figure 4 63a and 63b in), connect the first resistor element to the power supply voltage line ( Figure 4 The first switching element ( Figure 4 61), and connect the second resistor element to the ground voltage line ( Figure 4 The second switching element ( Figure 4 62); and the 2nd Circuit ( Figure 3 52), using the first signal ( Figure 3 The second circuit controls the first circuit when the logic level of the first signal is switched ( Figure 7 L to H in the second signal is at the first logic level ( Figure 7 In the case of H), the first and second switch elements are turned off, and when the second signal is at the second logic level ( Figure 7 L in ), turning on the first and second switching elements.

[0281] By applying the above-described embodiments, a nonvolatile semiconductor memory device and a memory system capable of improving processing performance can be provided.

[0282] Furthermore, the embodiments are not limited to the above-described embodiments and can be modified in various ways. Furthermore, the embodiments can be combined to the extent possible. For example, the first example of the fifth embodiment and the eighth embodiment can be applied to the configuration of the second embodiment, omitting the terminal corresponding to the ODT enable signal ODTEN and selecting the memory chip 70 to turn on the ODT circuit 60 based on the chip address data CADD.

[0283] Furthermore, in the above-described embodiment, the controller 100 may include an ODT circuit 60. For example, when signals are transmitted and received between the memories 10, the ODT circuit 60 of the controller 100 may be turned on.

[0284] Furthermore, in the above embodiment, the ODT circuit 60 is connected to the terminals corresponding to the data lines DQ[7:0], the clock signals DQS and DQSn, and the read enable signals REn and RE. However, the terminals to which the ODT circuit 60 is connected are not limited to these.

[0285] Furthermore, in the above embodiment, the ODT circuit 60 connected to the terminals corresponding to the read enable signals REn and RE is described as being disconnected in the DIN mode and connected in the DOUT mode. However, the ODT circuit 60 that switches on and off in the DIN mode and the DOUT mode is not limited to this.

[0286] Furthermore, in the above-described embodiment, the variable resistance elements 63 a and 63 b of the ODT control circuit 52 may be set to different resistance values ​​in the DIN mode and the DOUT mode.

[0287] Furthermore, in the above-described embodiment, the interface chip 20 (or the memory chip 70 ) using the ODT circuit 60 is not limited to the non-selected memory 10 (or the memory chip 70 ).

[0288] Furthermore, the above-described embodiment can also be applied to either a planar NAND flash memory or a three-dimensional stacked NAND flash memory.

[0289] Furthermore, the term “connected” in the above-described embodiment also includes a state of indirect connection with another component such as a transistor or a resistor interposed therebetween.

[0290] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways and can be omitted, replaced, or modified without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope and spirit of the invention and are also included within the scope of the invention set forth in the claims and their equivalents.

[0291] Furthermore, in each embodiment related to the present invention, the following may be employed. For example, the memory cell transistor MT can hold 2-bit (4-value) data, and when the threshold level when holding one of the 4 values ​​is set to E level (erase level), A level, B level, and C level in ascending order,

[0292] (1) During reading:

[0293] The voltage applied to the selected word line in the A-level read operation is, for example, between 0 V and 0.55 V. However, the voltage is not limited thereto and may be any one of 0.1 V to 0.24 V, 0.21 V to 0.31 V, 0.31 V to 0.4 V, 0.4 V to 0.5 V, and 0.5 V to 0.55 V.

[0294] The voltage applied to the selected word line in the B-level read operation is, for example, between 1.5 V and 2.3 V. However, the voltage is not limited thereto and may be any one of 1.65 V to 1.8 V, 1.8 V to 1.95 V, 1.95 V to 2.1 V, and 2.1 V to 2.3 V.

[0295] The voltage applied to the selected word line in the C-level read operation is, for example, between 3.0 V and 4.0 V. However, the voltage is not limited thereto and may be any one of 3.0 V to 3.2 V, 3.2 V to 3.4 V, 3.4 V to 3.5 V, 3.5 V to 3.6 V, and 3.6 V to 4.0 V.

[0296] The time (tR) of the read operation may be set to, for example, 25 μs to 38 μs, 38 μs to 70 μs, or 70 μs to 80 μs.

[0297] (2) The write operation includes the programming operation and the verification operation as described above. In the write operation:

[0298] The voltage initially applied to the selected word line during the programming operation is, for example, between 13.7 V and 14.3 V. However, the voltage is not limited thereto and may be, for example, between 13.7 V and 14.0 V or between 14.0 V and 14.6 V.

[0299] The voltage initially applied to the word line selected when writing to the odd-numbered word lines and the voltage initially applied to the word line selected when writing to the even-numbered word lines may be changed.

[0300] When the programming operation is performed by the ISPP method (Incremental Step Pulse Program), the step voltage may be approximately 0.5V, for example.

[0301] The voltage applied to the unselected word lines may be, for example, between 6.0 V and 7.3 V. However, the voltage is not limited to this, and may be, for example, between 7.3 V and 8.4 V, or may be 6.0 V or less.

[0302] The applied pass voltage may also be changed depending on whether the unselected word line is an odd-numbered word line or an even-numbered word line.

[0303] The time (tProg) of the programming operation may be set to, for example, 1700 μs to 1800 μs, 1800 μs to 1900 μs, or 1900 μs to 2000 μs.

[0304] (3) During the deletion action:

[0305] The voltage initially applied to the well formed on the semiconductor substrate and over which the memory cell is arranged is, for example, between 12 V and 13.6 V. However, the voltage is not limited thereto and may be, for example, between 13.6 V and 14.8 V, 14.8 V and 19.0 V, 19.0 V and 19.8 V, or 19.8 V and 21 V.

[0306] The erasing operation time (tErase) may be set to, for example, 3000 μs to 4000 μs, 4000 μs to 5000 μs, or 4000 μs to 9000 μs.

[0307] (4) Structure of storage unit:

[0308] A charge accumulation layer is provided on a semiconductor substrate (silicon substrate) with a tunnel insulating film having a dielectric film thickness of 4 to 10 nm. The charge accumulation layer can be a stacked structure of an insulating film such as SiN or SiON having a film thickness of 2 to 3 nm and polysilicon having a film thickness of 3 to 8 nm. In addition, a metal such as Ru can be added to the polysilicon. An insulating film is provided on the charge accumulation layer. The insulating film, for example, comprises a silicon oxide film having a film thickness of 4 to 10 nm separated between a lower High-k film having a film thickness of 3 to 10 nm and an upper High-k film having a film thickness of 3 to 10 nm. Examples of the High-k film include HfO. In addition, the film thickness of the silicon oxide film can be thicker than that of the High-k film. On the insulating film, a control electrode having a film thickness of 30 to 70 nm is formed with a material for adjusting the work function having a film thickness of 3 to 10 nm. Here, the material for adjusting the work function is a metal oxide film such as TaO or a metal nitride film such as TaN. W or the like can be used as the control electrode.

[0309] In addition, air gaps can be formed between memory cells.

[0310] [Explanation of Symbols]

[0311] 1 Memory System

[0312] 10 Memory

[0313] 20 interface chips

[0314] 21, 32, 41, 42 bumps

[0315] 30, 70 memory chips

[0316] 31 TSV

[0317] 33 Wiring

[0318] 40 Package substrate

[0319] 50 Input and output control circuit

[0320] 51 Logic Circuit

[0321] 52 ODT control circuit

[0322] 53 memory cell array

[0323] 54 Parameter storage unit

[0324] 60 ODT circuit

[0325] 61 p-channel MOS transistor

[0326] 62 n-channel MOS transistors

[0327] 63a, 63b variable resistance elements

[0328] 64 input receiver

[0329] 65 Output Driver

[0330] 71 terminal

[0331] 100 controllers

[0332] 200 host devices

Claims

1. A memory system, characterized in that include: The first memory includes: a first memory cell array capable of storing data; a first terminal for inputting write data to the first memory cell array and outputting read data from the first memory cell array; The second terminal receives a first signal, wherein the first signal indicates a timing for outputting read data; a first ODT circuit connected to the first terminal; a second ODT circuit connected to the second terminal; Terminal 3, input second signal; The second memory includes: a second memory cell array capable of storing data; a fourth terminal connected in common with the first terminal, inputting write data to the second memory cell array and outputting read data from the second memory cell array; a fifth terminal connected in common with the second terminal and inputting the first signal; a third ODT circuit connected to the fourth terminal; a fourth ODT circuit connected to the fifth terminal; The sixth terminal is used to input the second signal; and a controller capable of sending the first signal, the second signal, and write data to the first memory and the second memory, and capable of receiving read data from the first memory and the second memory; and The second signal controls the on / off states of the first ODT circuit, the second ODT circuit, the third ODT circuit, and the fourth ODT circuit; When the controller instructs a write operation or a read operation to the first memory, the controller switches the logic level of the second signal supplied to the sixth terminal of the non-selected second memory; When the logic level of the second signal supplied to the sixth terminal is switched, the non-selected second memory turns on the third ODT circuit and turns off the fourth ODT circuit when the first signal is at the first logic level, and turns on the third and fourth ODT circuits when the first signal is at the second logic level.

2. The memory system according to claim 1, wherein: When the read operation is instructed to the first memory, After the controller sets the second signal to be valid, it continuously inverts the first signal. The first memory outputs the read data in synchronization with the inversion of the first signal during a period in which the second signal is active.

3. The memory system according to claim 2, wherein: The controller performs the read operation. During the first period, the logic level of the first signal is maintained. From the beginning to the end of the first period, the second signal is set to be valid, In a second period following the first period, the first signal is continuously inverted.

4. The memory system according to claim 3, wherein: The first period is 25 nsec or longer. The controller activates the second signal after 5 nsec or more has passed since the start of the first period in the read operation.

5. The memory system according to claim 1, wherein: The second signal is an asynchronous signal.

6. The memory system according to claim 1, wherein: The sixth terminal is connected in common with the third terminal.

7. The memory system according to claim 1, wherein: The second signal also functions as a signal for instructing prohibition of the write operation.

8. The memory system according to claim 1, wherein: The controller instructs the second memory to perform a parameter setting operation. The second memory prevents the write operation based on the second signal before the parameter setting operation, and controls the third ODT circuit and the fourth ODT circuit based on the second signal after the parameter setting operation.

9. The memory system according to claim 1, wherein: Each of the first memory and the second memory includes: interface chip; and Each of the plurality of memory chips includes a through electrode extending from the upper surface to the lower surface thereof.

10. The memory system according to claim 1, wherein: Each of the first memory and the second memory is a memory chip.

11. The memory system according to claim 1, wherein: Each of the first ODT circuit, the second ODT circuit, the third ODT circuit, and the fourth ODT circuit includes: a first resistance element; a first switching element electrically connecting the first resistor element to a power supply voltage line; a second resistor element; and The second switching element electrically connects the second resistance element to the ground voltage line.

12. The memory system according to claim 1, wherein: Each of the first memory and the second memory is a NAND flash memory.

13. The memory system according to claim 1, wherein: The second signal is a signal for controlling the on / off state of the ODT circuit.

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