Register unit, cascade register and control method
By combining the latch function and flow control signal processing data in the register unit and cascade register, the loss problem caused by data congestion is solved, complexity and resource waste are reduced, and flexible data processing is achieved.
Patent Information
- Application Number
- CN202010896428.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-08-31
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2040-08-31
AI Technical Summary
In integrated circuit design, when data congestion occurs downstream, the previous cascading register cannot receive the flow control signal, resulting in the last stage register being unable to stop data transmission during the clock cycle, which may lead to data loss. FIFO cache is needed to avoid Functional errors, but this increases complexity and resource waste.
Design a register unit and cascade register to process data through the latch function of the register and the downstream flow control signal, and send a flow control signal to the upstream when the upstream data cannot be processed, avoid data loss, reduce the complexity of flow control, and No FIFO cache is required.
Improves the flexibility of data processing, reduces the complexity of traffic control, saves resources, and avoids data loss and functional errors.
Smart Images
Figure CN112036112B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of electronic circuits, and in particular relates to a register unit, a cascade register and a control method. Background Art
[0002] In the integrated circuit design process, when the amount of data is large, it will be stored through multiple levels of cascaded registers. The cascaded registers transmit the data to the next level of registers within the clock cycle, and the last level of registers sends the data to the downstream for processing.
[0003] When data congestion occurs downstream, a flow control signal will be sent to the last register. Since the previous cascade registers cannot receive the flow control signal, the data transmission within the clock cycle will not be stopped, resulting in the need to add a FIFO (first-in, first-out buffer) behind the last register to cache the data transmitted by the previous registers. Otherwise, data loss will occur, resulting in chip function errors.
[0004] However, adding FIFO for caching will increase the complexity of flow control and cause waste of resources and chip area. Summary of the invention
[0005] The object of the present invention is to provide a register unit, a cascade register and a control method.
[0006] To achieve one of the above-mentioned objects of the invention, an embodiment of the present invention provides a register unit, at least two register units are cascaded, each of the register units comprises a register and a control module connected to each other, wherein:
[0007] The register is used to latch data and send the latch status of the register to the control module at this level;
[0008] The control module is used to process the data in the register of this level according to the control signal of the lower level control module, and generate the control signal of the control module of this level in combination with the latch state of the register of this level, and send it to the upper level control module.
[0009] As a further improvement of an embodiment of the present invention, the latch state of the register includes latching data and not latching data, and the control module is further used for:
[0010] When receiving a control signal with a value of 1 from the lower-level control module, if there is data latched in the register at this level, the data in the register at this level is sent to the lower-level control module, and a control signal with a value of 1 for the control module at this level is sent to the upper-level control module; if there is no latched data in the register at this level, a control signal with a value of 1 for the control module at this level is sent directly to the upper-level control module.
[0011] As a further improvement of an embodiment of the present invention, the register is also used to send a latched state of the register to a lower-level control module;
[0012] The control module is also used for latching the received data in the current level register when receiving the data from the upper level register if the latching state of the upper level register is that the data is latched.
[0013] As a further improvement of an embodiment of the present invention, the control module is further used for:
[0014] When receiving a control signal with a value of 0 from the lower control module, if the register at this level latches data, a control signal with a value of 0 from the current level is sent to the upper control module, otherwise a control signal with a value of 1 from the current level is sent to the upper control module.
[0015] To achieve one of the above-mentioned objects of the invention, an embodiment of the present invention provides a cascade register, wherein the cascade register is formed by cascading at least two of the above-mentioned register units, wherein:
[0016] The register at this level outputs the latch status of the register to the lower level control module;
[0017] The control module at this level outputs control signals to the upper-level control module.
[0018] To achieve one of the above-mentioned objects of the invention, an embodiment of the present invention provides a control method of a register unit, wherein the register unit comprises a register and a control module connected to each other, and the method comprises:
[0019] When receiving a control signal with a value of 1 from a lower-level control module, the data in the register of this level is sent to the lower-level control module, and a control signal with a value of 1 from the control module of this level is sent to the upper-level control module;
[0020] When receiving a control signal with a value of 0 from the lower control module, if the register at this level latches data, a control signal with a value of 0 from the current level is sent to the upper control module, otherwise a control signal with a value of 1 from the current level is sent to the upper control module.
[0021] As a further improvement of an embodiment of the present invention, the method further includes:
[0022] When receiving data from the upper register, if the latch state of the upper register is latched with data, the received data is latched in the register at this level.
[0023] To achieve one of the above-mentioned objects of the invention, an embodiment of the present invention provides a control method for a cascade register, wherein the cascade register is formed by cascading at least two of the above-mentioned register units, each of the register units includes a register and a control module connected to each other, and the method includes:
[0024] When the control module of the last-level register unit receives the downstream flow control signal, if the register of this level has data latched, it sends a control signal of 0 to the upper-level control module, otherwise it sends a control signal of 1 to the upper-level control module;
[0025] When the control module of the register unit in the middle receives a control signal with a value of 0 from the lower control module, if the register at this level has data latched, it sends a control signal with a value of 0 to the upper control module, otherwise it sends a control signal with a value of 1 to the upper control module;
[0026] When the control module of the first-level register unit receives a control signal with a value of 0 from the lower-level control module, if the register at this level has data latched, a flow control signal is sent upstream.
[0027] As a further improvement of an embodiment of the present invention, the method further includes:
[0028] If the control module of the last-level register unit does not receive the flow control signal from the downstream, it sends the data latched by the register of this level to the downstream according to the clock signal, and sends a control signal of 1 to the upper-level control module;
[0029] When the control module of the register unit in the middle receives the control signal of 1 from the lower control module, it sends the data latched in the register of this level to the lower control module, and sends the control signal of 1 from this level to the upper control module.
[0030] As a further improvement of an embodiment of the present invention, the method further includes:
[0031] If the control module of the middle or last register unit receives data from the upper register, and the latch state of the upper register is that data is latched, the received data is latched in the register of this level.
[0032] Compared with the prior art, the register unit and cascade register of the present invention process the data latched by the register at this level through the latching function of the register itself and the downstream flow control signal, and send a flow control signal to the upstream when the upstream data cannot be processed, thereby improving the flexibility of data processing, reducing the complexity of flow control of data processing, and eliminating the need for FIFO caching, saving resources. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 It is a structural schematic diagram of the register unit of the present invention.
[0034] Figure 2 It is a schematic diagram of the structure of the cascade register of the present invention.
[0035] Figure 3 It is a flow chart of the control method of the register unit of the present invention.
[0036] Figure 4 It is a flow chart of the control method of the cascade register of the present invention.
[0037] Among them: 10, the latch state of the register at this level; 20, the latch state of the upper register; 30, the control signal of the control module at this level; 40, the control signal of the lower control module; 50, the downstream flow control signal. DETAILED DESCRIPTION
[0038] The present invention will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.
[0039] The present invention provides a register unit, which processes data latched by a register of this level through the latching function of the register itself and a downstream flow control signal, and sends a flow control signal to the upstream when the upstream data cannot be processed, thereby improving the flexibility of data processing, reducing the complexity of flow control of data processing, and eliminating the need for FIFO caching, thereby saving resources.
[0040] like Figure 1 and Figure 2 As shown, at least two register units are cascaded, each of the register units includes a register and a control module connected to each other, wherein:
[0041] The register is used to latch data and send the latched state 10 of the register to the control module at this level.
[0042] The control module is used to process the data in the register of the current level according to the control signal 40 of the lower level control module, and generate the control signal 30 of the current level control module in combination with the latch state 10 of the register of the current level, and send it to the upper level control module. Here, the register of the current level and the control module of the current level respectively represent the register and the control module of the register unit of the current level, the upper level register and the upper level control module respectively represent the register and the control module of the upper level register unit, and the lower level register and the lower level control module respectively represent the register and the control module of the lower level register unit.
[0043] It should be noted that the registers in the register unit of the present invention no longer send data to the lower-level register unit based on the clock signal, but based on the control signal of the lower-level register unit. When the lower-level register unit is capable of processing the data, the data in the register of this level will be sent to the lower-level register unit, thereby avoiding the situation where the last-level register unit is unable to process the data sent by the upper-level register unit after the flow control signal appears downstream.
[0044] In a preferred embodiment, the latch state of the register includes latching data and not latching data, and the control module is further used to:
[0045] When receiving the control signal 40 with a value of 1 from the lower-level control module, if there is data latched in the register at this level, the data in the register at this level is sent to the lower-level control module, and the control signal 30 with a value of 1 for the control module at this level is sent to the upper-level control module; if there is no latched data in the register at this level, the control signal 30 with a value of 1 for the control module at this level is sent directly to the upper-level control module.
[0046] It should be noted that a control signal value of 1 indicates that the corresponding control module can process data, and a control signal value of 0 indicates that the corresponding control module cannot process data at present, that is, data congestion occurs. Of course, the control signal can also use other values to represent the state in which the corresponding control module can or cannot process data. When the lower-level register unit can process data, the corresponding control module sends a control signal with a value of 1 to the upper-level control module, otherwise it sends a control signal with a value of 0.
[0047] Furthermore, the register is also used to send the latching state of the register to the lower-level control module; the control module is also used to latch the received data in the register of this level when receiving data from the upper-level register if the latching state of the upper-level register is latching data.
[0048] Furthermore, when receiving a control signal with a value of 0 from the lower-level control module, if the register at this level has data latched, a control signal with a value of 0 for the control module at this level is sent to the upper-level control module, otherwise a control signal with a value of 1 for the control module at this level is sent to the upper-level control module. That is, when congestion occurs in the lower-level register unit, if the register at this level does not latch data, the upper-level register unit is notified through a control signal to send data, and if the register at this level has data latched, the upper-level register unit is notified that the register unit at this level is congested.
[0049] like Figure 3 As shown, the present invention also provides a control method for a register unit, the register unit is as described above, and the method includes:
[0050] Step S110: when receiving a control signal of 1 from a lower-level control module, sending the data in the register of this level to the lower-level control module, and sending a control signal of 1 from this level to the upper-level control module.
[0051] Step S120: When receiving a control signal with a value of 0 from the lower control module, if the register at the current level has data latched, a control signal with a value of 0 from the current level is sent to the upper control module; otherwise, a control signal with a value of 1 from the current level is sent to the upper control module.
[0052] Furthermore, the method further comprises:
[0053] When receiving data from the upper register, if the latch state of the upper register is latched with data, the received data is latched in the register at this level.
[0054] like Figure 2 As shown, the present invention also provides a cascade register, which is formed by cascading at least two of the above-mentioned register units, wherein: the register at this level outputs the latch state of the register to the lower-level control module; the control module at this level outputs a control signal to the upper-level control module.
[0055] The present invention also provides a control method for a cascade register, wherein the cascade register is formed by cascading at least two of the above register units as described above, and each of the register units includes a register and a control module connected to each other. It should be noted that the cascade register is connected to an upstream and a downstream, and the register of the last level register unit of the cascade register is connected to the downstream, and at the same time, the last level register unit (such as Figure 2 The control module of the register unit N in the first level receives the flow control signal from the downstream. Figure 2 The control module of the register unit 1) receives upstream data and sends a flow control signal to the upstream.
[0056] like Figure 4 As shown, the method includes:
[0057] Step S210: When the control module of the last-level register unit receives the downstream flow control signal, if the register at this level latches data, a control signal of 0 is sent to the upper-level control module; otherwise, a control signal of 1 is sent to the upper-level control module.
[0058] Step S220: When the control module of the register unit located in the middle receives a control signal with a value of 0 from the lower control module, if the register at this level latches data, a control signal with a value of 0 is sent to the upper control module; otherwise, a control signal with a value of 1 is sent to the upper control module.
[0059] The middle register unit refers to a register unit located between the first-stage register unit and the last-stage register unit in the cascade connection.
[0060] Step S230: When the control module of the first-level register unit receives a control signal with a value of 0 from the lower-level control module, if the register at this level has data latched, a flow control signal is sent upstream.
[0061] In a preferred embodiment, the method further comprises:
[0062] If the control module of the last-level register unit does not receive the flow control signal from the downstream, it sends the data latched by the register of this level to the downstream according to the clock signal, and sends a control signal of 1 to the upper-level control module;
[0063] When the control module of the register unit in the middle receives the control signal of 1 from the lower control module, it sends the data latched in the register of this level to the lower control module, and sends the control signal of 1 from this level to the upper control module.
[0064] In a specific embodiment, the method further comprises:
[0065] If the control module of the middle or last register unit receives data from the upper register, and the latch state of the upper register is that data is latched, the received data is latched in the register of this level.
[0066] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.
[0067] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.
Claims
1. A register unit, It is characterized in that At least two register units are cascaded, each of the register units comprising a register and a control module connected to each other, wherein: The register is used to latch data and send the latch status of the register to the control module at this level; The control module is used to process the data in the register of this level according to the control signal of the lower level control module, and generate the control signal of the control module of this level in combination with the latch state of the register of this level, and send it to the upper level control module; Among them, the latching state of the register includes latching data and not latching data, and the control module is also used to: when receiving a control signal with a value of 1 from the lower-level control module, if there is data latched in the register at this level, send the data in the register at this level to the lower-level control module, and send a control signal with a value of 1 for the control module at this level to the upper-level control module; if there is no latched data in the register at this level, directly send a control signal with a value of 1 for the control module at this level to the upper-level control module.
2. The register unit according to claim 1, Features: The register is also used to send the latch state of the register to the lower-level control module; The control module is also used for latching the received data in the current level register when receiving the data from the upper level register if the latching state of the upper level register is that the data is latched.
3. The register unit according to claim 1, It is characterized in that The control module is also used for: When receiving a control signal with a value of 0 from the lower control module, if the register at this level latches data, a control signal with a value of 0 from the current level is sent to the upper control module, otherwise a control signal with a value of 1 from the current level is sent to the upper control module.
4. A cascade register, It is characterized in that The cascade register is formed by cascading at least two register units according to any one of claims 1 to 3, wherein: The register at this level outputs the latch status of the register to the lower level control module; The control module at this level outputs control signals to the upper-level control module.
5. A control method for a register unit, It is characterized in that The register unit includes a register and a control module connected to each other, and the method includes: When receiving a control signal with a value of 1 from a lower-level control module, the data in the register of this level is sent to the lower-level control module, and a control signal with a value of 1 from the control module of this level is sent to the upper-level control module; When receiving a control signal with a value of 0 from the lower control module, if the register at this level latches data, a control signal with a value of 0 from the current level is sent to the upper control module, otherwise a control signal with a value of 1 from the current level is sent to the upper control module.
6. The control method of the register unit according to claim 5, It is characterized in that The method further comprises: When receiving data from the upper register, if the latch state of the upper register is latched with data, the received data is latched in the register at this level.
7. A control method for cascade registers, It is characterized in that The cascade register is formed by cascading at least two of the above register units, each of the register units includes a register and a control module connected to each other, and the method includes: When the control module of the last-level register unit receives the downstream flow control signal, if the register of this level has data latched, it sends a control signal of 0 to the upper-level control module, otherwise it sends a control signal of 1 to the upper-level control module; When the control module of the register unit in the middle receives a control signal with a value of 0 from the lower control module, if the register at this level has data latched, it sends a control signal with a value of 0 to the upper control module, otherwise it sends a control signal with a value of 1 to the upper control module; When the control module of the first-level register unit receives a control signal with a value of 0 from the lower-level control module, if the register at this level has data latched, a flow control signal is sent upstream.
8. The control method of the cascade register according to claim 7, It is characterized in that The method further comprises: If the control module of the last-level register unit does not receive the flow control signal from the downstream, it sends the data latched by the register of this level to the downstream according to the clock signal, and sends a control signal of 1 to the upper-level control module; When the control module of the register unit in the middle receives the control signal of 1 from the lower control module, it sends the data latched in the register of this level to the lower control module, and sends the control signal of 1 from this level to the upper control module.
9. The control method of the cascade register according to claim 7, It is characterized in that The method further comprises: If the control module of the middle or last register unit receives data from the upper register, and the latch state of the upper register is that data is latched, the received data is latched in the register of this level.