Semiconductor device and method for forming the same
By forming a hard mask layer on the substrate of a semiconductor device and cutting the dummy gate structure with the cutting zone hard mask layer, the problem of poor quality of semiconductor device formation in the prior art is solved, and higher performance and stability are achieved sex.
Patent Information
- Application Number
- CN201910508001.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2019-06-12
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2039-06-12
AI Technical Summary
In the process of reducing size and increasing density of existing semiconductor devices, it is difficult to ensure the formation quality, and there is a short channel effect that leads to leakage current, affecting electrical performance.
A hard mask layer is formed on the substrate, and a discretely arranged fins are etched by the hard mask layer as a mask, and the hard mask layer on the top of the fins in the non-cut area is removed. When forming a dummy gate structure, the cutting area is hard The mask layer is cut to simplify the process and improve the contact quality of the fin and gate structure.
This method simplifies the process, improves the performance and quality of semiconductor devices, reduces failure phenomena during use, and expands the scope of use of devices.
Smart Images
Figure CN112086401B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a method for forming the same. Background Art
[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. As the most basic semiconductor device, the device is currently being widely used. The control ability of traditional planar devices on channel current has weakened, resulting in short channel effect and leakage current, which ultimately affects the electrical performance of semiconductor devices.
[0003] In order to overcome the short channel effect of the device and suppress leakage current, the prior art proposes a fin field effect transistor (Fin FET). The fin field effect transistor is a common multi-gate device. The structure of the fin field effect transistor includes: a fin and an isolation structure located on the surface of a semiconductor substrate, the isolation structure covers a portion of the sidewall of the fin, a gate structure located on the substrate and across the fin; and a source region and a drain region in the fin located on both sides of the gate structure.
[0004] However, as the size of semiconductor devices continues to shrink and the device density increases, how to ensure the formation of semiconductor devices with good quality has become an urgent problem that needs to be solved. Summary of the invention
[0005] The problem solved by the present invention is to provide a semiconductor device and a method for forming the same, thereby ensuring that the formed semiconductor device has higher quality.
[0006] To solve the above problems, the present invention provides a method for forming a semiconductor device, comprising: providing a substrate, the substrate comprising a cutting area and a non-cutting area; forming a hard mask layer on the substrate; etching a portion of the thickness of the substrate using the hard mask layer as a mask to form discretely arranged fins; removing the hard mask layer on the top of the fin in the non-cutting area; forming a dummy gate structure on the substrate, the dummy gate structure spanning the fin, and the top surface of the dummy gate structure is flush with the top surface of the hard mask layer.
[0007] Optionally, the material of the hard mask layer includes silicon nitride, silicon oxide, silicon oxynitride or silicon carbide.
[0008] Optionally, the process of forming the hard mask layer includes chemical vapor deposition, atomic layer vapor deposition or physical vapor deposition.
[0009] Optionally, the step of removing the hard mask layer on the fin in the non-cutting area includes: forming a photoresist layer on the substrate, the opening of the photoresist layer exposing the hard mask layer on the fin in the non-cutting area; using the photoresist layer as a mask; and removing the hard mask layer on the fin in the non-cutting area.
[0010] Optionally, a partial thickness of the substrate is etched by dry etching to form discretely arranged fins.
[0011] Optionally, after forming the dummy gate structure, the method further includes: removing the dummy gate structure; and forming a gate structure on the substrate, wherein the gate structure spans across the fin.
[0012] Optionally, the gate structure includes a gate dielectric layer and a metal gate.
[0013] Optionally, an isolation structure is also included, wherein the isolation structure covers a portion of the side wall of the fin.
[0014] Optionally, after forming the dummy gate structure, a top surface of the dummy gate structure is ground by chemical mechanical grinding.
[0015] The present invention also provides a semiconductor device formed by the above method, comprising: a substrate, including a cutting area and a non-cutting area; a plurality of fins, discretely arranged on the substrate; a hard mask layer, located on the top of the fins in the cutting area; a pseudo gate structure, located on the substrate, spanning the fins and with the top surface flush with the top of the hard mask layer.
[0016] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0017] A hard mask layer is formed on a substrate, and a portion of the substrate is etched using the hard mask as a mask to form discretely arranged fins. At this time, the hard mask layer on top of the fin in the non-cutting area of the substrate is removed. Due to the existence of the hard mask layer on top of the fin in the cutting area, the combined height of the fin and the hard mask layer in the cutting area is higher than the height of the fin in the non-cutting area. When a pseudo-gate structure is formed, the pseudo-gate structure is cut by the hard mask layer in the cutting area to obtain a rectangular-shape lineend. This method of obtaining a rectangular-shape lineend not only simplifies the process, but also improves the performance of the formed semiconductor device. This is because the existence of the hard mask layer in the cutting area directly cuts the pseudo-gate structure when forming the pseudo-gate structure, and no extra process is required. At the same time, due to the subsequent removal of the pseudo-gate structure to form a gate structure, there is no extra gap between the gate structure and the fin, and no holes or gaps will appear in the gate structure when it is formed, ensuring that a good quality gate structure can be formed, thereby improving the quality of the formed semiconductor device, reducing the failure of the semiconductor device during use, and expanding the scope of use of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figures 1 to 6 is a structural schematic diagram of a semiconductor device forming process in one embodiment;
[0019] Figures 7 to 13 is a structural schematic diagram of a semiconductor device forming process in a first embodiment of the present invention;
[0020] Figures 14 to 19 It is a structural schematic diagram of the semiconductor device forming process in the second embodiment of the present invention. DETAILED DESCRIPTION
[0021] In semiconductor devices, a polysilicon gate cut mask (Poly gate cut mask, P2) is usually used to obtain a rectangular-shape line end, so that the gate pattern can be better controlled and the density of the semiconductor device can be improved. The specific method of forming the semiconductor device is as follows:
[0022] refer to Figure 1 , providing a substrate 1, wherein the substrate 1 includes a cutting area 11 and a non-cutting area 12.
[0023] refer to Figure 2 A plurality of discretely arranged fins 2 are formed on the substrate 1 .
[0024] refer to Figure 3 , a dummy gate structure 3 spanning the fin 2 is formed on the substrate 1 .
[0025] refer to Figure 4, an opening 4 is formed in the dummy gate structure 3 in the cutting area 11 .
[0026] refer to Figure 5 , the opening 4 is filled with an insulating layer 5 .
[0027] refer to Figure 6 , remove the dummy gate structure 3 to form a gate structure 6.
[0028] The inventors found that the semiconductor device formed by using this method to obtain the rectangular line end has poor stability in performance, and the integration of the semiconductor device formed is low. The reason for the low integration of the formed semiconductor device is that when the insulating layer is formed, the insulating layer is filled in the opening formed by the pseudo gate structure, and there is a pseudo gate structure between the formed insulating layer and the fin, so there is a certain distance between the fin and the insulating layer, resulting in waste of space; the reason why the formed semiconductor device has poor stability during use is that when the pseudo gate structure is removed to form the gate structure, there is a small gap between the fin and the insulating layer, so when the gate structure is formed, the gas pressure inside the gap has a strong reaction to the formation of the gate structure, and it is easy to form holes or gaps inside the gate structure. Such holes or gaps easily cause the failure of the use function of the semiconductor device and limit the use of the semiconductor device.
[0029] The inventors have discovered that a hard mask layer is formed on a substrate, and a portion of the substrate is etched using the hard mask layer as a mask to form a fin. The top surface of the fin thus formed has a hard mask layer. At this time, the hard mask on the top of the fin in the non-cutting area is removed. When a pseudo-gate structure is formed, since the top of the fin in the cutting area has a hard mask layer, the hard mask layer in the cutting area directly cuts the pseudo-gate structure, thereby obtaining a rectangular line end. This formation method simplifies the process of obtaining a rectangular line end on the one hand; on the other hand, when the pseudo-gate structure is removed to form a gate structure, there is no additional reaction force acting on the gate structure, so that there are no gaps or holes in the formed gate structure, thereby ensuring the quality of the formed gate structure, thereby improving the performance of the formed semiconductor device.
[0030] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0031] First embodiment
[0032] Figures 7 to 13 It is a structural schematic diagram of the semiconductor device forming process in the first embodiment of the present invention.
[0033] First reference Figure 7 , providing the substrate 100 , wherein the substrate 100 includes a cutting area 110 and a non-cutting area 120 .
[0034] In this embodiment, the material of the substrate 100 is single crystal silicon; in other embodiments, the substrate 100 may be single crystal silicon, polycrystalline silicon or amorphous silicon; the substrate 100 may also be a semiconductor material such as silicon, germanium, germanium silicon, gallium arsenide, etc.
[0035] refer to Figure 8 , a hard mask layer 200 is formed on the substrate 100 .
[0036] In this embodiment, the material of the hard mask layer 200 is silicon nitride; in other embodiments, the material of the hard mask layer 200 may also be silicon oxide, silicon oxynitride or silicon carbide.
[0037] In this embodiment, the hard mask layer 200 covers the position where the fin is formed.
[0038] In this embodiment, the hard mask layer 200 is formed by atomic layer deposition. In other embodiments, the hard mask layer 200 may be formed by chemical vapor deposition or physical vapor deposition.
[0039] In this embodiment, the atomic layer deposition method parameters include: the gas used is a mixed gas of SiH2Cl2 and NH3, the flow rate of the mixed gas is 1500sccm~4000sccm, the pressure is 1mtorr~10mtorr, the temperature is 200 degrees Celsius~600 degrees Celsius, and the number of deposition times is 30 times~100 times.
[0040] refer to Fig. 9 , using the hard mask layer 200 as a mask to etch a portion of the thickness of the substrate 100 , to form discretely arranged fins 300 on the substrate 100 .
[0041] In this embodiment, a partial thickness of the substrate 100 is etched by dry etching to form the fin 300 ; in other embodiments, a partial thickness of the substrate 100 may be etched by wet etching to form the fin 300 .
[0042] In this embodiment, the parameters of the dry etching include: the etching gases used include HBr and Ar, wherein the flow rate of HBr is 10 sccm to 1000 sccm, and the flow rate of Ar is 10 sccm to 1000 sccm.
[0043] refer to Fig.10 , a photoresist layer 201 is formed on the substrate 100 , and an opening of the photoresist layer 201 exposes the hard mask layer 200 in the non-cutting area 120 .
[0044] In this embodiment, the material of the photoresist layer 201 is krypton fluoride (KrF); in other embodiments, argon fluoride (ArF) may also be used.
[0045] refer to Fig.11 , using the photoresist layer 201 as a mask, removing the hard mask layer 200 on the fin 300 in the non-cutting area 120 .
[0046] In this embodiment, anisotropic dry etching is used to remove the hard mask layer 200 on the fin 300 in the non-cutting area 120 ; in other embodiments, wet etching may also be used to remove the hard mask layer 200 .
[0047] In this embodiment, the dry etching parameters include: the gases used include CF4 gas and CHF3 gas, the flow rate of CF4 gas is 8sccm~500sccm, the flow rate of CHF3 gas is 30sccm~200sccm, the chamber pressure is 10mtorr~2000mtorr, the source RF power is 100W~1300W, the bias voltage is 80V~500V, and the time is 4 seconds~500 seconds.
[0048] refer to Fig.12 , remove the photoresist layer 201.
[0049] In this embodiment, an ashing process is used to remove the photoresist layer 201 ; in other embodiments, a chemical solution may also be used to remove the photoresist layer 201 .
[0050] refer to Fig.13 A dummy gate structure 400 is formed on the substrate 100 , wherein the dummy gate structure 400 spans across the fin 300 , and a top surface of the dummy gate structure 400 is flush with a top surface of the hard mask layer 200 .
[0051] In the present embodiment, the dummy gate structure 400 is cut in the cutting area 110 to form a cut-off dummy gate structure. The dummy gate structure 400 is directly cut using the fin 300 having the hard mask layer 200, so as to obtain a rectangular line end. On the one hand, this simplifies the process of obtaining the rectangular line end; on the other hand, when the dummy gate structure 400 is subsequently removed to form a gate structure, there is no additional force acting on the gate structure, so that the quality of the formed gate structure is improved, thereby improving the performance of the formed semiconductor device.
[0052] In this embodiment, after the dummy gate structure 400 is formed and deposited, the top surface of the dummy gate structure 400 is polished by chemical mechanical polishing, so that the top surface of the dummy gate structure 400 is flush with the top surface of the hard mask layer 200 .
[0053] In other embodiments, mechanical grinding is further used to make the top surface of the dummy gate structure 400 flush with the top surface of the hard mask layer 200 .
[0054] In the present embodiment, chemical mechanical polishing is used to make the top surface of the dummy gate structure 400 flush with the top surface of the hard mask layer 200. The reason is that chemical mechanical polishing combines the advantages of chemical polishing and mechanical polishing, which can ensure the efficiency of removing the excess dummy gate structure 400, and at the same time obtain a more perfect surface of the dummy gate structure 400, and the surface flatness of the dummy gate structure 400 is higher.
[0055] A semiconductor device formed by the above method includes: a substrate 100, including a cutting area 110 and a non-cutting area 120; fins 300, which are discretely arranged on the substrate 100; a hard mask layer 200, which is located on the top of the fins 300 in the cutting area 110; and a pseudo gate structure 400, which is located on the substrate 100, spanning the fins 300 and having a top surface flush with the top surface of the hard mask layer 200.
[0056] Second embodiment
[0057] Figures 14 to 19 Schematic diagram of the semiconductor device forming process in the first embodiment of the present invention
[0058] In this embodiment, the process from providing the substrate to forming the fin is the same as that of the first embodiment, and will not be described in detail. Figures 7 to 9 .
[0059] refer to Fig.14 , an isolation structure 500 is formed on the substrate 100 , and the isolation structure 500 covers a portion of the sidewall of the fin 300 .
[0060] In this embodiment, the isolation structure 500 is formed on the substrate 100 ; in other embodiments, the isolation structure 500 may not be formed on the substrate 100 .
[0061] In this embodiment, the material of the isolation structure 500 is silicon oxide; in other embodiments, the material of the isolation structure 500 may also be silicon nitride or silicon oxynitride.
[0062] In this embodiment, the isolation structure 500 adopts a shallow trench isolation (STI) structure, and the shallow trench isolation structure is formed in a traditional manner.
[0063] In this embodiment, the isolation structure 500 not only protects the substrate 100 , but also serves as an etching stop layer in a subsequent etching process.
[0064] In this embodiment, the isolation structure 500 is formed by using a conventional process.
[0065] refer to Fig.15 , a photoresist layer 201 is formed on the substrate 100 , and an opening of the photoresist layer 201 exposes the hard mask layer 200 in the non-cutting area 120 .
[0066] In this embodiment, the material of the photoresist layer 201 is argon fluoride (ArF).
[0067] refer to Fig.16 , using the photoresist layer 201 as a mask, removing the hard mask layer 200 on the fin 300 in the non-cutting area 120 .
[0068] In this embodiment, the hard mask layer 200 is removed by the same method as in the first embodiment.
[0069] refer to Fig.17 , remove the photoresist layer 201.
[0070] In this embodiment, an ashing process is used to remove the photoresist layer 201 .
[0071] refer to Fig.18 A dummy gate structure 400 is formed on the substrate 100 , wherein the dummy gate structure 400 spans across the fin 300 , and a top surface of the dummy gate structure 400 is flush with a top surface of the hard mask layer 200 .
[0072] In this embodiment, the dummy gate structure 400 is formed by a conventional process. The dummy gate structure 400 includes a gate dielectric layer (not shown in the figure) and a gate layer. The material of the gate layer is polysilicon.
[0073] refer to Fig.19 , the dummy gate structure 400 is removed, and a gate structure 600 is formed on the substrate 100 , wherein the gate structure 600 spans across the fin 300 .
[0074] In this embodiment, the dummy gate structure 400 is removed by a wet etching process, and the wet etching process uses tetramethylammonium hydroxide (TMAH) as an etching solution to remove the dummy gate structure 400.
[0075] In other embodiments, the dummy gate structure 400 may be removed by dry etching process, using HBr gas or SF6 gas as etching gas.
[0076] In this embodiment, the gate structure 600 is formed by using a conventional process.
[0077] In this embodiment, the gate structure 600 includes a gate dielectric layer 610 and a metal gate 620 .
[0078] In this embodiment, the material of the gate dielectric layer 610 is a high-K dielectric material, and the high-K dielectric material can be HfO2, HfSiO, HfSiON, HfTaO, HfZrO, or ZrO2, etc. The gate dielectric layer 610 can be formed by a chemical vapor deposition process, an atomic layer vapor deposition process, or a sputtering process.
[0079] In this embodiment, a sputtering process is adopted to sputter a pure Hf target in an Ar and O2 atmosphere at a power of 50-100 W and a pressure of 1-10 Pa to deposit a HfO2 gate dielectric layer.
[0080] In this embodiment, the material of the metal gate 620 includes Ti, TiW, TiN or W.
[0081] In the present embodiment, since the dummy gate structure 400 is cut directly by utilizing the hard mask layer 200 on the top of the fin 300 retaining the cutting area 110, when the dummy gate structure 400 is removed to form the gate structure 600, no additional force acts on the gate structure 600, thereby ensuring the formation of a high-quality gate structure 600, thereby improving the quality and performance of the formed semiconductor device.
[0082] A semiconductor device formed by the above method includes: a substrate 100, including a cutting area 110 and a non-cutting area 120; fins 300, which are discretely arranged on the substrate 100; an isolation structure 500, which is located on the substrate 100; a hard mask layer 200, which is located on the top of the fin 300 in the cutting area 110; a gate structure 600, which includes a gate dielectric layer 610 and a metal gate 620, which is located on the substrate 100, spanning the fin 300 and having a top surface flush with the top surface of the hard mask layer 200, wherein the gate dielectric layer 610 covers a portion of the top surface and a portion of the sidewall surface of the fin 300; and a metal gate 620, which covers the gate dielectric layer 610.
[0083] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising a cutting area and a non-cutting area; forming a hard mask layer on the substrate; Using the hard mask layer as a mask, etching a portion of the thickness of the substrate to form discretely arranged fins; removing the hard mask layer on the top of the fin portion in the non-cutting area; A dummy gate structure is formed on the substrate, wherein the dummy gate structure spans the fin portion, and a top surface of the dummy gate structure is flush with a top surface of the hard mask layer.
2. The method for forming a semiconductor device according to claim 1, wherein: The material of the hard mask layer includes silicon nitride, silicon oxide, silicon oxynitride or silicon carbide.
3. The method for forming a semiconductor device according to claim 1, wherein: The process of forming the hard mask layer includes chemical vapor deposition, atomic layer vapor deposition or physical vapor deposition.
4. The method for forming a semiconductor device according to claim 1, wherein: The step of removing the hard mask layer on the fin portion of the non-cutting area includes: forming a photoresist layer on the substrate, wherein an opening of the photoresist layer exposes the hard mask layer on the fin portion of the non-cutting area; using the photoresist layer as a mask; The hard mask layer on the fin portion of the non-cut area is removed.
5. The method for forming a semiconductor device according to claim 1, wherein: A partial thickness of the substrate is etched by dry etching to form discretely arranged fins.
6. The method for forming a semiconductor device according to claim 1, wherein: After forming the dummy gate structure, the method further includes: removing the dummy gate structure; A gate structure is formed on the substrate, the gate structure spanning the fin.
7. The method for forming a semiconductor device according to claim 6, wherein: The gate structure includes a gate dielectric layer and a metal gate.
8. The method for forming a semiconductor device according to claim 1, wherein: An isolation structure is also included, wherein the isolation structure covers a portion of the sidewall of the fin.
9. The method for forming a semiconductor device according to claim 1, wherein: After forming the dummy gate structure, the top surface of the dummy gate structure is polished by chemical mechanical polishing.
10. A semiconductor device formed by the method according to any one of claims 1 to 9, characterized in that: include: A substrate including a cutting area and a non-cutting area; A plurality of fins are discretely arranged on the substrate; a hard mask layer located on top of the fin portion of the cutting area; The dummy gate structure is located on the substrate, spans across the fin and has a top surface flush with the top of the hard mask layer.