A method for manufacturing a dielectric isolation structure based on SOI and a dielectric isolation structure

Abstract

Disclosed is a method for manufacturing a dielectric isolation structure based on SOI and a dielectric isolation structure, the manufacturing method comprising: performing oxidation pretreatment on the upper surface of the top silicon of the SDB silicon wafer to obtain a silicon dioxide layer, and then depositing a silicon nitride layer; depositing a photoresist film on the silicon nitride layer, and using negative photoresist contact exposure; dry etching the silicon nitride layer, wet etching the silicon dioxide layer, and then deep trench etching; degumming; oxidation growth of 1.7-1.8μm thick silicon dioxide on the inner side wall of the groove formed by etching, the air pressure of the growth environment is greater than ten standard atmospheres; low-pressure chemical vapor deposition of polysilicon, and the polysilicon fills the groove formed by etching; surface flattening of the polysilicon; removing the silicon nitride layer, and then field oxidation. The manufacturing process of the present invention is low in complexity, the insulation performance between the high and low voltage areas of the dielectric isolation structure is good, and the breakdown voltage reaches more than 880V.

Description

Technical Field

[0001] The present invention relates to the technical field of SOI, and in particular to a method for manufacturing a dielectric isolation structure based on SOI and the dielectric isolation structure. Background Art

[0002] As a full dielectric isolation technology, SOI (Silicon-On-Insulator) technology effectively overcomes the shortcomings of bulk silicon materials with its unique structure, fully exploits the potential of silicon integrated circuit technology, and is gradually becoming the mainstream technology for manufacturing high-speed, low-power, high-integration and high-reliability ultra-large-scale integrated circuits. SOI technology adopts full dielectric isolation, completely eliminates the parasitic latch effect of CMOS (Complementary Metal Oxide Semiconductor) devices, reduces single-particle flip interfaces, and has excellent resistance to single particles and instantaneous irradiation, allowing SOI chips to work in the worst cosmic ray environment and are widely used in space science. However, the charge capture and interface states generated in the oxide layer by total dose ionization damage will cause the silicon substrate near the isolation oxide layer to be inverted, and form parasitic tube leakage under a certain source-drain bias.

[0003] In addition, in the prior art, some improvements have been made to the structure or material of the dielectric isolation region to suppress the opening of the parasitic channel. However, no matter which method is used, the process complexity is increased to a certain extent, which increases the manufacturing cost of the transistor device. However, for the SOI process of thick silicon film, the full dielectric isolation process between devices is difficult and complex, and the shallow trench isolation technology cannot meet the circuit requirements.

[0004] The prior art lacks a process for manufacturing a dielectric isolation structure based on a SOI process of a thick silicon film. Summary of the invention

[0005] In order to overcome the shortcomings of the prior art, the present invention provides a method for manufacturing a dielectric isolation structure based on SOI and a dielectric isolation structure. The specific technical solution is as follows:

[0006] On the one hand, a method for manufacturing a dielectric isolation structure based on SOI is disclosed, so that the breakdown voltage of the dielectric isolation structure is greater than 880V on SOI with a silicon film thickness of 20 μm, and the method comprises the following steps:

[0007] S1, performing oxidation pretreatment on the upper surface of the top silicon of the SDB silicon wafer to form a 50-55nm silicon dioxide layer, wherein the SDB silicon wafer is made of SOI material;

[0008] S2, depositing a 55-60 nm silicon nitride layer on the silicon dioxide layer;

[0009] S3, depositing a photoresist film on the silicon nitride layer and using negative photoresist contact exposure, wherein the thickness of the film is greater than 1 μm;

[0010] S4, dry-etching the silicon nitride layer, wet-etching the silicon dioxide layer, and then deep-trench etching to form a groove with a width greater than 5 μm and less than 6.2 μm;

[0011] S5, removing the remaining photoresist;

[0012] S6, oxidizing and growing silicon dioxide on the inner sidewall of the groove formed by etching in step S4, wherein the pressure of the growth environment is greater than ten standard atmospheres, and the growth thickness of the silicon dioxide is in the range of 1.7-1.8 μm;

[0013] S7, depositing polysilicon by low-pressure chemical vapor deposition on the surface of the semi-finished structure formed in step S6, wherein the deposition thickness of the polysilicon is greater than 3 μm, and the polysilicon fills the groove formed by the etching;

[0014] S8, planarizing the surface of the polysilicon;

[0015] S9, removing the silicon nitride layer, and then performing field oxidation to form a field oxide layer.

[0016] Furthermore, the SDB silicon wafer comprises a top silicon layer, a buried oxide layer and a substrate from top to bottom, and the groove obtained in step S4 is etched to the buried oxide layer.

[0017] Furthermore, before step S1, a SDB silicon wafer is manufactured, the thickness of the top silicon layer is 20 μm, and the thickness of the buried oxide layer is in the range of 5-6 μm.

[0018] Preferably, in step S8, a CMP process is used to planarize the surface of the polysilicon.

[0019] Preferably, the gas pressure of the growth environment in step S6 is 10.8 standard atmospheres, and the growth thickness range of the silicon dioxide is 1.76 μm.

[0020] Preferably, in step S4, deep trench etching is performed to obtain a trench with a width of 6.1 μm.

[0021] Optionally, the wet etching solution used in the wet etching process in step S4 includes any one of KOH, EPW, and TMAH.

[0022] On the other hand, a SOI-based dielectric isolation structure is disclosed, which is manufactured using the manufacturing method described above.

[0023] Furthermore, the thickness of the top silicon layer on the SOI is 20 μm, and the breakdown voltage of the dielectric isolation structure is greater than 880V.

[0024] The beneficial effects brought by the technical solution of the present invention include:

[0025] (a) Applied in thick silicon film SOI process, the breakdown voltage of the dielectric isolation structure reaches over 880V;

[0026] (b) The dielectric isolation structure has good insulation performance between the high and low voltage areas and low manufacturing process complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 It is a flow chart of a method for manufacturing a dielectric isolation structure based on SOI provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the scheme of the present invention, and to more clearly understand the purpose, technical scheme and advantages of the present invention, the technical scheme in the embodiments of the present invention is clearly and completely described below in combination with specific embodiments and with reference to the accompanying drawings. Obviously, the described embodiments are only embodiments of a part of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without creative work should belong to the scope of protection of the present invention. In addition, the terms "including" and "having" in the specification and claims of the present invention and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0030] In one embodiment of the present invention, a method for manufacturing a dielectric isolation structure based on SOI is provided, so that the breakdown voltage of the dielectric isolation structure is greater than 880V on SOI with a silicon film thickness of 20 μm. Figure 1 As shown, the method comprises the following steps:

[0031] First, a SDB silicon wafer is manufactured. The SDB silicon wafer comprises a top silicon layer, a buried oxide layer and a substrate from top to bottom. The thickness of the top silicon layer is 20 μm, and the thickness of the buried oxide layer is in the range of 5-6 μm.

[0032] S1. Performing oxidation pretreatment on the upper surface of the top silicon of a silicon direct bonding (hereinafter referred to as SDB) silicon wafer to form a 50-55 nm silicon dioxide layer, wherein the SDB silicon wafer is made of SOI material;

[0033] S2, depositing a 55-60 nm silicon nitride layer on the silicon dioxide layer;

[0034] S3, depositing a photoresist film on the silicon nitride layer and using negative photoresist contact exposure, wherein the thickness of the film is greater than 1 μm;

[0035] S4, dry-etching the silicon nitride layer, wet-etching the silicon dioxide layer, and then deep-trench etching to form a groove with a width greater than 5 μm and less than 6.2 μm (preferably 6.1 μm), wherein the groove is etched to the buried oxide layer.

[0036] Specifically, by adopting a wet etching process, the expected dielectric isolation groove depth can be obtained by controlling the size of the etching window and the etching time, thereby achieving the simultaneous completion of the full dielectric isolation and partial isolation structure of the thick silicon film SOI integrated circuit, improving the integration of the integrated circuit, reducing the number of photolithography times, and the process is simple and controllable, with little damage. The wet etching liquid used in the wet etching process includes any one of KOH (potassium hydroxide), EPW (ethylenediamine and catechol), and TMAH (tetramethylammonium hydroxide).

[0037] S5, removing the remaining photoresist;

[0038] S6. Oxidatively grow silicon dioxide on the inner sidewalls of the grooves formed by etching in step S4, wherein the pressure of the growth environment is greater than ten standard atmospheres, and the growth thickness of the silicon dioxide is in the range of 1.7-1.8 μm (preferably 1.76 μm).

[0039] One of the core inventive points of the present invention is that a high pressure environment of 10.8 standard atmospheres is preferably used to oxidize and grow silicon dioxide on the inner sidewalls of the grooves formed by etching, which plays a key role in improving the breakdown voltage of the dielectric isolation structure.

[0040] S7, forming low pressure chemical vapor deposition (LPCVD) polysilicon on the surface of the semi-finished structure formed in step S6, wherein the deposition thickness of the polysilicon is greater than 3 μm, and the polysilicon fills the groove formed by etching;

[0041] The full dielectric isolation trench is filled with polysilicon, which avoids the long-term high-temperature annealing of the traditional isolation process, reduces the impact on the total dose reinforcement impurity diffusion, and improves the device's ability to resist total dose radiation; this isolation process has little impact on other process steps and can be completed before the device's well injection or before the gate oxide.

[0042] S8, planarizing the surface of the polysilicon.

[0043] Preferably, the surface of the polysilicon is planarized by using a chemical mechanical polishing (CMP) process. CMP is to press the workpiece to be polished onto a rotating elastic grinding pad, supply a corrosive processing fluid to the workpiece, and while the workpiece is being corroded (chemically), a polishing material of ultrafine abrasive particles (diameter below 100 nm) is simultaneously supplied to perform a selective polishing operation (mechanically) on the convex portion of the workpiece. Here, CMP is introduced into the surface shaping of the dielectric isolation structure to reduce the height of the field oxygen tip angle and increase the breakdown voltage of the dielectric isolation.

[0044] S9, removing the silicon nitride layer, and then performing field oxidation to form a field oxide layer.

[0045] On the other hand, a SOI-based dielectric isolation structure is disclosed, which is manufactured using the manufacturing method described above.

[0046] Furthermore, the thickness of the top silicon layer on the SOI is 20 μm, and the breakdown voltage of the dielectric isolation structure is greater than 880V.

[0047] The dielectric isolation method of the present invention is applied to the thick silicon film SOI process, and adopts alkaline wet etching to simultaneously realize dielectric isolation grooves of different depths, thereby realizing full dielectric isolation between devices, improving the integration of circuits, reducing the number of photolithography times, and reducing process manufacturing costs. At the same time, the process is simple and has low difficulty. The isolation process adopted by the present invention can avoid long-term high-temperature annealing of the isolation structure. In the application of radiation-resistant circuits, it can reduce the impact on the diffusion of total dose reinforcement impurities, improve the device's ability to resist total dose radiation, and at the same time, full dielectric isolation eliminates the parasitic latch effect of CMOS devices.

[0048] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a dielectric isolation structure based on SOI, characterized in that: The method is to achieve a breakdown voltage of a dielectric isolation structure greater than 880V on a SOI with a silicon film thickness of 20 μm, the method comprising the following steps: Prefabricate an SDB silicon wafer, wherein the SDB silicon wafer comprises a top silicon layer, a buried oxide layer and a substrate from top to bottom, wherein the thickness of the top silicon layer is 20 μm, and the thickness of the buried oxide layer is in the range of 5-6 μm; S1, performing oxidation pretreatment on the upper surface of the top silicon of the SDB silicon wafer to form a 50-55nm silicon dioxide layer, wherein the SDB silicon wafer is made of SOI material; S2, depositing a 55-60 nm silicon nitride layer on the silicon dioxide layer; S3, depositing a photoresist film on the silicon nitride layer and using negative photoresist contact exposure, wherein the thickness of the film is greater than 1 μm; S4, dry-etching the silicon nitride layer, wet-etching the silicon dioxide layer, and then deep-trench etching to form a groove with a width greater than 5 μm and less than 6.2 μm, wherein the groove is etched to the buried oxide layer; S5, removing the remaining photoresist; S6, oxidizing and growing silicon dioxide on the inner sidewall of the groove formed by etching in step S4, the pressure of the growth environment is 10.8 standard atmospheric pressure, and the growth thickness of the silicon dioxide is in the range of 1.7-1.8 μm; S7, depositing polysilicon by low-pressure chemical vapor deposition on the surface of the semi-finished structure formed in step S6, wherein the deposition thickness of the polysilicon is greater than 3 μm, and the polysilicon fills the groove formed by etching; S8, planarizing the surface of the polysilicon by using a CMP process; S9, removing the silicon nitride layer, and then performing field oxidation to form a field oxide layer.

2. The method for manufacturing a dielectric isolation structure based on SOI according to claim 1, characterized in that: The growth thickness of the silicon dioxide in step S6 is in the range of 1.76 μm.

3. The method for manufacturing a dielectric isolation structure based on SOI according to claim 1, characterized in that: In step S4, deep trench etching is performed to obtain a trench with a width of 6.1 μm.

4. The method for manufacturing a dielectric isolation structure based on SOI according to claim 1, characterized in that: The wet etching solution used in the wet etching process in step S4 includes any one of KOH, EPW, and TMAH.

5. A dielectric isolation structure based on SOI, characterized in that: The method is prepared by any one of claims 1 to 4.

6. The SOI-based dielectric isolation structure according to claim 5, characterized in that: The thickness of the top silicon layer on the SOI is 20 μm, and the breakdown voltage of the dielectric isolation structure is greater than 880V.

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