Epitaxial channel field effect transistor device and preparation method thereof

Abstract

The invention provides an epitaxial channel field effect transistor device and a preparation method thereof. The preparation method comprises the following steps: sequentially forming a first sacrificial layer, a second sacrificial layer and a third sacrificial layer on a substrate; forming a dummy gate groove and a channel; etching part of the third sacrificial layer and all the second sacrificial layer; forming a control gate; removing the third sacrificial layer; forming a first side wall, a source electrode, a source electrode metal interconnection and a source electrode isolation layer; removing the substrate and the first sacrificial layer; and forming a second side wall, a drain electrode, drain electrode metal interconnection and a drain electrode isolation layer. The gate length of the transistor is accurately defined through the growth thickness of the second sacrificial layer, and the channel is protected from being influenced by the subsequent process through the first sacrificial layer and the third sacrificial layer, so that the accurate control of the channel length is realized, and the process deviation in the preparation process of the vertical field effect transistor is effectively reduced, thereby reducing the process complexity and simultaneously improving the production efficiency of the vertical field effect transistor. The device performance of the field effect transistor is ensured, and the problems that an existing vertical field effect transistor is poor in device performance and complex in preparation process are solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to an epitaxial channel field effect transistor device and a preparation method thereof. Background Art

[0002] Field Effect Transistor (FET) has the advantages of high input resistance, low noise, low power consumption, large dynamic range, easy integration, no secondary breakdown phenomenon, and wide safe operating area. It is widely used in integrated circuit design.

[0003] With the continuous development of the integrated circuit industry, the small size effect caused by the reduction of the size of the traditional planar MOSFET (metal-oxide semiconductor field effect transistor, metal-oxide semiconductor FET) has become more and more prominent, thus limiting the further integration of integrated circuits. In order to solve the small size effect of the traditional planar MOSFET, the researchers proposed the vertical field effect transistor (Vertical Field Effect Transistor, VFET) with its unique structural design. By vertically erecting the nanowire / nanosheet channel structure on the substrate, the source / drain (S / D) region is formed above and below the nanowire / nanosheet channel structure, respectively, thereby transferring the gate length, source and drain volume and other dimensional parameters of the traditional planar MOSFET to the vertical direction, thereby further reducing the area of ​​the device in the planar direction, greatly improving the device's integration.

[0004] At present, VFET devices generally adopt the method of first depositing a sacrificial silicon layer and then etching to define the channel length in the channel preparation. However, the deposition thickness and etching depth of the sacrificial silicon layer are difficult to accurately control, resulting in uneven channel length, thus affecting the performance of the device. Moreover, the top-down preparation scheme currently used makes the top source / drain and the bottom source / drain of the VFET device structurally asymmetric, which in turn causes differences in the quality of the two regions during the preparation process. The upward lead-out of the bottom source / drain brings higher RC delay and isolation requirements, which has an adverse effect on the overall performance and reliability of the device. In addition, the existing VFET device structure is relatively complex and the manufacturing process is relatively cumbersome, which limits the realization of its large-scale integrated application. Summary of the invention

[0005] The object of the present invention is to provide an epitaxial channel field effect transistor device and a method for preparing the same, so as to solve the problems of poor performance and complicated preparation process of the existing vertical field effect transistor device.

[0006] In order to solve the above technical problems, the present invention provides a method for preparing an epitaxial channel field effect transistor device, comprising: providing a substrate; forming a first sacrificial layer, a second sacrificial layer and a third sacrificial layer in sequence on the substrate; Etching to form a dummy gate trench, the bottom of the dummy gate trench exposing the substrate; forming a channel in the dummy gate trench, wherein a surface of the channel is flush with a surface of the third sacrificial layer; etching a portion of the third sacrificial layer and removing the entire second sacrificial layer to form a pit between the first sacrificial layer and the third sacrificial layer; forming a control gate in the pit; removing the third sacrificial layer; forming a first sidewall on both sides of the trench; forming a source electrode on a surface of the channel; Forming a source metal interconnection on the top of the source, and forming a source isolation layer on the surface of the first sidewall and around the source; removing the substrate and the first sacrificial layer; forming a second sidewall on both sides of the trench; forming a drain on a surface of the channel; A drain metal interconnection is formed on the top of the drain, and a drain isolation layer is formed on the surface of the second sidewall and around the drain.

[0007] Optionally, in the method for preparing the epitaxial channel field effect transistor device, the etching selectivity of the second sacrificial layer is greater than the etching selectivity of the first sacrificial layer, and greater than the etching selectivity of the third sacrificial layer.

[0008] Optionally, in the method for preparing the epitaxial channel field effect transistor device, the materials of the first sacrificial layer, the second sacrificial layer and the third sacrificial layer are SiGe; the Ge content of the second sacrificial layer is higher than the Ge content of the first sacrificial layer, and higher than the Ge content of the third sacrificial layer; the Ge content of the first sacrificial layer is consistent with the Ge content of the third sacrificial layer.

[0009] Optionally, in the method for preparing the epitaxial channel field effect transistor device, the method for etching to form the dummy gate trench comprises: A dummy gate groove region is defined on the surface of the third sacrificial layer using a photoresist; Using a photolithography process, photolithography is performed on the third sacrificial layer, the second sacrificial layer and the first sacrificial layer in the dummy gate trench region until the substrate is exposed, so as to form a dummy gate trench; Remove the photoresist.

[0010] Optionally, in the method for preparing the epitaxial channel field effect transistor device, the method for forming a channel in the dummy gate trench includes: Silicon is epitaxially grown in the dummy gate trench by using an epitaxial growth process to form a silicon channel.

[0011] Optionally, in the method for preparing the epitaxial channel field effect transistor device, the method of etching part of the third sacrificial layer and removing the entire second sacrificial layer to form a pit between the first sacrificial layer and the third sacrificial layer includes: A pit area is defined on the surface of the third sacrificial layer using a photoresist; Photolithography the third sacrificial layer and a portion of the second sacrificial layer in the pit area using a photolithography process; Removing photoresist; The entire second sacrificial layer is removed.

[0012] Optionally, in the method for preparing the epitaxial channel field effect transistor device, the method for forming the control gate in the pit includes: Using an epitaxial growth process, an interface oxide layer is formed in the pit, wherein the interface oxide layer covers the first sacrificial layer, the channel sidewalls and the lower surface of the third sacrificial layer; Using an epitaxial growth process, a dielectric layer is formed on the surface of the interface oxide layer; Forming a gate metal layer in the pit by using an epitaxial growth process, wherein a surface of the gate metal layer is flush with a surface of the third sacrificial layer; The interface oxide layer, the dielectric layer and the gate metal layer constitute a control gate.

[0013] Optionally, in the method for preparing the epitaxial channel field effect transistor device, the dielectric layer is a high-k dielectric layer.

[0014] Optionally, in the method for preparing the epitaxial channel field effect transistor device, a chemical mechanical polishing process is used to make the surface of the channel flush with the surface of the third sacrificial layer, and at the same time, make the surface of the gate metal layer flush with the surface of the third sacrificial layer.

[0015] Optionally, in the method for preparing the epitaxial channel field effect transistor device, the material of the source and the drain is Si, SiGe, SiC or other III-V group or II-VI group compound semiconductor materials.

[0016] Optionally, in the method for preparing the epitaxial channel field effect transistor device, the source and the drain are doped with the same ions, and the doping concentration is heavy doping.

[0017] Optionally, in the method for preparing the epitaxial channel field effect transistor device, the material of the first sidewall spacer and the second sidewall spacer is an insulating low-k dielectric material.

[0018] Optionally, in the method for preparing the epitaxial channel field effect transistor device, the material of the first sidewall spacer and the second sidewall spacer is silicon nitride, SiCN or SiOCN.

[0019] Optionally, in the method for preparing the epitaxial channel field effect transistor device, the method further comprises: A through hole is formed in the source isolation layer and the drain isolation layer, and the bottom of the through hole exposes the gate metal layer.

[0020] In order to solve the above technical problems, the present invention also provides an epitaxial channel field effect transistor device, which is prepared using the preparation method of the epitaxial channel field effect transistor device as described in any of the above items, and the epitaxial channel field effect transistor device includes a drain, a channel and a source connected in sequence from top to bottom; control gates are formed on both sides of the channel.

[0021] Optionally, in the epitaxial channel field effect transistor device, the control gate includes an interface oxide layer, a dielectric layer and a gate metal layer; the interface oxide layer, the dielectric layer and the gate metal layer are formed in sequence on both sides of the channel from the inside to the outside; the two ends of the interface oxide layer and the dielectric layer are in contact with the source and the drain respectively; the gate metal layer is isolated from the source by a first side wall, and is isolated from the drain by a second side wall.

[0022] Optionally, in the epitaxial channel field effect transistor device, the channel is a nanowire channel or a nanosheet channel.

[0023] The epitaxial channel field effect transistor device and the preparation method thereof provided by the present invention include: providing a substrate; forming a first sacrificial layer, a second sacrificial layer and a third sacrificial layer on the substrate in sequence; etching to form a dummy gate groove, the bottom of the dummy gate groove exposing the substrate; forming a channel in the dummy gate groove, the surface of the channel being flush with the surface of the third sacrificial layer; etching part of the third sacrificial layer and removing all of the second sacrificial layer to form a pit between the first sacrificial layer and the third sacrificial layer; forming a control gate in the pit; removing the third sacrificial layer; forming a first side wall on both sides of the channel; forming a source on the surface of the channel; forming a source metal interconnection on the top of the source, and forming a source isolation layer on the surface of the first side wall and around the source; removing the substrate and the first sacrificial layer; forming a second side wall on both sides of the channel; forming a drain on the surface of the channel; forming a drain metal interconnection on the top of the drain, and forming a drain isolation layer on the surface of the second side wall and around the drain. The gate length of the transistor is precisely defined by the growth thickness of the second sacrificial layer, and the channel is protected from being affected in subsequent processes by the first and third sacrificial layers, thereby achieving precise control of the channel length and effectively reducing the process deviation in the preparation process of the vertical field effect transistor, thereby reducing the complexity of the preparation process while ensuring the device performance of the vertical field effect transistor, solving the problem of poor device performance and complex preparation process of existing vertical field effect transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A flow chart of a method for preparing an epitaxial channel field effect transistor device provided in this embodiment; Figures 2A to 2U A schematic diagram of the structure of an epitaxial channel field effect transistor device corresponding to each step in the preparation method provided in this embodiment; Figure 3 A schematic diagram of the three-dimensional structure of an epitaxial channel field effect transistor device provided in this embodiment; The descriptions of the reference numerals are as follows: 100-substrate; 110-first sacrificial layer; 120-second sacrificial layer; 130-third sacrificial layer; 140-dummy gate groove; 141-channel; 150-pit; 160-interface oxide layer; 170-dielectric layer; 180-gate metal layer; 190-sidewall dielectric layer; 191-first sidewall; 200-source; 210-source metal interconnection; 220-source isolation layer; 230-second sidewall; 240-drain; 250-drain metal interconnection; 260-drain isolation layer; 270-through hole. DETAILED DESCRIPTION

[0025] The epitaxial channel field effect transistor device and the method for preparing the same proposed by the present invention are further described in detail below in combination with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the accompanying drawings is often a part of the actual structure. In particular, the emphasis of each accompanying drawing is different, and sometimes different proportions are used.

[0026] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] This embodiment provides a method for preparing an epitaxial channel field effect transistor device, such as Figure 1 As shown, including: S01, providing a substrate; S02, sequentially forming a first sacrificial layer, a second sacrificial layer and a third sacrificial layer on the substrate; S03, etching to form a dummy gate trench, wherein the bottom of the dummy gate trench exposes the substrate; S04, forming a channel in the dummy gate trench, wherein a surface of the channel is flush with a surface of the third sacrificial layer; S05, etching a portion of the third sacrificial layer and removing the entire second sacrificial layer to form a pit between the first sacrificial layer and the third sacrificial layer; S06, forming a control gate in the pit; S07, removing the third sacrificial layer and forming first sidewall spacers on both sides of the trench; S08, forming a source electrode on the surface of the channel; S09, forming a source metal interconnection on the top of the source, and forming a source isolation layer on the surface of the first sidewall and around the source; S10, removing the substrate and the first sacrificial layer, and forming second sidewall spacers on both sides of the trench; S11, forming a drain on the channel surface; S12, forming a drain metal interconnection on the top of the drain, and forming a drain isolation layer on the surface of the second sidewall and around the drain.

[0028] The method for preparing an epitaxial channel field effect transistor device provided in this embodiment accurately defines the gate length of the transistor by the growth thickness of the second sacrificial layer, and protects the channel from being affected in subsequent processes by the first sacrificial layer and the third sacrificial layer, thereby achieving precise control of the channel length and effectively reducing the process deviation in the preparation process of the vertical field effect transistor, thereby reducing the complexity of the preparation process while ensuring the device performance of the vertical field effect transistor, and solving the problem of poor performance and complex preparation process of existing vertical field effect transistor devices.

[0029] The method for preparing the epitaxial channel field effect transistor device provided in this embodiment adopts the gate-around technology, and the gate structure is surrounded by the sidewall of the nanowire / nanosheet channel to achieve all-round gate control capability and has excellent electrostatic performance. The gate-around technology combined with the vertical field effect transistor can greatly improve the integration and device performance of the transistor.

[0030] The method for preparing the epitaxial channel field effect transistor device provided in this embodiment adopts back power supply and back signal technology, and utilizes the structural characteristics of the vertical gate field effect transistor that the source / drain region is located at the bottom of the device. Power routing and signal routing are realized by leading out metal interconnections at the source and drain of the vertical field effect transistor, which effectively alleviates the additional area sacrifice caused by wiring rules in the front routing, allows a wider power line width, reduces the RC delay of the back end, and improves the chip performance while reducing the chip area.

[0031] Specifically, in this embodiment, Figure 2A As shown, step S01, providing a substrate 100. Specifically, the substrate 100 may be a silicon substrate. Of course, in practical applications, substrates of other materials may also be selected, and the present application does not limit this.

[0032] Furthermore, in this embodiment, if Figure 2B As shown, in step S02 , a first sacrificial layer 110 , a second sacrificial layer 120 and a third sacrificial layer 130 are sequentially formed on the substrate 100 .

[0033] Specifically, in this embodiment, the etching selectivity of the second sacrificial layer 120 is greater than the etching selectivity of the first sacrificial layer 110, and greater than the etching selectivity of the third sacrificial layer 130. In this way, it is convenient to form a pit structure in subsequent processes.

[0034] In order to effectively distinguish the three sacrificial layers and reduce the process complexity as much as possible, in practical applications, the materials of the first sacrificial layer 110, the second sacrificial layer 120 and the third sacrificial layer 130 are SiGe; the Ge content of the second sacrificial layer 120 is higher than the Ge content of the first sacrificial layer 110, and higher than the Ge content of the third sacrificial layer 130; the Ge content of the first sacrificial layer 110 is consistent with the Ge content of the third sacrificial layer 130. For example, the material of the first sacrificial layer 110 is SiGe. 0.7 Ge 0.3 The material of the second sacrificial layer 120 is Si 0.5 Ge 0.5 The material of the third sacrificial layer 130 is Si 0.7 Ge 0.3 .

[0035] Furthermore, in this embodiment, if Figure 2C As shown, in step S03 , a dummy gate trench 140 is formed by etching, and the bottom of the dummy gate trench 140 exposes the substrate 100 .

[0036] Specifically, in order to ensure process accuracy, a photolithography process can be used: first, a dummy gate groove area is defined on the surface of the third sacrificial layer 130 with photoresist; then, the third sacrificial layer 130, the second sacrificial layer 120 and the first sacrificial layer 110 in the dummy gate groove area are photolithographically processed until the substrate 100 is exposed to form a dummy gate groove 140; finally, the photoresist is removed.

[0037] During the photolithography process, a portion of the substrate 100 may be etched so that the surface of the substrate 100 at the bottom of the dummy gate trench 140 is slightly lower than the surface height of the original substrate 100 .

[0038] Furthermore, in this embodiment, if Figure 2D As shown, in step S04 , a channel 141 is formed in the dummy gate trench 140 , and a surface of the channel 141 is flush with a surface of the third sacrificial layer 130 .

[0039] Specifically, an epitaxial growth process may be used to achieve: epitaxial growth of silicon in the dummy gate trench 140 to form a silicon channel 141 .

[0040] In practical applications, in order to reduce process complexity, after forming the channel 141 , grinding may not be performed first to retain the current shape of the channel 141 , and then grind together in a subsequent process so that the surface of the channel 141 is flush with the surface of the third sacrificial layer 130 .

[0041] Furthermore, in this embodiment, in step S05 , a portion of the third sacrificial layer 130 is etched, and all of the second sacrificial layer 120 is removed, so as to form a pit 150 between the first sacrificial layer 110 and the third sacrificial layer 130 .

[0042] Specifically, in order to ensure the process accuracy, the photolithography process can also be used: first, a pit area is defined on the surface of the third sacrificial layer 130 using photoresist; then, as shown in FIG. Figure 2E As shown, the third sacrificial layer 130 and part of the second sacrificial layer 120 in the pit area are photolithographically processed; then, the photoresist is removed; finally, as shown in FIG. Figure 2F As shown, the entire second sacrificial layer 120 is removed, thereby obtaining a pit 150 .

[0043] At this time, the pit 150 has the first sacrificial layer 110 as the bottom, the channel 141 as the sidewall, and the third sacrificial layer 130 as the top, and has an open pit structure at the top. In addition, the second sacrificial layer 120 no longer exists in the semiconductor device at this time. Thanks to the etching selectivity of the three sacrificial layers, after the second sacrificial layer 120 is completely removed, the first sacrificial layer 110 and the third sacrificial layer 130 are retained, thereby ensuring that the channel 141 is not affected in the subsequent process, achieving precise control of the channel length, and effectively reducing the process deviation in the preparation process of the vertical field effect transistor.

[0044] Furthermore, in this embodiment, in step S06 , a control gate is formed in the pit 150 .

[0045] Specifically, in this embodiment, the control gate can be formed by using an epitaxial growth process: first, as Figure 2G As shown, an interfacial oxide layer 160 is formed in the pit 150 by using an epitaxial growth process, and the interfacial oxide layer 160 covers the first sacrificial layer 110, the sidewall of the channel 141 and the lower surface of the third sacrificial layer 130; then, as shown Figure 2H As shown, a dielectric layer 170 is formed on the surface of the interface oxide layer 160 by using an epitaxial growth process; finally, as shown Fig.2I As shown, a gate metal layer 180 is formed in the pit 150 by using an epitaxial growth process, and the surface of the gate metal layer 180 is flush with the surface of the third sacrificial layer 130. The interface oxide layer 160, the dielectric layer 170 and the gate metal layer 180 constitute a control gate.

[0046] In this embodiment, the interface oxide layer 160 can be made of silicon oxide or other materials. The dielectric layer 170 is a high-k dielectric layer. Wherein, k refers to the dielectric constant, and the high-k dielectric refers to a dielectric with a dielectric constant k greater than 3.9, including but not limited to hafnium dioxide, zirconium oxide, aluminum oxide, barium titanate, etc. The gate metal layer 180 can be made of metal or semiconductor material.

[0047] In practical applications, due to the influence of the process, the formed gate metal layer 180 may be higher than the surface of the third sacrificial layer 130. At this time, a chemical mechanical polishing process may be used to make the surface of the gate metal layer 180 flush with the surface of the third sacrificial layer 130. If polishing and leveling are not performed after the channel 141 is formed, a chemical mechanical polishing process may also be used in this step to make the surface of the channel 141 flush with the surface of the third sacrificial layer 130. That is, only one chemical mechanical polishing process is performed to make the surface of the channel 141, the surface of the gate metal layer 180 and the surface of the third sacrificial layer 130 flush, thereby effectively reducing the complexity of the process.

[0048] Furthermore, in this embodiment, in step S07 , the third sacrificial layer 130 is removed, and first spacers 191 are formed on both sides of the trench 141 .

[0049] Specifically, the first sidewall spacer 191 may be formed by using a deposition process and an etching back process: first, Figure 2J As shown, the third sacrificial layer 130 is removed, for example, the third sacrificial layer 130 can be removed by an etching process; then, as shown Figure 2K As shown, a spacer dielectric layer 190 is deposited on the surface of the semiconductor device, and the spacer dielectric layer 190 covers the channel 141, the interface oxide layer 160 and the gate metal layer 180; finally, as shown Figure 2L As shown, the spacer dielectric layer 190 is etched back to expose the channel 141 , thereby obtaining a first spacer 191 .

[0050] In practical applications, the material of the first sidewall 191 is an insulating low-k dielectric material, wherein k refers to the dielectric constant. The insulating low-k dielectric refers to a dielectric with a dielectric constant k less than 3.9 and insulating properties, such as silicon nitride, SiCN or SiOCN.

[0051] Of course, in practical applications, a photolithography process may be used to form the first sidewall 191. In this embodiment, by selecting the back-etching process when preparing the first sidewall 191, the self-alignment of the channel structure can be achieved, and the requirement for overlay accuracy can be reduced; at the same time, the photolithography steps can be reduced, thereby simplifying the process and reducing the difficulty of process integration.

[0052] It should be noted that if the photolithography process is adopted, the thickness of the first sidewall 191 can be guaranteed to be consistent with the thickness of the sidewall dielectric layer 190; and if the back-etching process is adopted, the thickness of the first sidewall 191 will be less than the thickness of the sidewall dielectric layer 190. Therefore, when the back-etching process is adopted, in order to ensure that the height of the first sidewall 191 in the vertical field effect transistor meets the design requirements, when the sidewall dielectric layer 190 is formed, its thickness should be greater than the designed height of the first sidewall 191.

[0053] Furthermore, in this embodiment, if Figure 2M As shown, in step S08 , a source 200 is formed on the surface of the channel 141 .

[0054] Specifically, an epitaxial growth process may be used to form the source 200 on the surface of the channel 141. The source 200 may be made of Si, SiGe, SiC or other III-V or II-VI compound semiconductor materials.

[0055] And, in this embodiment, if Figure 2N As shown, in step S09 , a source metal interconnection 210 is formed on the top of the source 200 , and a source isolation layer 220 is formed on the surface of the first spacer 191 and around the source 200 .

[0056] Specifically, a deposition process and an etching process may be selected to sequentially form the source metal interconnect 210 and the source isolation layer 220 . The specific implementation method is well known to those skilled in the art and will not be described in detail in this application.

[0057] In practical applications, after this step, a through hole 270 may be formed in the source isolation layer 220, and the bottom of the through hole 270 exposes the gate metal layer 180. Fig.2O As shown, the through hole 270 can be formed by using a photolithography process, and the specific process is well known to those skilled in the art, and will not be described in detail in this application.

[0058] Furthermore, in this embodiment, in step S10 , the substrate 100 and the first sacrificial layer 110 are removed, and second spacers 230 are formed on both sides of the trench 141 .

[0059] In practical applications, in order to facilitate the implementation of the process, the semiconductor device can be turned over first, and the source metal interconnect 210 and the source isolation layer 220 are supported on the carrier silicon wafer so that the substrate 100 is located on the top. Figure 2P In this way, the reliable preparation of the second sidewall and the drain originally located at the bottom can be ensured, and at the same time, the arrangement and preparation of the back power line and the back signal line can be met, thereby further reducing the device area and improving the integration.

[0060] Afterwards, if Figure 2Q As shown, the substrate 100 and the first sacrificial layer 110 are removed by an etching process. Figure 2R As shown, similar to the formation of the first sidewall 191, the second sidewall 230 is formed on both sides of the channel 141. In this embodiment, by selecting the same back etching process when preparing the second sidewall 230, the self-alignment of the channel structure can be achieved, and the requirement for overlay accuracy can be reduced; at the same time, the number of photolithography steps can be reduced, thereby simplifying the process and reducing the difficulty of process integration.

[0061] In practical applications, the material of the second sidewall spacer 230 can be consistent with the material of the first sidewall spacer 191 , that is, an insulating low-k dielectric material such as silicon nitride, SiCN or SiOCN.

[0062] Further, in this embodiment, step S11 is similar to step S08, such as Figure 2S As shown, a drain 240 is formed on the surface of the channel 141 .

[0063] In order to reduce the process complexity, in this embodiment, the material of the drain 240 is consistent with the material of the source 200, and can be Si, SiGe, SiC or other III-V group, II-VI group compound semiconductor materials. For example, in an N-type device, the material of the source 200 and the drain 240 is SiC; in a P-type device, the material of the source 200 and the drain 240 is SiGe.

[0064] In practical applications, the source 200 and the drain 240 are doped with the same ions, and the doping concentration is heavy doping (1e16 cm-3~1e22 cm-3). For example, in an N-type device, the source 200 and the drain 240 are doped with As (arsenic) ions, and the doping concentration is 5e20 cm-3; in a P-type device, the source 200 and the drain 240 are doped with B (boron) ions, and the doping concentration is 5e20 cm-3.

[0065] And, in this embodiment, step S12 is similar to step S09, such as Figure 2T As shown, a drain metal interconnection 250 is formed on the top of the drain 240 , and a drain isolation layer 260 is formed on the surface of the second spacer 230 and around the drain 240 .

[0066] In practical applications, after this step, a through hole 270 may be formed in the drain isolation layer 260, and the bottom of the through hole 270 exposes the gate metal layer 180. Figure 2U As shown, the through hole 270 can be formed by using a photolithography process, and the specific process is well known to those skilled in the art, and will not be described in detail in this application.

[0067] This embodiment also provides an epitaxial channel field effect transistor device, which is prepared by the method for preparing the epitaxial channel field effect transistor device as described above. Figure 3 As shown, the epitaxial channel field effect transistor device includes a drain 240 , a channel 141 and a source 200 which are sequentially connected from top to bottom; control gates are formed on both sides of the channel 141 .

[0068] Specifically, in the present embodiment, the control gate includes an interface oxide layer 160, a dielectric layer 170 and a gate metal layer 180; the interface oxide layer 160, the dielectric layer 170 and the gate metal layer 180 are sequentially formed on both sides of the channel 141 from the inside to the outside; the two ends of the interface oxide layer 160 and the dielectric layer 170 are in contact with the source 200 and the drain 240 respectively; the gate metal layer 180 is isolated from the source 200 by a first side wall 191, and is isolated from the drain 240 by a second side wall 230.

[0069] In this way, by utilizing the surround gate technology and surrounding the control gate structure around the sidewalls of the channel, all-round gate control capability is achieved, thereby enabling the vertical field effect transistor to have superior electrostatic performance and greatly improving the integration and device performance of the vertical field effect transistor.

[0070] Furthermore, in this embodiment, the channel 141 is a nanowire channel or a nanosheet channel.

[0071] In practical applications, the epitaxial channel field effect transistor can also form a source metal interconnection on the top of the source 200, and form a source isolation layer on the surface of the first side wall 191 and around the source 200; form a drain metal interconnection on the top of the drain 240, and form a drain isolation layer on the surface of the second side wall 230 and around the drain 240.

[0072] In this way, the back power supply and back signal technology can be used, and the structural characteristics of the source / drain region of the vertical gate field effect transistor being located at the bottom of the device can be utilized. The power routing and signal routing can be realized by leading out metal interconnections at the source and drain of the epitaxial channel field effect transistor, which effectively alleviates the additional area sacrifice caused by the wiring rules in the front routing, allows a wider power line width, reduces the RC delay at the back end, and improves the chip performance while reducing the chip area.

[0073] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0074] The epitaxial channel field effect transistor device and the preparation method thereof provided in the present embodiment include: providing a substrate; forming a first sacrificial layer, a second sacrificial layer and a third sacrificial layer on the substrate in sequence; etching to form a dummy gate groove, the bottom of the dummy gate groove exposing the substrate; forming a channel in the dummy gate groove, the surface of the channel is flush with the surface of the third sacrificial layer; etching part of the third sacrificial layer and removing all of the second sacrificial layer to form a pit between the first sacrificial layer and the third sacrificial layer; forming a control gate in the pit; removing the third sacrificial layer; forming a first side wall on both sides of the channel; forming a source on the surface of the channel; forming a source metal interconnection on the top of the source, and forming a source isolation layer on the surface of the first side wall and around the source; removing the substrate and the first sacrificial layer; forming a second side wall on both sides of the channel; forming a drain on the surface of the channel; forming a drain metal interconnection on the top of the drain, and forming a drain isolation layer on the surface of the second side wall and around the drain. The gate length of the transistor is precisely defined by the growth thickness of the second sacrificial layer, and the channel is protected from being affected in subsequent processes by the first and third sacrificial layers, thereby achieving precise control of the channel length and effectively reducing the process deviation in the preparation process of the vertical field effect transistor, thereby reducing the complexity of the preparation process while ensuring the device performance of the vertical field effect transistor, solving the problem of poor device performance and complex preparation process of existing vertical field effect transistors.

[0075] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for preparing an epitaxial channel field effect transistor device, characterized in that: include: providing a substrate; forming a first sacrificial layer, a second sacrificial layer and a third sacrificial layer in sequence on the substrate; Etching to form a dummy gate trench, the bottom of the dummy gate trench exposing the substrate; forming a channel in the dummy gate trench, wherein a surface of the channel is flush with a surface of the third sacrificial layer; etching a portion of the third sacrificial layer and removing the entire second sacrificial layer to form a pit between the first sacrificial layer and the third sacrificial layer; forming a control gate in the pit; removing the third sacrificial layer and forming first sidewall spacers on both sides of the trench; forming a source electrode on a surface of the channel; Forming a source metal interconnection on the top of the source, and forming a source isolation layer on the surface of the first sidewall and around the source; removing the substrate and the first sacrificial layer, and forming second sidewalls on both sides of the trench; forming a drain on a surface of the channel; A drain metal interconnection is formed on the top of the drain, and a drain isolation layer is formed on the surface of the second sidewall and around the drain.

2. The method for preparing an epitaxial channel field effect transistor device according to claim 1, characterized in that: The etching selectivity of the second sacrificial layer is greater than the etching selectivity of the first sacrificial layer, and greater than the etching selectivity of the third sacrificial layer.

3. The method for preparing an epitaxial channel field effect transistor device according to claim 2, characterized in that: The materials of the first sacrificial layer, the second sacrificial layer and the third sacrificial layer are SiGe; the Ge content of the second sacrificial layer is higher than the Ge content of the first sacrificial layer and higher than the Ge content of the third sacrificial layer; the Ge content of the first sacrificial layer is consistent with the Ge content of the third sacrificial layer.

4. The method for preparing an epitaxial channel field effect transistor device according to claim 1, characterized in that: The method for etching the dummy gate trench comprises: A dummy gate groove region is defined on the surface of the third sacrificial layer using a photoresist; Using a photolithography process, photolithography is performed on the third sacrificial layer, the second sacrificial layer and the first sacrificial layer in the dummy gate trench region until the substrate is exposed, so as to form a dummy gate trench; Remove the photoresist.

5. The method for preparing an epitaxial channel field effect transistor device according to claim 1, characterized in that: The method for forming a channel in a dummy gate trench comprises: Silicon is epitaxially grown in the dummy gate trench by using an epitaxial growth process to form a silicon channel.

6. The method for preparing an epitaxial channel field effect transistor device according to claim 1, characterized in that: The method of etching part of the third sacrificial layer and removing all of the second sacrificial layer to form a pit between the first sacrificial layer and the third sacrificial layer includes: A pit area is defined on the surface of the third sacrificial layer using a photoresist; Photolithography the third sacrificial layer and a portion of the second sacrificial layer in the pit area using a photolithography process; Removing photoresist; The entire second sacrificial layer is removed.

7. The method for preparing an epitaxial channel field effect transistor device according to claim 1, characterized in that: The method for forming a control gate in a pit comprises: Using an epitaxial growth process, an interface oxide layer is formed in the pit, wherein the interface oxide layer covers the first sacrificial layer, the channel sidewalls and the lower surface of the third sacrificial layer; Using an epitaxial growth process, a dielectric layer is formed on the surface of the interface oxide layer; Forming a gate metal layer in the pit by using an epitaxial growth process, wherein a surface of the gate metal layer is flush with a surface of the third sacrificial layer; The interface oxide layer, the dielectric layer and the gate metal layer constitute a control gate.

8. The method for preparing an epitaxial channel field effect transistor device according to claim 7, characterized in that: The dielectric layer is a high-k dielectric layer.

9. The method for preparing an epitaxial channel field effect transistor device according to claim 7, characterized in that: A chemical mechanical polishing process is adopted to make the surface of the channel flush with the surface of the third sacrificial layer, and at the same time, make the surface of the gate metal layer flush with the surface of the third sacrificial layer.

10. The method for preparing an epitaxial channel field effect transistor device according to claim 1, characterized in that: The source electrode and the drain electrode are made of Si, SiGe, SiC or other III-V group or II-VI group compound semiconductor materials.

11. The method for preparing an epitaxial channel field effect transistor device according to claim 1, characterized in that: The source and the drain are doped with the same ions, and the doping concentration is heavy.

12. The method for preparing an epitaxial channel field effect transistor device according to claim 1, characterized in that: The first sidewall spacer and the second sidewall spacer are made of insulating low-k dielectric material.

13. The method for preparing an epitaxial channel field effect transistor device according to claim 12, characterized in that: The first sidewall spacer and the second sidewall spacer are made of silicon nitride, SiCN or SiOCN.

14. The method for preparing an epitaxial channel field effect transistor device according to claim 7, characterized in that: The preparation method further comprises: A through hole is formed in the source isolation layer and the drain isolation layer, and the bottom of the through hole exposes the gate metal layer.

15. An epitaxial channel field effect transistor device, prepared by the method for preparing an epitaxial channel field effect transistor device according to any one of claims 1 to 14, characterized in that: The epitaxial channel field effect transistor device comprises a drain, a channel and a source which are sequentially connected from top to bottom; control gates are formed on both sides of the channel.

16. The epitaxial channel field effect transistor device according to claim 15, characterized in that: The control gate includes an interface oxide layer, a dielectric layer and a gate metal layer; the interface oxide layer, the dielectric layer and the gate metal layer are formed in sequence from the inside to the outside on both sides of the channel; the two ends of the interface oxide layer and the dielectric layer are in contact with the source and the drain respectively; the gate metal layer is isolated from the source by a first side wall and isolated from the drain by a second side wall.

17. The epitaxial channel field effect transistor device according to claim 15, characterized in that: The channel is a nanowire channel or a nanosheet channel.

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