Quantum circuit compilation method and device based on quantum chip coupling topology structure

Abstract

The present application discloses a quantum circuit compilation method and device based on the coupled topological structure of a quantum chip, which is used to solve the problem that the design of quantum circuits is applied to quantum computers and that the application barriers are caused by the coupling relationship between physical bits. The method determines the coupled topological structure corresponding to each physical bit in the quantum chip; according to the coupled topological structure, traverses all gate operations to be performed on the quantum circuit, determines the gate operation that needs to be adjusted for the coupled topological structure, and uses it as the gate operation to be adjusted; according to the gate operation to be adjusted, adjusts the coupled topological structure through the SWAP gate operation; restores the adjusted coupled topological structure through the SWAP gate operation, and completes the compilation of the quantum circuit.

Description

Technical Field

[0001] The present application relates to the field of quantum computing, and in particular to a quantum circuit compilation method and device based on a quantum chip coupling topology structure. Background Art

[0002] In the application process of quantum computers, quantum algorithms are usually designed through quantum circuits and then implemented through quantum chips.

[0003] For the sake of ease of distinction, the quantum bit structure in a quantum chip is generally called a physical bit, and the object bit operated in a quantum circuit is called a quantum bit.

[0004] In quantum computers, the design of arbitrary logic gate operations can be realized through the two basic gate operations, single-bit gate operations and two-bit gate operations, as well as the combination of these two basic gate operations. Among them, single-bit gate operations include X-gate, T-gate, etc., and two-bit gate operations include SWAP, etc.

[0005] However, in actual application, the two-bit gate operation can only be realized between two physical bits with a coupling relationship, while the physical bits corresponding to the two-bit gate operation designed in the quantum circuit may not have a coupling relationship, that is, it does not meet the application restrictions of the two-bit gate operation. Therefore, in the process of applying the design of quantum circuits to quantum computers, certain obstacles are often encountered. Summary of the invention

[0006] The embodiments of the present application provide a quantum circuit compilation method and device based on a quantum chip coupling topology structure, so as to solve the problem that when the design of quantum circuits is applied to quantum computers, application barriers may arise due to the limitation of the coupling relationship between physical bits.

[0007] The embodiment of the present application provides a quantum circuit compilation method based on a quantum chip coupling topology structure, comprising:

[0008] Determine the coupling topology corresponding to each physical bit in the quantum chip;

[0009] According to the coupling topological structure, traverse all gate operations to be performed in the quantum circuit, and determine the gate operations for which the coupling topological structure needs to be adjusted as the gate operations to be adjusted;

[0010] According to the gate operation to be adjusted, adjusting the coupling topology structure through a SWAP gate operation;

[0011] Through the SWAP gate operation, the adjusted coupling topology is restored to complete the compilation of the quantum circuit.

[0012] In one example, according to the coupling topology, all gate operations to be performed on the quantum circuit are traversed to determine the gate operation for which the coupling topology needs to be adjusted as the gate operation to be adjusted, including: for all gate operations to be performed on the quantum circuit, according to the coupling topology, determining whether the quantum bits corresponding to the gate operation have a coupling relationship; and determining the gate operation corresponding to the quantum bits that do not have a coupling relationship as the gate operation to be adjusted.

[0013] In one example, according to the gate operation to be adjusted, the coupling topology structure is adjusted through a SWAP gate operation, including: according to the quantum bits corresponding to the gate operation to be adjusted, determining a number of SWAP gate operations corresponding to the adjustment of the coupling topology structure; through the several SWAP gate operations, adjusting each quantum bit in the coupling topology structure, and establishing a coupling relationship between the quantum bits corresponding to the gate operation to be adjusted.

[0014] In one example, according to the quantum bits corresponding to the gate operation to be adjusted, a number of SWAP gate operations corresponding to adjusting the coupling topology structure are determined, including: determining two quantum bits corresponding to the gate operation to be adjusted; and according to the distance between the two quantum bits in the coupling topology structure, determining a number of SWAP gate operations corresponding to adjusting the coupling topology structure.

[0015] In one example, according to the distance between the two quantum bits in the coupling topology structure, a number of SWAP gate operations corresponding to adjusting the coupling topology structure are determined, including: according to the distance between the two quantum bits in the coupling topology structure, the number of SWAP gate operations required to adjust the coupling topology structure and the execution order between the SWAP gate operations are determined.

[0016] In one example, the distance is directly correlated to the number of SWAP gate operations required.

[0017] In one example, each SWAP gate operation is used to gradually reduce the distance between two quantum bits corresponding to the gate operation to be adjusted.

[0018] In one example, through the several SWAP gate operations, each quantum bit in the coupled topological structure is adjusted to establish a coupling relationship between the quantum bits corresponding to the gate operation to be adjusted, including: through each SWAP gate operation, the order of the corresponding two quantum bits is exchanged until a coupling relationship exists between the two quantum bits corresponding to the gate operation to be adjusted.

[0019] In one example, the adjusted coupling topology structure is restored through SWAP gate operations, including: according to the number of required SWAP gate operations, the adjusted coupling topology structure is restored in the reverse order of the execution order between the SWAP gate operations.

[0020] The embodiment of the present application provides a quantum circuit compilation device based on a quantum chip coupling topology structure, comprising:

[0021] Determine the module and the coupling topology corresponding to each physical bit in the quantum chip;

[0022] A traversal module, according to the coupling topology, traverses all gate operations to be performed on the quantum circuit, and determines the gate operations that need to adjust the coupling topology as the gate operations to be adjusted;

[0023] An adjustment module, adjusting the coupling topology structure through a SWAP gate operation according to the gate operation to be adjusted;

[0024] The recovery module, through SWAP gate operation, restores the adjusted coupling topology and completes the compilation of the quantum circuit.

[0025] The embodiment of the present application provides a quantum circuit compilation method and device based on a quantum chip coupling topology structure, which at least includes the following beneficial effects: utilizing the characteristics of the SWAP gate operation, two quantum bits that do not have a coupling relationship in the physical bit coupling topology structure can establish a coupling relationship through exchange, thereby achieving the smooth execution of all two-bit gate operations in the quantum circuit. This method of compiling quantum circuits solves the obstacles to the application of quantum circuits in quantum chips in a simple implementation manner, and provides a good solution for the smooth implementation of various quantum algorithms. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0027] Figure 1 A flow chart of a quantum circuit compilation method based on a quantum chip coupling topology structure provided in an embodiment of the present application;

[0028] Figure 2 Schematic diagram of the UCSB five-qubit superconducting quantum chip provided in the embodiment of the present application;

[0029] Figure 3 A schematic diagram of the physical bit coupling topology of the UCSB five-bit superconducting quantum chip provided in the embodiment of the present application;

[0030] Figure 4 A schematic diagram of a two-bit gate operation in a quantum circuit provided in an embodiment of the present application;

[0031] Figure 5 The embodiments of the present application provide Figure 4 The corresponding quantum circuit compilation diagram;

[0032] Figure 6 Schematic diagram of the structure of a quantum circuit compilation device based on a quantum chip coupling topology provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0034] Figure 1 The flowchart of the quantum circuit compilation method based on the quantum chip coupling topology structure provided in the embodiment of the present application specifically includes the following steps:

[0035] S101: Determine the coupling topological structure corresponding to each physical bit in the quantum chip.

[0036] In an embodiment of the present application, the server may determine a coupling topology structure corresponding to the physical bit structure according to the structure of the physical bits in the quantum chip of the quantum computer.

[0037] like Figure 2 The figure shows a schematic diagram of the UCSB five-qubit superconducting quantum chip. Figure 3 Shown is a schematic diagram of the physical bit coupling topology of the UCSB five-bit superconducting quantum chip.

[0038] exist Figure 2 In the quantum chip, there are five physical bits Q0 to Q4. These five physical bits are coupled through capacitance, and only adjacent physical bits have a coupling relationship.

[0039] exist Figure 3 In the equation, q0 to q4 represent Figure 2 The five physical bits in the coupled topological structure correspond to the quantum bits in the coupled topological structure. The bidirectional arrow between two quantum bits represents the coupling relationship between the two quantum bits. Figure 3It can be seen that in this coupled topological structure, there is a coupling relationship between every two adjacent quantum bits, that is, between q0 and q1, between q1 and q2, between q2 and q3, and between q3 and q4. Apart from this, there is no other coupling relationship.

[0040] S102: According to the coupling topology structure, traverse all gate operations to be executed in the quantum circuit, and determine the gate operations that need to adjust the coupling topology structure as the gate operations to be adjusted.

[0041] In an embodiment of the present application, the server can compile all gate operations designed for the quantum circuit according to the designed quantum circuit during the application in the quantum chip to avoid the existence of gate operations in the gate operations of the quantum circuit that do not comply with the coupling relationship restrictions of the physical bits, thereby affecting the application of the quantum algorithm.

[0042] Specifically, for all gate operations to be executed in the quantum circuit, the server can determine whether the gate operation is a gate operation that does not comply with the physical bit coupling relationship restriction based on the determined coupling topology. The gate operation to be executed represents the gate operation pre-designed in the quantum circuit to be applied in the quantum chip, and the non-compliance with the physical bit coupling relationship restriction means that there is no coupling relationship between the physical bits corresponding to the gate operation.

[0043] If the gate operation meets the physical bit coupling relationship restrictions, the gate operation can be directly applied in the quantum chip without additional adjustments to the coupling topology. If the gate operation does not meet the physical bit coupling relationship restrictions, the gate operation cannot be directly applied in the quantum chip and the coupling topology needs to be adjusted before it can be applied. Therefore, the server can mark the gate operation that needs to adjust the coupling topology as a gate operation to be adjusted.

[0044] In one embodiment, since a single-bit gate operation does not have the problem of physical bit coupling relationship limitation, the gate operation mentioned in the embodiment of the present application that requires adjustment of the coupling topology structure is usually a two-bit gate operation.

[0045] For all gate operations to be performed in the quantum circuit, the server can determine the two qubits corresponding to each gate operation based on the coupling topology, and determine whether there is a coupling relationship between the two qubits. If there is a coupling relationship, the gate operation corresponding to the two qubits can be directly applied. If there is no coupling relationship, the gate operation corresponding to the two qubits is the gate operation to be adjusted.

[0046] like Figure 4 Shown is a schematic diagram of a two-bit gate operation in a quantum circuit.

[0047] exist Figure 4 In the figure, q0~q4 represent Figure 3 There are five corresponding quantum bits, and there is a coupling relationship between every two adjacent quantum bits. Figure 4 It also includes three two-bit gate operations, where the dot represents a quantum bit corresponding to the two-bit gate operation, and the plus sign “⊕” connected to the dot represents another quantum bit corresponding to the two-bit gate operation.

[0048] Take the two-bit controlled NOT gate CONTROL-NOT(i, j) as an example. The i in CONTROL-NOT(i, j) represents the number of the control qubit in the two qubits corresponding to the two-bit gate operation, that is, Figure 4 The dot in the figure represents the number of the target quantum bit in the two quantum bits corresponding to the two-bit gate operation, that is, Figure 4 The plus sign in . So, Figure 4 The three two-bit gate operations in are represented as CONTROL-NOT(q0,q1), CONTROL-NOT(q1,q3) and CONTROL-NOT(q1,q4).

[0049] according to Figure 3 , Figure 4 It can be seen that there is a coupling relationship between the physical bits Q0 and Q1, so the gate operation CONTROL-NOT (q0, q1) can be directly applied. There is no coupling relationship between the physical bits Q1 and Q3, and between Q1 and Q4. Therefore, the gate operations CONTROL-NOT (q1, q3) and CONTROL-NOT (q1, q4) both need to adjust the coupling topology structure before application, which are the gate operations to be adjusted.

[0050] S103: According to the gate operation to be adjusted, the coupling topology structure is adjusted through a SWAP gate operation.

[0051] In the embodiment of the present application, the server can adjust the coupling topology structure by adding a SWAP gate operation according to the determined gate operation to be adjusted, so as to realize the application of the gate operation to be adjusted in the quantum chip. Among them, the SWAP gate operation is a commonly used two-bit gate operation that can perform an exchange operation on two quantum bits.

[0052] In one embodiment, the server can determine the number of SWAP gate operations that need to be added when adjusting the coupled topological structure based on the relationship between the two qubits corresponding to the gate operation to be adjusted in the topological structure. Afterwards, the server can adjust the position of each qubit in the coupled topological structure through the determined number of SWAP gate operations, and exchange two non-adjacent qubits into two adjacent physical bits to establish a coupling relationship between the two qubits corresponding to the gate operation to be adjusted, thereby realizing the application of the gate operation to be adjusted.

[0053] That is to say, through each SWAP gate operation, the order of two adjacent quantum bits is exchanged until the position relationship of the two quantum bits corresponding to the gate operation to be adjusted is changed from non-adjacent to adjacent, so that the two quantum bits can have a coupling relationship to realize the application of the gate operation to be adjusted.

[0054] Specifically, the server may determine the distance between two qubits corresponding to the gate operation to be adjusted, and determine a number of SWAP gate operations corresponding to adjusting the coupling topology structure based on the obtained distance. The distance between the two qubits may be represented by the number of qubits between the two qubits.

[0055] like Figure 4 As shown, there is 1 quantum bit between quantum bits q1 and q3, so their distance can be expressed as 1, and there are 2 quantum bits between quantum bits q1 and q4, so their distance can be expressed as 2.

[0056] In one embodiment, the server may determine the number of SWAP gate operations required to adjust the coupling topology and the execution order of multiple SWAP gate operations based on the distance between two quantum bits in the coupling topology, with the rule of shortening the distance between the two quantum bits.

[0057] Among them, the distance between the two quantum bits corresponding to the gate operation to be adjusted is positively correlated with the number of SWAP gate operations required. The farther the distance, the more SWAP gate operations are required, and the closer the distance, the fewer SWAP gate operations are required.

[0058] Furthermore, for the adjustment process of a gate operation to be adjusted on the coupling topology structure, the SWAP gate operation is used to gradually reduce the distance between the two corresponding qubits. In other words, each SWAP gate operation can reduce the distance between the two target qubits by 1 until the distance between the two qubits is 0. Therefore, the server can determine the execution order between multiple SWAP gate operations according to the requirement of the SWAP gate operation to gradually reduce the distance.

[0059] It should be noted that since the SWAP gate operation can only be performed between two quantum bits with a coupling relationship, when the server adjusts the coupling topology structure through the SWAP gate operation, it can only exchange two adjacent quantum bits in the coupling topology structure, and cannot exchange them arbitrarily.

[0060] Taking the above CONTROL-NOT (q1, q4) as an example, there are 2 qubits between the two qubits q1 and q4 corresponding to the gate operation to be adjusted, and the distance is 2, so it can be determined that the number of SWAP gate operations required is 2. Therefore, according to the requirement of gradually reducing the distance between qubits 1 and 4 through SWAP gate operations, the server can first use the first SWAP gate operation SWAP (q3, q4) to exchange qubits q3 and q4, so that the order of the five qubits changes from q0, q1, q2, q3, q4 to q0, q1, q2, q4, q3, and then use the second SWAP gate operation SWAP (q2, q4) to exchange qubits q2 and q4, so that the order of the five qubits changes from q0, q1, q2, q4, q3 to q0, q1, q4, q2, q3. Therefore, after adjustment, a coupling relationship is established between the two quantum bits q1 and q4 corresponding to the CONTROL-NOT (q1, q4) gate operation, and the CONTROL-NOT (q1, q4) gate operation can be applied.

[0061] The server may also adopt the first SWAP gate operation SWAP(q1, q2) and the second SWAP gate operation SWAP(q1, q3) to exchange, and the topology structure adjustment with the same effect can be achieved.

[0062] S104: Through the SWAP gate operation, the adjusted coupling topology structure is restored to complete the compilation of the quantum circuit.

[0063] In the embodiment of the present application, after the server completes the application of the gate operation to be adjusted in the quantum chip, in order to avoid the logical confusion of the quantum bits in the quantum chip, the adjusted coupling topology structure can be restored through the SWAP gate operation to maintain the normal logical order. At this point, the server can determine that the compilation process of the quantum circuit is completed.

[0064] In one embodiment, the server may perform the same SWAP gate operation again in the reverse order of the execution order according to the number of SWAP gate operations required for adjusting the coupling topology structure determined in S102 and the corresponding execution order, thereby realizing recovery of the adjusted coupling topology structure.

[0065] Taking the above CONTROL-NOT (q1, q4) as an example, after two SWAP gate operations SWAP (q3, q4) and SWAP (q2, q4) are adjusted, the order of the five quantum bits in the current coupling topology is q0, q1, q4, q2, q3. After CONTROL-NOT (q1, q4) is completed, the server can restore the order of the five quantum bits to q0, q1, q2, q3, q4 through the reverse order of SWAP (q2, q4) and SWAP (q3, q4) to achieve the recovery of the coupling topology.

[0066] like Figure 5 Shown with Figure 4 Corresponding quantum circuit compilation diagram.

[0067] Using the above two-bit control NOT gate CONTROL-NOT(i, j) example, Figure 5 In the figure, the cross marks “×” at both ends of the connecting line indicate SWAP gate operation.

[0068] CONTROL-NOT(q0,q1) can be directly applied in the quantum chip and does not change after compilation. Figure 4 and Figure 5 The two-bit operation gates in are the same.

[0069] Figure 4 CONTROL-NOT(q1,q3) corresponds to Figure 5 The two-bit gate operation in the dashed box on the left. After the compilation, two SWAP gate operations are inserted into CONTROL-NOT(q1, q3). After the first SWAP gate operation is performed, the quantum bits q1 and q3 have a coupling relationship, CONTROL-NOT(q1, q3) is executed, and then the second SWAP gate operation restores the coupling topology.

[0070] Figure 4 CONTROL-NOT(q1,q4) corresponds to Figure 5 The two-bit gate operation in the dotted box on the right. After the compilation of CONTROL-NOT(q1, q4), four SWAP gate operations are inserted. After the first SWAP gate operation and the second SWAP gate operation are exchanged twice, the quantum bits q1 and q4 have a coupling relationship. CONTROL-NOT(q1, q4) is executed, and then the third SWAP gate operation and the fourth SWAP gate operation restore the coupling topology.

[0071] In the embodiment of the present application, the characteristics of the SWAP gate operation are used to establish a coupling relationship between two quantum bits that do not have a coupling relationship in the physical bit coupling topology, so as to achieve the smooth execution of all two-bit gate operations in the quantum circuit. This method of compiling quantum circuits solves the obstacles to the application of quantum circuits in quantum chips in a simple implementation manner, and provides a good solution for the smooth implementation of various quantum algorithms.

[0072] The above is a quantum circuit compilation method based on a quantum chip coupling topology structure provided in the embodiment of the present application. Based on the same inventive idea, the embodiment of the present application also provides a corresponding quantum circuit compilation device based on a quantum chip coupling topology structure, such as Figure 6 shown.

[0073] Figure 6 The schematic diagram of the structure of a quantum circuit compilation device based on a quantum chip coupling topology structure provided in an embodiment of the present application specifically includes:

[0074] Determining module 601, determining the coupling topological structure corresponding to each physical bit in the quantum chip;

[0075] A traversal module 602 traverses all gate operations to be performed in the quantum circuit according to the coupling topology structure, and determines the gate operations for which the coupling topology structure needs to be adjusted as the gate operations to be adjusted;

[0076] An adjustment module 603 adjusts the coupling topology structure through a SWAP gate operation according to the gate operation to be adjusted;

[0077] The recovery module 604 recovers the adjusted coupling topology structure through SWAP gate operation to complete the compilation of the quantum circuit.

[0078] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0079] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0080] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A quantum circuit compilation method based on a quantum chip coupling topology structure, characterized in that: include: Determine the coupling topology corresponding to each physical bit in the quantum chip; According to the coupling topology, all gate operations to be performed on the quantum circuit are traversed to determine the gate operation for which the coupling topology needs to be adjusted as the gate operation to be adjusted, including: for all gate operations to be performed on the quantum circuit, according to the coupling topology, determining whether there is a coupling relationship between the quantum bits corresponding to the gate operation; and determining the gate operation corresponding to the quantum bits that do not have a coupling relationship as the gate operation to be adjusted; According to the gate operation to be adjusted, the coupling topology structure is adjusted through the SWAP gate operation, including: determining two quantum bits corresponding to the gate operation to be adjusted; determining the two quantum bits corresponding to the gate operation to be adjusted, and determining a number of SWAP gate operations corresponding to the adjustment of the coupling topology structure according to the distance between the two quantum bits in the coupling topology structure, including: determining the number of SWAP gate operations required for adjusting the coupling topology structure and the execution order between the SWAP gate operations according to the distance between the two quantum bits in the coupling topology structure; adjusting each quantum bit in the coupling topology structure through the several SWAP gate operations, and establishing a coupling relationship between the quantum bits corresponding to the gate operation to be adjusted; After the application of the gate operation to be adjusted in the quantum chip is completed, the adjusted coupling topology structure is restored through the SWAP gate operation to complete the compilation of the quantum circuit, including: according to the number of the required SWAP gate operations, the adjusted coupling topology structure is restored in the reverse order of the execution order between the SWAP gate operations.

2. The method according to claim 1, characterized in that The distance is directly related to the number of SWAP gate operations required.

3. The method according to claim 1, characterized in that Each SWAP gate operation is used to gradually reduce the distance between two quantum bits corresponding to the gate operation to be adjusted.

4. The method according to claim 1, characterized in that: By means of the plurality of SWAP gate operations, each qubit in the coupled topological structure is adjusted to establish a coupling relationship between qubits corresponding to the gate operations to be adjusted, including: Through each SWAP gate operation, the order of the corresponding two quantum bits is exchanged until a coupling relationship exists between the two quantum bits corresponding to the gate operation to be adjusted.

5. A quantum circuit compilation device based on a quantum chip coupling topology structure, characterized in that: include: Determine the module and the coupling topology corresponding to each physical bit in the quantum chip; A traversal module, according to the coupling topology, traverses all gate operations to be performed on the quantum circuit, and determines the gate operation that needs to adjust the coupling topology as the gate operation to be adjusted, including: for all gate operations to be performed on the quantum circuit, according to the coupling topology, determining whether the quantum bits corresponding to the gate operation have a coupling relationship; and determining the gate operation corresponding to the quantum bits that do not have a coupling relationship as the gate operation to be adjusted; The adjustment module adjusts the coupling topology structure through a SWAP gate operation according to the gate operation to be adjusted, including: determining two quantum bits corresponding to the gate operation to be adjusted; determining the two quantum bits corresponding to the gate operation to be adjusted, and determining a number of SWAP gate operations corresponding to the adjustment of the coupling topology according to the distance between the two quantum bits in the coupling topology, including: determining the number of SWAP gate operations required for adjusting the coupling topology according to the distance between the two quantum bits in the coupling topology, and the execution order between the SWAP gate operations; adjusting each quantum bit in the coupling topology through the several SWAP gate operations, and establishing a coupling relationship between the quantum bits corresponding to the gate operation to be adjusted; The recovery module, after completing the application of the gate operation to be adjusted in the quantum chip, recovers the adjusted coupling topology structure through SWAP gate operation to complete the compilation of the quantum circuit, including: according to the number of the required SWAP gate operations, in the reverse order of the execution order between the SWAP gate operations, recovering the adjusted coupling topology structure.

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