Synchronous rectification control circuit and voltage converter

Abstract

A synchronous rectification control circuit is disclosed, including a first trigger, a first comparator, a second comparator and a delay circuit, wherein the first comparator compares the drain-source voltage of the synchronous rectifier tube with a first reference signal and provides a first control signal, the second comparator compares the drain-source voltage of the synchronous rectifier tube with a second reference signal and provides a third control signal to the second input terminal of the first trigger, and the delay circuit delays the first control signal and provides a second control signal to the first input terminal of the first trigger. The delay time of the delay circuit of the synchronous rectification control circuit of the present invention is a threshold value for judging whether the body diode of the rectifier tube is normally turned on or parasitic oscillation turned on, that is, judging whether the effective start time of the third control signal is before or after the effective start time of the second control signal, respectively corresponding to the first trigger being set to two output states before maintaining the original output state, and controlling the timely conduction and shutdown of the synchronous rectifier tube.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a synchronous rectification control circuit and a voltage converter. Background Art

[0002] Flyback voltage converter Figure 1 As shown, it includes a primary circuit and a secondary circuit, the primary circuit and the secondary circuit are isolated by a transformer T, the primary circuit includes a primary switch Q in the electrical loop, and the energy can be transferred to the secondary circuit through the switching action of the primary switch Q, the secondary circuit includes an output capacitor C0 connected in series with the secondary side of the transformer T and a synchronous rectifier SR arranged between the secondary side of the transformer T and the output capacitor C0, and the two ends of the output capacitor are coupled to the load. Among them, in order to improve the efficiency of the power supply, the synchronous rectifier of the secondary side usually adopts a synchronous rectifier with a lower resistance than a diode or a body diode and a low loss in the synchronous conduction state, and a high-efficiency rectification function is achieved by timely controlling the conduction and shutdown of the synchronous rectifier.

[0003] Among them, for the voltage-controlled synchronous rectifier, the turn-on time point of the synchronous rectifier is generally determined by detecting the drain-source voltage Vds of the synchronous rectifier SR, such as Figure 2 As shown, when it is detected that Vds is less than the second threshold voltage Vth2, it is considered that the body diode of the synchronous rectifier has been turned on, and the synchronous rectifier can be controlled to be turned on.

[0004] In the prior art, when the circuit operates in the DCM (Discontinuous Conduction Mode) mode, the circuit will generate parasitic oscillations, and the parasitic oscillations may also cause the body diode of the synchronous rectifier SR to turn on, thereby misleadingly turning on the synchronous rectifier SR under the parasitic oscillation. Figure 2 As shown, in the prior art, the PWM (Pulse Width Modulation) signal corresponds to controlling the conduction of the synchronous rectifier SR, and a Blank signal is set after the PWM signal. The Blank signal corresponds to the parasitic oscillation time, and controls the synchronous rectifier SR to maintain the shutdown to prevent the synchronous rectifier SR from being mis-conducted. However, if the power supply needs to be compatible with CCM (Continuous Conduction Mode), QR (quasi-resonant) mode and DCM operation, the blank time of the Blank signal will prevent the normal conduction of the synchronous rectifier SR in the QR and CCM working modes, thereby reducing the power supply efficiency. Summary of the invention

[0005] In view of the above problems, an object of the present invention is to provide a synchronous rectification control circuit and a voltage converter, so as to improve power supply efficiency.

[0006] According to one aspect of the present invention, there is provided a synchronous rectification control circuit, comprising a synchronous rectifier drain-source voltage receiving terminal and a synchronous rectifier gate control signal output terminal, characterized in that it comprises:

[0007] A first comparator, comprising an input terminal coupled to the synchronous rectifier drain-source voltage receiving terminal, a first reference signal input terminal and a first control signal output terminal;

[0008] A delay circuit, comprising an input terminal coupled to the first control signal output terminal and a second control signal output terminal;

[0009] A second comparator comprises an input terminal coupled to the synchronous rectifier drain-source voltage receiving terminal, a second reference signal input terminal and a third control signal output terminal;

[0010] a first trigger, wherein a first input terminal of the first trigger is coupled to the second control signal output terminal of the delay circuit, a second input terminal is coupled to the third control signal output terminal of the second comparator, and an output terminal is coupled to the gate control signal output terminal of the synchronous rectifier tube,

[0011] The level of the first reference signal is higher than the level of the second reference signal.

[0012] Optionally, the delay circuit includes:

[0013] A capacitor, wherein a first terminal of the capacitor is coupled to the output terminal of the current source, and a second terminal of the capacitor is grounded;

[0014] A switch connected in series at two ends of the capacitor, the switch comprising a switch control end coupled to the first control signal output end;

[0015] The third comparator comprises an input terminal coupled to the first terminal of the capacitor, a third reference signal input terminal and an output terminal, and the output terminal of the third comparator is the second control signal output terminal.

[0016] Optionally, the third reference signal input terminal of the delay circuit is coupled to a third reference signal output terminal of an external third reference signal configuration circuit.

[0017] Optionally, the delay circuit further includes an inverter, and the inverter is forward coupled between the first control signal output terminal and the switch control terminal of the switch;

[0018] The switch is an NMOS tube, and the gate of the NMOS tube is the switch control terminal.

[0019] Optionally, it also includes:

[0020] An OR gate, coupled between the second control signal output terminal and the first input terminal of the first trigger, the OR gate comprising a first input terminal, a second input terminal and an output terminal, the second input terminal of the OR gate being coupled to the second control signal output terminal, and the output terminal of the OR gate being coupled to the first input terminal of the first trigger;

[0021] A pulse generator, wherein the input end of the pulse generator is coupled to the first control signal output end, and the pulse output end of the pulse generator is coupled to the first input end of the OR gate.

[0022] Optionally, it also includes:

[0023] An AND gate includes a first input terminal coupled to the first control signal output terminal, a second input terminal coupled to the output terminal of the first trigger, and an output terminal coupled to the synchronous rectifier gate control signal output terminal.

[0024] Optionally, it also includes:

[0025] A second trigger, wherein a set terminal of the second trigger is coupled to the output terminal of the AND gate, and an output terminal of the second trigger is coupled to the gate control signal output terminal of the synchronous rectifier;

[0026] The synchronous rectifier shutoff detection module comprises an input terminal coupled to the synchronous rectifier drain-source voltage receiving terminal and a synchronous rectifier shutoff signal output terminal coupled to the reset terminal of the second trigger.

[0027] Optionally, it also includes:

[0028] A second trigger, wherein a set terminal of the second trigger is coupled to an output terminal of the first trigger, an output terminal of the second trigger is coupled to a gate control signal output terminal of the synchronous rectifier, and the second trigger is a reset dominant trigger;

[0029] The synchronous rectifier shutoff detection module comprises an input terminal coupled to the synchronous rectifier drain-source voltage receiving terminal and a synchronous rectifier shutoff signal output terminal coupled to the reset terminal of the second trigger.

[0030] Optionally, the synchronous rectifier shutdown detection module includes:

[0031] The fourth comparator comprises an input terminal coupled to the synchronous rectifier drain-source voltage receiving terminal, a fourth reference signal input terminal and a synchronous rectifier shutdown signal output terminal coupled to the reset terminal of the second trigger.

[0032] Optionally, the first trigger is an RS trigger, the set end of the RS trigger is the first input end of the first trigger, the reset end of the RS trigger is the second input end of the first trigger, and the inverting output end of the RS trigger is the output end of the first trigger.

[0033] According to another aspect of the present invention, there is provided a voltage converter, comprising:

[0034] A transformer, wherein the transformer is connected to a primary circuit and a secondary circuit, wherein the secondary circuit includes a synchronous rectifier tube;

[0035] According to the synchronous rectification control circuit provided by the present invention, the synchronous rectification tube gate control signal output terminal of the synchronous rectification control circuit is coupled to the gate of the synchronous rectification tube.

[0036] The synchronous rectification control circuit provided by the present invention includes a first trigger, a first comparator, a second comparator and a delay circuit, the first comparator compares the drain-source voltage of the synchronous rectifier and the first reference signal, and provides a first control signal, the second comparator compares the drain-source voltage of the synchronous rectifier and the second reference signal, and provides a third control signal, the delay circuit delays the first control signal to provide a second control signal, the second control signal is provided to the first input end of the first trigger, and the third control signal is provided to the second input end of the first trigger, wherein the delay time of the delay circuit is a threshold for judging whether the body diode of the rectifier is normally turned on or parasitic oscillation turned on, that is, whether the effective start time of the third control signal is before or after the effective start time of the second control signal, which respectively corresponds to the first trigger setting it to two output states before maintaining the original output state, which respectively corresponds to the conduction and shutdown of the synchronous rectifier.

[0037] The delay circuit determines the delay time by the time taken for the first end of the capacitor to be charged to the third reference signal level. The performance of the capacitor is stable, and the delay is simple and effective.

[0038] The third reference signal is configured by an external third reference signal configuration circuit and can be adjusted externally. After the circuit design is completed, the delay time can be adjusted to adapt to the synchronous rectification specifications of different voltage converters and match the delay time control design of the capacitor. It can also be adapted to parameter changes caused by device aging. Adjusting the third reference signal can compensate for the errors caused by aging and improve practicality.

[0039] The charging and discharging of the capacitor of the delay circuit is controlled by a switch, and the switch selects an NMOS tube, which has a fast response speed and high delay time accuracy.

[0040] An OR gate and a pulse generator are designed to provide a narrow pulse when the first control signal starts to take effect, which is provided to the first input of the first trigger after executing the OR logic with the second control signal. The inverting output of the first trigger can be initialized to 0, corresponding to the shutdown of the synchronous rectifier tube, thereby avoiding the accidental start-up of the synchronous rectifier tube.

[0041] An AND gate is set to execute the AND logic of the first control signal and the output state of the inverting output terminal of the first trigger to control the opening of the synchronous rectifier. This can prevent the first trigger from being interfered by other signals during the time when the output state is unclear and erroneously outputting a valid synchronous rectifier gate control signal, thereby avoiding erroneous opening of the synchronous rectifier during this time.

[0042] A reset-dominated second trigger and a synchronous rectifier shutdown detection module are set up, and the output end of the synchronous rectifier shutdown detection module is coupled to the reset end of the second trigger, which independently controls the shutdown of the synchronous distillation section to ensure that the synchronous rectifier is shut down within the time when the synchronous rectifier needs to be shut down to avoid mis-turning on.

[0043] The voltage converter provided by the present invention comprises a primary circuit and a secondary circuit connected by a transformer, wherein the secondary circuit comprises a synchronous rectifier tube, and the synchronous rectifier tube is controlled by the synchronous rectifier control circuit provided by the present invention, so that the synchronous rectifier tube can be prevented from being turned on during the parasitic oscillation time, thereby improving the working efficiency of the voltage converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0045] Figure 1 A schematic diagram of the structure of a flyback voltage converter according to the prior art is shown;

[0046] Figure 2 shows a control signal timing diagram of a synchronous rectifier according to the prior art;

[0047] Figure 3 A schematic structural diagram of a synchronous rectification control circuit according to an embodiment of the present invention is shown;

[0048] Figure 4 shows a working timing diagram of a pulse generator according to an embodiment of the present invention;

[0049] Figure 5 A partial timing diagram of a synchronous rectification control circuit according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0050] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0051] The specific implementation of the present invention is further described in detail below in conjunction with the drawings and examples.

[0052] The term "connection" or "coupling" in the specification includes both direct connection and indirect connection. Indirect connection is coupling through an intermediate medium, such as coupling through an electrical conductive medium such as a conductor, wherein the electrical conductive medium may contain parasitic inductance or parasitic capacitance, or coupling through an intermediate circuit or component described in the embodiments in the specification; indirect connection may also include coupling through other active or passive devices on the basis of achieving the same or similar functions, such as coupling through circuits or components such as signal amplification circuits, follower circuits, and logic processing circuits.

[0053] Figure 3 A structural schematic diagram of a synchronous rectification control circuit according to an embodiment of the present invention is shown.

[0054] like Figure 3 As shown, the synchronous rectification control circuit 100 of the embodiment of the present invention includes a second trigger T2, a synchronous rectifier turn-on detection module 110 and a synchronous rectifier turn-off detection module 120, the synchronous rectifier drain-source voltage Vds comes from the synchronous rectifier drain-source voltage receiving end (not shown in the figure), the synchronous rectifier turn-on detection module 110 and the synchronous rectifier turn-off detection module 120 detect the voltage value of the synchronous rectifier drain-source voltage Vds, and output a synchronous rectifier turn-on signal (second trigger set signal T2S) to the set end of the second trigger T2 and output a synchronous rectifier turn-off signal (second trigger reset signal T2R) to the reset end of the second trigger T2, the output end Q of the second trigger T2 is coupled to the gate of the synchronous rectifier SR, and the conduction and shutdown of the synchronous rectifier SR are controlled according to the second trigger set signal T2S and the second trigger reset signal T2R. Among them, the second trigger T2 is a reset dominant trigger. When the reset signal T2R of the second trigger is 1 and valid, the output terminal Q outputs a low level and turns off the synchronous rectifier tube SR.

[0055] The synchronous rectifier on detection module 110 includes a first comparator COMP1, a pulse generator 111, a first trigger T1, an AND gate 115, a second comparator COMP2, an OR gate 114, a third comparator COMP4, a reference value configuration circuit (third reference signal configuration circuit) 112, a capacitor C1, a switch S1, a resistor Rcf, a current source I1 and an inverter 113. The first trigger T1 is a common RS trigger, which maintains the original output state when both the set terminal and the reset terminal are 1.

[0056] In this embodiment, the first trigger T1 is an RS trigger, the set end of the RS trigger is the first input end of the first trigger T1, the reset end of the RS trigger is the second input end of the first trigger T1, and the inverting output end of the RS trigger is the output end of the first trigger T1.

[0057] The input end of the first comparator COMP1 is coupled to the synchronous rectifier drain-source voltage receiving end, that is, the inverting input end receives the synchronous rectifier drain-source voltage Vds; it includes a first reference signal input end, that is, the non-inverting input end receives the first reference signal Vth1; and the first control signal output end outputs the first control signal CU1.

[0058] The inverter 113, the switch S1, the current source I1, the capacitor C1, and the third comparator COMP4 constitute a delay circuit, which includes an input terminal coupled to the first control signal output terminal, a third reference signal input terminal, and a third control signal output terminal, receives the first control signal CU1, and outputs the second control signal CU4 after a certain delay.

[0059] Among them, the delay time can be controlled by the third reference signal Vth_conf, and the third reference signal Vth_conf is configured by the reference value configuration circuit 112. The reference value configuration circuit 112 is the third reference signal configuration circuit, which outputs the third reference signal Vth_conf at the third reference signal output end, and the other end is grounded through the resistor Rcf. The third reference signal configuration circuit is an external circuit, and the voltage value of the output point third reference signal can be adjusted through external resistors, capacitors and other elements. The slope of the ramp voltage signal Vramp provided by the first end of the capacitor C1 during charging is fixed, and the time it rises to the level value of the third reference signal Vth_conf is the delay time, and the effective start time of the second control signal CU4 will be one delay time later than the effective start time of the first control signal CU1.

[0060] In the delay circuit, the input end of the inverter 113 receives the first control signal CU1, and the output end is coupled to the switch control end of the switch S1 to control the on and off of the switch S1; the first end of the capacitor C1 is coupled to the output end of the current source I1, and the second end is grounded; the switch S1 is connected in series at both ends of the capacitor C1; the third comparator COMP4 includes an input end coupled to the first end of the capacitor C1, a third reference signal input end and a second control signal output end, the third reference signal input end is the inverting input end of the third comparator COMP4, and receives the third reference signal Vth_conf, the non-inverting input end of the third comparator COMP4 receives the ramp voltage signal Vramp, and the output end of the third comparator COMP4 is the second control signal output end, providing the second control signal CU4; the second control signal CU4 is coupled to the second input end of the OR gate 114, the first input end of the OR gate 114 is coupled to the pulse output end of the pulse generator 111, and the second control signal CU4 and the pulse signal Pulse1 are executed with the OR logic as the set signal T1S of the first trigger T1.

[0061] The second comparator COMP2 includes an input terminal (inverting input terminal) coupled to the synchronous rectifier drain-source voltage receiving terminal for receiving the synchronous rectifier drain-source voltage Vds, a second reference signal input terminal (non-inverting input terminal) for receiving the second reference signal Vth2, and a third control signal output terminal, and the third control signal is the reset signal T1R of the first trigger T1. The output signal TU1 of the inverting output terminal (Q non-terminal) of the first trigger T1 can be used as a synchronous rectifier gate control signal to control the conduction and shutdown of the synchronous rectifier, that is, the inverting output terminal of the first trigger T1 can be directly coupled to the synchronous rectifier gate control signal output terminal.

[0062] The synchronous rectifier shutdown detection module 120 includes a fourth comparator COMP3, which includes an input end, a fourth reference signal input end and a synchronous rectifier shutdown signal output end, that is, the non-inverting input end of the fourth comparator receives the synchronous rectifier drain-source voltage Vds, and the inverting input end receives the fourth reference signal Vth3. When the synchronous rectifier drain-source voltage Vds is greater than the fourth reference signal Vth3 level, a valid synchronous rectifier shutdown signal is output, that is, the reset signal T2R of the second trigger T2 is valid, and the second trigger T2 is a reset dominant trigger, and its output end (Q end) is reset to a low level, the synchronous rectifier SR is turned off, and the synchronous rectifier drain-source voltage Vds is raised synchronously with the secondary voltage of the voltage converter.

[0063] Figure 4 FIG. 4 shows a working timing diagram of a pulse generator according to an embodiment of the present invention.

[0064] like Figure 4As shown, the pulse signal output by the pulse generator of the embodiment of the present invention is synchronized with the rising edge of the input signal, and when the input signal becomes a high level, a narrow pulse signal is immediately output.

[0065] Figure 5 A partial timing diagram of a synchronous rectification control circuit according to an embodiment of the present invention is shown.

[0066] Also refer to Figure 5 and Figure 3 , where Vth1>0>Vth3>Vth2, and the time from t4 to t9 is within the parasitic oscillation time. When Vds>Vth3, the fourth comparator outputs a high level, the reset signal T2R of the second flip-flop T2 is valid at 1, the output of the second flip-flop T2 is reset to 0, and the gate of the synchronous rectifier is at a low level and remains off. The high level can be understood as 1, and the low level can be understood as 0.

[0067] At time t1, the drain-source voltage Vds of the synchronous rectifier drops to the level of the first reference signal Vth1, the first control signal CU1 becomes a high level, and the pulse signal Pulse1 output by the pulse generator outputs a narrow pulse, so that the set signal T1S of the first trigger T1 is briefly set to 1 and then maintained at 0, and the inverting output terminal of the first trigger T1 can be set to 0, that is, the inverting output terminal of the first trigger T1 is initialized to 0 and then maintained at 0; Vds>Vth2, T1R is 0; so that during the time from t1 to t2, the output signal TU1 of the inverting output terminal of the first trigger T1 is 0; the switch S1 is disconnected, the capacitor C1 starts to charge, and the ramp voltage Vramp starts to rise, but it is less than the level value of the third reference signal Vth_conf, and CU4 is maintained at 0 after the Pulse1 pulse ends.

[0068] Among them, CU1 controls the on and off of switch S1 through inverter 113. Switch S1 can be selected as NMOS (N-Metal-Oxide-Semiconductor) tube, whose gate is the switch control terminal. At time t1, its gate control signal is low level, the NMOS tube is turned off, and switch S1 is disconnected. The NMOS tube responds quickly and the time control is precise.

[0069] At time t2, the Vds signal decreases to Vth2, the second comparator outputs a high level, the reset signal T1R of the first trigger is set to 1, the ramp voltage Vramp is still less than the level value of the third reference signal Vth_conf, the set signal T1S of the first trigger T1 is equal to CU4 is 0, the output signal TU1 of the inverting output end of the first trigger T1 is controlled to 1 by its reset signal T1R, Vds is less than Vth3, T2R is 0, T2S is 1, the output end of the second trigger T2 is high level, and the synchronous rectifier is turned on. The time from t1 to t2 is the first time that Vds decreases from Vth1 to Vth2.

[0070] At time t3, the ramp voltage Vramp at the first end of the capacitor C1 increases to the level of the third reference signal Vth_conf, CU4 becomes high level, the set signal of the first trigger T1 is 1, the reset signal is 1, the output state is maintained, that is, TU1 is maintained at 1, and the synchronous rectifier is maintained on. The time from t1 to t3 is the delay time.

[0071] At time t4, Vds increases to Vth2 and is less than Vth1, T1R becomes low level, T1S is high level, the set end of the first trigger T1 is valid, the reset end is invalid, TU1 becomes 0, and the rectifier can be controlled to turn off. Among them, after TU1 and CU1 are executed and logic, they are provided to the set end of the second trigger T2, and the reset end of the second trigger T2 is controlled by the synchronous rectifier turn-off detection module 120. At time t4, Vds is less than Vth3, the output end of the second trigger T2 is maintained at 1, TU1 is maintained at 0, T2S is maintained at 0, and the output end signal of the second trigger T2 cannot be set to 1. The synchronous rectifier can be maintained as turned off during the parasitic oscillation time from t4 to t9. The start time of its turn-off is after t4, and when Vds is greater than Vth3, that is, the turn-off of the synchronous rectifier is based on Vth3 as the reference standard, and it is turned on during the time from t2 to t4 outside the turn-off.

[0072] At t5, it is in the parasitic oscillation time, Vds rises back to Vth1, CU1 becomes low level, switch S1 is closed, the first end of capacitor C1 is grounded, the ramp voltage Vramp is at ground level, CU4 becomes low level, the set end of the first trigger T1 is 0, the reset end is also 0, and TU1 at the inverting output end is 0. Among them, if Vds is less than Vth1 during the parasitic oscillation time, the ramp voltage Vramp is continuously charged, so that the CU4 signal is continuously at a high level, then after t5, TU1 will continue to be set to 0, keeping the synchronous rectifier off, and avoiding false start-up.

[0073] At time t6, the parasitic oscillation Vds drops to Vth1, CU1 becomes a high level, the pulse generator outputs a narrow pulse, briefly sets the set end of the first trigger T1 to 1, initializes the first trigger T1, TU1 is 0, the switch S1 is disconnected, the capacitor C1 starts to charge, and the ramp voltage Vramp starts to increase.

[0074] At time t7, the ramp voltage Vramp increases to the level value of the third reference signal Vth_conf, CU4 becomes a high level, the set end of the first trigger T1 is 1, and Vds has not yet dropped to Vth2, TIR is 0, the inverting output end of the first trigger T1 is set to 0, TU1 is 0, and the set end of the second trigger T2 is 0. The output end of the second trigger T2 will not be set to 1, and the output is 0, and the synchronous rectifier tube remains off.

[0075] Among them, during the time from t5 to t7 and excluding the pulse time of Pulse1, the set terminal and the reset terminal of the first trigger are both 0, and the output state is unclear. In the absence of other interference, the TU1 signal at the inverting output terminal is maintained at 0. The TU1 signal and the CU1 signal are controlled to be turned on after performing the AND logic through the AND gate 115, which can avoid the interference signal interfering with the output state of the first trigger during the time when the output state of the first trigger is unclear, thereby avoiding misleading the synchronous rectifier.

[0076] At time t8, Vds drops to Vth2, and the T1R signal becomes 1, making the reset end of the first trigger T1 1. At the same time, the set end of the first trigger T1 remains at 1, the output state of the first trigger T1 remains original, TU1 remains at 0, and the synchronous rectifier tube remains off.

[0077] Among them, the time from t1 to t3 is equal to the time from t6 to t7, which is the delay time. The first time from t1 to t2 is the time when the Vds of the body diode of the drain-source voltage of the synchronous rectifier is normally turned on and the Vds is reduced from Vth1 to Vth2. The second time from t6 to t8 is the time when the Vds of the body diode of the drain-source voltage of the synchronous rectifier is turned on during the parasitic oscillation time and the Vds is reduced from Vth1 to Vth2. The first time < delay time < second time. After the delay time, the set signal T1S of the first trigger T1 is 1. After the first time or the second time, the reset signal T1R of the first trigger T1 is 1. The first trigger T1 maintains the output state when both its set terminal and reset terminal are 1.

[0078] When the body diode of the synchronous rectifier is normally turned on, Vds decreases from Vth1 to Vth2 quickly, and the first time is less than the delay time, that is, before the first trigger T1 maintains its original state, the reset signal T1R of the first trigger T1 is valid, and the output signal TU1 of the inverting output end of the first trigger T1 is reset to 1. After the delay time, TU1 remains at 1, turning on the synchronous rectifier.

[0079] The body diode corresponding to the synchronous rectifier is turned on during the parasitic oscillation time, Vds decreases slowly from Vth1 to Vth2, the second time is greater than the delay time, and before the first trigger T1 maintains its original state, the set signal T1S of the first trigger T1 is valid, so that the output signal TU1 of the inverting output end of the first trigger T1 is set to 0. After the second time, the reset signal T1R of the first trigger T1 is 1, and the output signal TU1 of the inverting output end of the first trigger T1 is maintained at 0, and during the time from t4 to t7, the TU1 signal is set to 0 by CU4 and maintained at 0, the synchronous rectifier is in the off state, and can be maintained in the off state after t7, thereby avoiding the mis-conduction of the synchronous rectifier during the parasitic oscillation time.

[0080] The re-conduction of the synchronous rectifier requires that its body diode is normally turned on and Vds is reduced from Vth1 to Vth2. That is, the synchronous rectification control circuit of the embodiment of the present invention can control the synchronous rectifier to turn on the synchronous rectifier only when its body diode is normally turned on, which can effectively avoid mis-conduction of the synchronous rectifier during the parasitic oscillation time.

[0081] The synchronous rectification control circuit of the present invention sets a delay time. After the delay time has passed, the set end of the first trigger is 1, and the first trigger is an ordinary trigger. The reset signal of its reset end is determined according to the speed at which the drain-source voltage of the synchronous rectifier tube decreases from the first reference signal level to the second reference signal level, wherein the body diode of the synchronous rectifier tube corresponding to the fast speed is normally turned on, the reset signal is valid before the set signal is 1, the inverting output end of the first trigger is reset to 1, and is maintained at 1 after the delay time has passed, so as to control the synchronous rectifier tube to turn on; the body diode of the synchronous rectifier tube corresponding to the slow speed is turned on within the parasitic oscillation time, the reset signal is valid after the set signal is 1, the inverting output end of the first trigger is set to 0, and then maintained at 0, so as to avoid the synchronous rectifier tube being mis-turned on within the parasitic oscillation time.

[0082] Those skilled in the art should know that the logic controls such as "high level" and "low level", "set" and "reset", "AND gate" and "OR gate", "in-phase" and "inverted" in the above-mentioned logic controls can be interchanged or changed with each other, and the same function or purpose as the above-mentioned embodiment can be achieved by adjusting the subsequent logic controls.

[0083] The effects or advantages described in the specification may not be reflected in the actual experimental examples due to the uncertainty of specific conditions and parameters or other factors. The effects or advantages described in the specification are not used to limit the scope of the invention.

[0084] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A synchronous rectification control circuit, comprising a synchronous rectifier drain-source voltage receiving end and a synchronous rectifier gate control signal output end, characterized in that: include: A first comparator, comprising an input terminal coupled to the synchronous rectifier drain-source voltage receiving terminal, a first reference signal input terminal and a first control signal output terminal; A delay circuit, comprising an input terminal coupled to the first control signal output terminal and a second control signal output terminal, the delay circuit comprising a capacitor, a switch and a third comparator, the first terminal of the capacitor being coupled to the output terminal of the current source, the second terminal being grounded, the switch being connected in parallel to both ends of the capacitor, the switch comprising a switch control terminal, the switch control terminal being coupled to the first control signal output terminal, the third comparator comprising an input terminal coupled to the first terminal of the capacitor, a third reference signal input terminal and an output terminal, the output terminal of the third comparator being the second control signal output terminal; A second comparator comprises an input terminal coupled to the synchronous rectifier drain-source voltage receiving terminal, a second reference signal input terminal and a third control signal output terminal; as well as A first trigger, wherein a first input terminal of the first trigger is coupled to a second control signal output terminal of the delay circuit, a second input terminal of the first trigger is coupled to a third control signal output terminal of the second comparator, and an output terminal of the first trigger is coupled to a gate control signal output terminal of the synchronous rectifier; An OR gate, coupled between the second control signal output terminal and the first input terminal of the first trigger, the OR gate comprising a first input terminal, a second input terminal and an output terminal, the second input terminal of the OR gate being coupled to the second control signal output terminal, and the output terminal of the OR gate being coupled to the first input terminal of the first trigger; A pulse generator, wherein an input terminal of the pulse generator is coupled to the first control signal output terminal, and a pulse output terminal of the pulse generator is coupled to a first input terminal of the OR gate; an AND gate, the AND gate comprising a first input terminal coupled to the first control signal output terminal, a second input terminal coupled to the output terminal of the first trigger, and an output terminal; A second trigger, wherein a set terminal of the second trigger is coupled to the output terminal of the AND gate, and an output terminal of the second trigger is coupled to the gate control signal output terminal of the synchronous rectifier; as well as A synchronous rectifier shutdown detection module includes a fourth comparator, wherein the fourth comparator includes an input terminal coupled to the synchronous rectifier drain-source voltage receiving terminal, a fourth reference signal input terminal, and a synchronous rectifier shutdown signal output terminal coupled to the reset terminal of the second trigger, The level of the first reference signal is greater than 0, and the level of the fourth reference signal is less than 0 and greater than the level of the second reference signal.

2. The synchronous rectification control circuit according to claim 1, characterized in that: The delay circuit includes a third reference signal input terminal, and the third reference signal input terminal is coupled to a third reference signal output terminal of an external third reference signal configuration circuit.

3. The synchronous rectification control circuit according to claim 1, characterized in that: The delay circuit further includes an inverter, which is forward coupled between the first control signal output terminal and the switch control terminal of the switch; The switch is an NMOS tube, and the gate of the NMOS tube is the switch control terminal.

4. The synchronous rectification control circuit according to claim 1, characterized in that: The first trigger is an RS trigger, the set end of the RS trigger is the first input end of the first trigger, the reset end of the RS trigger is the second input end of the first trigger, and the inverting output end of the RS trigger is the output end of the first trigger.

5. A voltage converter, characterized in that: include: A transformer, wherein the transformer is connected to a primary circuit and a secondary circuit, wherein the secondary circuit includes a synchronous rectifier tube; The synchronous rectification control circuit according to any one of claims 1 to 4, wherein a synchronous rectifier gate control signal output terminal of the synchronous rectification control circuit is coupled to a gate of the synchronous rectifier.

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