Processor and core switching processing method

Abstract

The present invention discloses a processor having a trusted core and an untrusted core. The processor comprises a program status register, a switching status register and a switching control unit. The program status register is suitable for storing a current core identification bit and a starting core identification bit. The current core identification bit indicates whether the current core of the processor is a trusted core or an untrusted core, and the starting core identification bit indicates whether the core of the processor before switching to the current core is a trusted core or an untrusted core. The switching status register is suitable for storing a switching status identification bit. The switching status identification bit indicates a core switching mode. The switching control unit is suitable for receiving a core switching request, and processing the core switching request according to the current core identification bit, the starting core identification bit and the switching status identification bit to perform core switching. The present invention also discloses a core switching request processing method executed in the processor and a system on chip comprising the processor.

Description

Technical Field

[0001] The present invention relates to the field of processors, and in particular to the field of processors with a trusted core and a non-trusted core. Background Art

[0002] In the field of mobile Internet and Internet of Things, for security reasons, a new trusted world state is added to the processor's operating mode. The processors in the trusted world, the system IP with trusted attributes, and sensitive and important software and hardware resources in other systems are divided into the trusted world. Through hardware mechanisms, it is ensured that the resources in the trusted world can only be accessed by members of the trusted world, thereby achieving isolation between the trusted world and the non-trusted world, ensuring the confidentiality and integrity of security resources.

[0003] To this end, a trusted kernel can be added to the processor, and a trusted kernel operation mode can be added to allow some programs with security requirements to be executed in the trusted kernel. Therefore, the processor needs to perform kernel switching during operation, that is, world switching. How to quickly and safely perform kernel switching is a problem that needs to be solved in this field.

[0004] Especially for smart devices such as IoT devices. These devices are huge in number and widely distributed. Unlike existing PCs or mobile terminals, these devices face more security issues due to their use in various scenarios. Therefore, for these devices, how to complete kernel switching more safely and quickly is one of the problems that needs to be solved urgently. Summary of the invention

[0005] To this end, the present invention provides a new kernel switching solution to try to solve or at least alleviate at least one of the above problems.

[0006] According to one aspect of the present invention, a processor is provided, which has a trusted core and an untrusted core. The processor includes a program status register, a switching status register and a switching control unit. The program status register is suitable for storing a current core identification bit and a starting core identification bit. The current core identification bit indicates whether the current core of the processor is a trusted core or an untrusted core, and the starting core identification bit indicates whether the core of the processor before switching to the current core is a trusted core or an untrusted core. The switching status register is suitable for storing a switching status identification bit. The switching status identification bit indicates a core switching mode. The switching control unit is suitable for receiving a core switching request, and processing the core switching request according to the current core identification bit, the starting core identification bit and the switching status identification bit to perform core switching.

[0007] Optionally, in a processor according to the present invention, a core switching request includes a switch initiation request and a switch return request corresponding to the switch initiation request, and the switch initiation request has a corresponding core switching mode, and the switch control unit is suitable for setting a starting core identification bit according to the current core of the processor upon receiving the switch initiation request, setting a switch state identification bit according to the core switching mode corresponding to the switch initiation request, and setting a current core identification bit according to the target core of the switch initiation request to perform core switching; and the switch control unit is also suitable for determining the target core of the switch return request according to the value of the starting core identification bit upon receiving the switch return request, determining the switch initiation request corresponding to the switch return request according to the switch state identification bit, and setting the current core identification bit according to the determined target core to perform core switching.

[0008] Optionally, in the processor according to the present invention, the core switching mode includes a mode corresponding to the switching instruction and a mode corresponding to the interruption, and the processor further includes an instruction execution unit and an interruption initiation unit. The instruction execution unit is coupled to the switching control unit and is adapted to execute the switching instruction to issue a switching initiation request corresponding to the switching instruction to the switching control unit, and to execute the return instruction to issue a switching return request to the switching control unit. The interruption initiation unit is coupled to the switching control unit and is adapted to generate an interruption to issue a switching initiation request corresponding to the interruption to the switching control unit.

[0009] Optionally, the processor according to the present invention also includes: a field maintenance unit, coupled to the switching control unit, suitable for storing the field status information of the current core of the processor into the stack, and suitable for restoring the field status information of the core from the stack; and the switching control unit is also suitable for instructing the field maintenance unit to store and / or restore the core field status information when processing a core switching request.

[0010] Optionally, in a processor according to the present invention, a program status register includes a trusted kernel program status register and an untrusted kernel program status register, and when the processor is in a trusted kernel, the trusted kernel program status register is used as a program status register, and when the processor is in an untrusted kernel, the untrusted kernel program status register is used as a program status register; and a switching status flag includes a trusted kernel switching status flag and an untrusted kernel switching status flag, the trusted kernel switching status flag indicates a kernel switching mode from an untrusted kernel to a trusted kernel, and the untrusted kernel switching status flag indicates a kernel switching mode from a trusted kernel to an untrusted kernel.

[0011] Optionally, the processor according to the present invention also includes: a trusted caller base address register, suitable for storing address information of a cross-core caller in a trusted kernel; an untrusted caller base address register, suitable for storing address information of a cross-core caller in an untrusted kernel; and a switching control unit adapted to obtain the address of the cross-core caller corresponding to the switching instruction from the trusted caller base address register or the untrusted caller base address register when processing a kernel switching request triggered by a switching instruction, so as to instruct the instruction execution unit to execute instructions starting from the obtained address.

[0012] Optionally, the processor according to the present invention also includes a trusted exception program base address register, which is suitable for storing address information of the exception handler in the trusted kernel; an untrusted exception program base address processor, which is suitable for storing address information of the exception handler in the untrusted kernel; and a switching control unit is suitable for obtaining the address of the exception handler corresponding to the interrupt from the trusted exception program base address register or the untrusted exception program base address register when processing a kernel switching request triggered by an interrupt, so as to instruct the instruction execution unit to start executing instructions from the obtained address.

[0013] Optionally, in a processor according to the present invention, the program status register is also suitable for storing a supervisor status bit, which indicates whether the processor is currently in normal user mode or supervisor mode; the field maintenance unit is suitable for storing the field status information of the core in which the processor is currently located in the supervisor stack; and the switching control unit is suitable for setting the supervisor status bit to indicate the supervisor mode after performing the core switching when processing the switching initiation request.

[0014] According to another aspect of the present invention, a method for processing a kernel switching request is provided, which is suitable for execution in a processor having a trusted kernel and an untrusted kernel, the processor comprising a program status register and a switching status register, the kernel switching request comprising a switching initiation request and a switching return request corresponding to the switching initiation request, and the switching initiation request has a corresponding kernel switching mode, the method comprising the steps of: receiving the switching initiation request and processing it so as to set a starting kernel identification bit in the program status register according to the kernel in which the processor is currently located, setting a switching status identification bit in the switching status register according to the kernel switching mode corresponding to the switching initiation request, and setting a current kernel identification bit in the program status register according to the target kernel of the switching initiation request to perform kernel switching.

[0015] According to yet another aspect of the present invention, a system on chip is provided, comprising the processor according to the present invention.

[0016] According to another aspect of the present invention, there is provided an intelligent device including the system on chip according to the present invention.

[0017] According to the solution of the present invention, by introducing the current kernel identification bit and the starting kernel identification bit in the program status register of the processor, and introducing the switching status register storing the switching status, the previous kernel status can be recorded before the kernel switching, so that the kernel can be correctly returned to the state before the kernel switching after the kernel switching, so that the kernel switching can be conveniently performed. Therefore, according to the solution of the present invention, the program status register and the switching status register can be used to guide the processor to perform the kernel switching through instructions, thereby significantly simplifying the processing process of the kernel switching.

[0018] For smart devices such as IoT devices, when these devices are deployed in a complex external environment, it is necessary to quickly complete the kernel switching in order to provide a safe operation mode. Therefore, the solution according to the present invention is particularly suitable for use in various IoT devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] To achieve the above and related purposes, certain illustrative aspects are described herein in conjunction with the following description and accompanying drawings, which indicate various ways in which the principles disclosed herein can be practiced, and all aspects and their equivalents are intended to fall within the scope of the claimed subject matter. The above and other purposes, features and advantages of the present disclosure will become more apparent by reading the following detailed description in conjunction with the accompanying drawings. Throughout the present disclosure, the same reference numerals generally refer to the same parts or elements.

[0020] Figure 1 A schematic diagram of a processor 100 according to an embodiment of the present invention is shown;

[0021] Figure 2 A schematic diagram of a processor 200 according to another embodiment of the present invention is shown;

[0022] Figure 3 A schematic diagram showing a core switching method 300 according to an embodiment of the present invention; and

[0023] Figure 4 A schematic diagram of a system on chip (SoC) 400 according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0024] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0025] Figure 1 FIG. 1 is a schematic diagram of a processor 100 according to an embodiment of the present invention. Figure 1 As shown, the processor 100 is divided into a trusted core 110 and an untrusted core 120. The trusted core 110 and the untrusted core 120 and related resources constitute a trusted world and an untrusted world respectively. To ensure security, the two are logically independent.

[0026] The processor 100 can execute instructions in the trusted kernel 110, i.e., the trusted world. At this time, the processor 100 is in a trusted execution environment and can access the trusted resources 112 dedicated to the trusted kernel 110. The processor 100 can also execute instructions in the untrusted kernel 120, i.e., the untrusted world. At this time, the processor 100 is in an untrusted execution environment and can access the untrusted resources 122 dedicated to the untrusted kernel 120. According to one embodiment of the present invention, when there is only one physical kernel in the processor 100, the physical kernel can run in the mode of the trusted kernel 110, and can perform kernel switching to switch to the mode of the untrusted kernel 120 to run. When there are multiple physical kernels in the processor 100, each physical kernel can also run in the mode of the trusted kernel 110 or the untrusted kernel 120, and can perform kernel switching to switch to a different kernel to run.

[0027] During the processing of instructions, if the processor 100 encounters a situation where a specific program needs to be executed in another core, the processor 100 performs core switching to enter another core to execute the specific program, and returns to the original core to continue processing subsequent instructions after the specific program is executed. To this end, the processor 100 has three ways to switch between cores, two of which are ways to initiate core switching, that is, ways to trigger the processor 100 to initiate core switching; the other is a core switching method that returns to the original core after performing core switching and completing the specific program processing.

[0028] According to an embodiment of the present invention, the method of initiating core switching includes executing a switching instruction and an interrupt.

[0029] The processor 100 provides a special instruction, such as a wsc instruction. When the processor 100 executes the wsc instruction, a core switch request is triggered, so that the processor 100 processes the core switch request and performs core switch, and executes a program corresponding to the task specified by the wsc instruction in the new core.

[0030] In addition, when the processor 100 receives an interrupt from an interrupt source during the execution of an instruction, if the interrupt attribute is inconsistent with the core in which the current processor 100 is located, a core switching request will also be triggered, so that the processor 100 processes the core switching request and performs core switching, and executes the corresponding interrupt processing program in the new core. For example, when the processor 100 executes an instruction in the trusted core 110, if an untrusted interrupt is received, a core switching request from the trusted core to the untrusted core will be generated in the processor 100, so that the processor 100 performs core switching and enters the untrusted core to execute the interrupt processing program corresponding to the untrusted interrupt.

[0031] Whether by executing a switch instruction or an interrupt, the processor 100 will process the corresponding kernel switch request and enter the new kernel to execute the corresponding program. When the execution of the corresponding program is completed, the processor 100 executes a special return instruction to trigger the kernel switch request. The processor 100 then processes the kernel switch request and returns to the previous kernel. According to one embodiment of the present invention, a special instruction ret is provided in the processor 100. In this way, when the processor 100 completes the execution of the task or interrupt handler specified by the wsc instruction, the ret instruction is executed to issue a kernel switch request, and the kernel switch is performed to return to the previous kernel.

[0032] As described above, the core switching request that the processor 100 can process includes a switch initiation request and a switch return request corresponding to the switch initiation request. The switch initiation request has a corresponding core switching mode, that is, a mode corresponding to the switch instruction (wsc) and a mode corresponding to the interrupt. The switch return request is generated by executing the return instruction (ret).

[0033] The processor 100 further includes a public resource 130 that is accessible in both the trusted world and the non-trusted world. According to one embodiment of the present invention, the public resource 130 loads different contents depending on whether the processor 100 is in the trusted core or the non-trusted core.

[0034] According to one embodiment, the common resource 130 includes a general purpose register GPR 132, which is generally used to transmit and temporarily store data, and can also participate in arithmetic and logical operations and save the operation results. Since the access speed of the register is faster than that of the memory, multiple general purpose registers are designed in modern processor architectures to speed up the execution speed of the processor.

[0035] In addition, the common resource 130 also includes a vector general register VGPR 134. Similar to the function of GPR 132, VGPR 134 is also a register used to transmit and temporarily store data, and participate in arithmetic and logical operations. VGPR 134 can have more bits than GPR 134, and can be more efficiently used for floating-point operations in the vector operation unit VDSP and the floating-point operation unit FPU.

[0036] In addition, optionally, the common resource 130 also includes a control register CR 136. The CR 136 can control and determine the operation mode of the processor and set the system operation function, I / O control, etc. The CR 136 in the common resource 130 is generally a register that does not contain security information. The control register CR containing security information can be set for the trusted core 110 and the untrusted core 120 respectively, such as the trusted control register 112 contained in the trusted core 110 and the untrusted control register 122 in the untrusted core 120.

[0037] According to one embodiment of the present invention, in order to support switching between a trusted core and an untrusted core, the processor 100 further includes a trusted program status register T_PSR 114 and an untrusted program status register NT_PSR 124 respectively located in the trusted core 110 and the untrusted core 120. These two registers have substantially the same result and can be accessed in the same logical manner, i.e., in the name of the program status register PSR. That is, when the processor 100 is in the trusted core 110, when the processor 100 executes an instruction to access the program status register PSR, the instruction accesses the trusted program status register T_PSR 114. When the processor 100 is in the untrusted core 120, when the processor 100 executes an instruction to access the program status controller PSR, the instruction accesses the NT_PSR 124 at this time.

[0038] T_PSR 114 and NT_PSR 124 have a current kernel identification bit T. The current kernel identification bit T indicates whether the processor 100 is currently executing instructions in a trusted kernel or an untrusted kernel. According to one embodiment of the present invention, T is a bit in register PSR. When the value of T is 1, it indicates that the processor 100 is currently in a trusted kernel. When the value of T is 0, it indicates that the processor 100 is currently in an untrusted kernel. Therefore, the T bit value of T_PSR 114 is fixed to 1, and the T bit value of NT_PSR 124 is fixed to 0. Optionally, the processor 100 can also be instructed to perform kernel switching by modifying the T bit value of PSR. It should be noted that the above description of the T value is schematic. For example, according to another embodiment, the T value can be 0 to indicate that the processor 100 is in a trusted kernel, and the T value can be 1 to indicate an untrusted kernel, and the corresponding T bit values ​​of T_PSR 114 and NT_PSR 124 can be fixed to 0 and 1, respectively. The present invention is not limited to the specific value of T, and all methods that can indicate different cores with different T values ​​are within the protection scope of the present invention. Similarly, the values ​​of each status bit in other registers are also illustrative, and different value methods can be adopted according to actual design requirements without departing from the protection scope of the present invention.

[0039] T_PSR 114 and NT_PSR 124 also have a starting kernel identification bit SP. The starting kernel identification bit SP indicates whether the processor 100 is in a trusted kernel or an untrusted kernel before the kernel switch is performed, that is, it indicates the starting kernel of the kernel switch. According to one embodiment of the present invention, the starting kernel identification bit SP is a bit in the program status register PSR. When the value of PSR.SP is 1, it indicates that the starting kernel at the time of kernel switch is a trusted kernel; when the value of PSR.SP is 0, it indicates that the starting kernel at the time of kernel switch is an untrusted kernel. When the processor 100 performs a kernel switch, the value of the PSR.SP bit is set according to the kernel in which the processor 100 is currently located, so that after the kernel switch is performed, it can return to the original kernel.

[0040] According to one embodiment of the present invention, the processor 100 further includes a switch status register T_WSSR 116, in which a switch status flag is stored. The switch status flag indicates the core switch mode, that is, indicates whether the request is initiated by executing a switch instruction or by responding to an interrupt when the processor processes a switch initiation request in a core switch request. Considering that the switch status register is used when performing a core switch process, according to one embodiment, the switch status register T_WSSR 116 is in the trusted core 110.

[0041] Optionally, according to an embodiment of the present invention, the switching state identification bit includes a trusted kernel switching state identification bit TSC and an untrusted kernel switching state identification bit NTSC. T_WSSR.TSC indicates a kernel switching mode for switching to a trusted kernel, while T_WSSR.NTSC indicates a kernel switching mode for switching to an untrusted kernel. According to one embodiment, when the value of TSC is 0, it indicates switching to a trusted kernel by means of a trusted interrupt; and when the value of TSC is 1, it indicates switching to a trusted kernel by executing a switching instruction wsc. Similarly, when the value of NTSC is 0, it indicates switching to an untrusted kernel by means of an untrusted interrupt, and when the value of NTSC is 1, it indicates switching to an untrusted kernel by executing a switching instruction wsc. According to one embodiment, TSC and NTSC are both one bit in a switching state register. The present invention is not limited to the above provisions, and any method that can be defined for various switching modes in the switching state register T_WSSR is within the protection scope of the present invention.

[0042] In addition, the processor 100 also includes a trusted cross-core caller base address register T_EBR 118 in the trusted core 110 and an untrusted cross-core caller base address register NT_EBR 128 in the untrusted core 120. The address information of the trusted program called across the core is stored in T_EBR 118, and similarly, the address information of the untrusted program called across the core is stored in NT_EBR 128. According to one embodiment, the T_EBR and NT_EBR registers store the entry vector table of the cross-core task caller. The cross-core caller corresponding to the trusted task or untrusted task specified by wsc can find the corresponding entry address in T_EBR 118 and NT_EBR 128, respectively, so that the processor 100 can jump to the entry address to execute the instructions in the cross-core caller.

[0043] In addition, the processor 100 further includes a trusted exception program base register T_VBR 117 in the trusted core 110 and a non-trusted exception program base register NT_VBR 127 in the non-trusted core 120 .

[0044] T_VBR 117 is an exception entry base address register in the trusted kernel 110. All exceptions or entry addresses of interrupt service routines in the trusted kernel 110 are stored in an exception vector table with T_VBR 117 as the base address. When the processor 100 responds to a trusted interrupt, the processor uses T_VBR 117 as the base address to obtain the corresponding interrupt service routine entry address from the exception vector table, thereby facilitating the processor 100 to jump to the entry address to execute instructions in the interrupt service routine.

[0045] Similarly, NT_VBR 127 is an exception entry base address register in the untrusted kernel 120. The entry addresses of all interrupt service routines in the untrusted kernel 120 are stored in an exception vector table with NT_VBR 127 as the base address. When the processor 100 responds to an untrusted interrupt, the processor uses NT_VBR 127 as the base address to obtain the corresponding interrupt service routine entry address from the exception vector table, thereby facilitating the processor 100 to jump to the entry address to execute instructions in the interrupt service routine.

[0046] When the processor 100 processes an interrupt, whether in the trusted core 110 or the untrusted core 120, it is necessary to save the current state of the core, such as the program state and counter information of the core, before processing the interrupt, so as to restore the core state after the interrupt processing is completed. To this end, the processor 110 includes an exception preservation state register T_EPSR 119a and an exception preservation program counter T_EPC 119b in the trusted core 110, and an exception preservation state register NT_EPSR 129a and an exception preservation program counter NT_EPC 129b in the untrusted core 120.

[0047] T_EPSR 119a can preserve the data in T_PSR 114 during interrupt or exception processing in the trusted kernel, and T_EPC 119b can preserve the value of the program counter. In this way, when the processor 100 completes the interrupt processing, the value of T_PSR 114 can be restored from T_EPSR 119a, and the program counter can be restored from the exception-preserved program counter T_EPC 119b to continue the execution of the subsequent program.

[0048] Similarly, NT_EPSR 129a can preserve the data in NT_PSR 124 during interrupt or exception processing in the non-trusted kernel, and NT_EPC 129b can preserve the value of the program counter. In this way, when the processor 100 completes the interrupt processing, the value of NT_PSR 114 can be restored from NT_EPSR 129a, and the program counter can be restored from the exception-preserved program counter NT_EPC 129b to continue the execution of the subsequent program.

[0049] In addition, the processor 100 may also include a trusted user stack 115 in the trusted kernel 110 and an untrusted user stack 125 in the untrusted kernel 120. The trusted user stack 115 is used to store the field state information of the trusted kernel, such as the values ​​of various registers and program counters. Similarly, the untrusted user stack 125 is used to store the field state information of the untrusted kernel. When the kernel is switched, the field state information of the kernel can be stored in the user stack before the switch, so that after the kernel is switched back, the field state information can be restored from the user stack to continue the execution of subsequent instructions.

[0050] Optionally, according to an embodiment of the present invention, the processor 100 may further include a supervisor mode and a normal user mode. The trusted kernel 110 and the untrusted kernel 120 both have supervisor mode and normal user mode, that is, the processor 100 includes a trusted kernel supervisor mode, a trusted kernel normal user mode, an untrusted kernel supervisor mode, and an untrusted kernel normal user mode.

[0051] The program status register PSR also includes a user status bit S to indicate whether the processor 100 is currently in the supervisor mode or the normal user mode. According to one embodiment, when the value of the S bit is 0, it indicates that the processor 100 is currently in the normal user mode, and when the value of S is 1, it indicates that the processor 100 is currently in the supervisor mode. Therefore, the mode in which the processor 100 is in can be determined based on the values ​​of the T and S bits in the program status register PSR.

[0052] Optionally, in the case of the existence of supervisor mode and normal user mode, during the kernel switching, the user stack in the supervisor mode is used to save the kernel field state, and after the kernel switching is performed, the kernel is switched to the supervisor mode for operation. Therefore, the program status register (T_PSR 114 and NT_PSR 124), the switch status register T_WSSR 116, the cross-kernel caller base address register (T_EBR 118 and NT_EBR 128), and the exception program base address register (T_VBR 117 and NT_VBR 127) are all available in the supervisor mode.

[0053] It should be noted that the present invention is not limited to whether the processor 100 has a supervisor mode and a normal user mode. As long as the processor 100 can switch between a trusted core and an untrusted core, the processor is within the protection scope of the present invention.

[0054] In addition, it should be noted that the present invention describes the status and control information during kernel switching by taking the T, SP, TSC and NTSC bits contained in the program status register (PSR) and the switch status register (WSSR) as examples, but the present invention is not limited to this. According to actual needs, registers such as PSR and / or WSSR can be replaced or merged with other registers, or each status bit (T, SP, TSC and NTSC) can be deployed in other registers. As long as the processor includes status bits or registers that implement the above functions, the design of the processor is within the protection scope of the present invention.

[0055] Figure 2 FIG. 2 is a schematic diagram of a processor 200 according to another embodiment of the present invention. Figure 1 Components such as various registers of the processor 100 in the trusted core 110 and the untrusted core 120 are shown. Figure 2 The various components of the processor 200 used for instruction execution are shown. The processors 100 and 200 illustrate different aspects of the processors claimed in the present invention, but both are within the scope of protection of the present invention.

[0056] like Figure 2 As shown, the processor 200 includes a switching control unit 210. The switching control unit 210 receives a core switching request and processes the core switching request according to the values ​​stored in the program status register PSR and the switching status register T_WSSR to perform core switching.

[0057] As described above, the core switching request includes a switching initiation request and a corresponding switching return request, wherein the switching initiation request has a corresponding core switching mode. The core switching mode includes being triggered by the processor 200 executing a switching instruction and generating an interrupt in the processor 200. The switching return request is triggered by the processor 200 executing a return instruction.

[0058] When receiving the switching initiation request, the switching control unit 210 sets the starting core identification bit PSR.SP according to the core currently located by the processor 200. According to an embodiment, when the current core of the processor 200 is the trusted core 110, the value of the PSR.SP bit can be set to 1 at this time, and when the current core of the processor 200 is the untrusted core 120, the value of the PSR.SP bit can be set to 0.

[0059] Subsequently, the switching control unit 210 sets the switching state flag in the switching state register T_WSSR according to the core switching mode. According to one embodiment of the present invention, the switching state register T_WSSR includes a trusted core switching state flag TSC and an untrusted core switching state flag NTSC. When the processor 200 is currently in the trusted core 110 and is to be switched to the untrusted core 120, the value of NTSC can be set to indicate the corresponding switching mode; similarly, when the processor 200 is currently in the untrusted core 120 and is to be switched to the trusted core 110, the value of TSC can be set to indicate the corresponding switching mode.

[0060] Next, the switch control unit 210 sets the T bit in the program status register PSR to indicate the target core for core switching, so that the processor 200 performs core switching.

[0061] When receiving a switch return request, the switch control unit 210 determines the target core of the switch return request according to the value of the starting core identification bit PSR.SP, determines the switch initiation request corresponding to the switch return request according to the switch status identification bit in the switch status register T_WSSR, and sets the value of the current core identification bit PSR.T to indicate the determined target core for core switching, so as to return to the core state when the switch initiation request was issued.

[0062] According to an embodiment of the present invention, the handover control unit 210 processes the handover return request according to the values ​​given in the following Table 1:

[0063] Table 1: Switch return request judgment

[0064]

[0065] like Figure 2 As shown, the processor 200 further includes an instruction execution unit 220 and an interrupt initiation unit 230 coupled to the switching control unit 210. The instruction execution unit 220 executes instructions in the trusted core 110 and the untrusted core 120, and when executing the switching instruction wsc, sends a switching initiation request corresponding to the switching instruction wsc to the switching control unit 210, so that the switching control unit 210 processes the switching initiation request to perform core switching.

[0066] The instruction execution unit 220 may also execute corresponding programs after the core switching, such as instructions in the program corresponding to the cross-core task specified in the wsc instruction, and instructions in the interrupt handling program. When the execution of these programs is completed, the instruction execution unit 220 executes the return instruction ret to issue a switch return request to the switch control unit 210, so that the switch control unit 210 performs the core switching and returns to the core state before the switch initiation request is issued.

[0067] The interrupt initiation unit 230 generates an interrupt to issue a switching initiation request corresponding to the interrupt to the switching control unit 210. The interrupts that can be generated by the interrupt initiation unit 230 include trusted interrupts and untrusted interrupts. Trusted interrupts are to be processed under the trusted kernel, while untrusted interrupts are to be processed in the untrusted kernel. When the processor 200 is in the untrusted kernel 120 and the interrupt initiation unit 230 generates a trusted interrupt, or when the processor 200 is in the trusted kernel and the interrupt initiation unit 230 generates an untrusted interrupt, a kernel switch is required to perform interrupt processing. Therefore, the interrupt initiation unit 2340 issues a switching initiation request corresponding to the interrupt to the switching control unit 210 so that the switching control unit 210 performs a kernel switch so as to switch to the appropriate kernel for interrupt processing.

[0068] like Figure 2 As shown, the processor 200 also includes a field maintenance unit 240 coupled to the switching control unit 210. The field maintenance unit 240 can store the field status information of the current kernel of the processor 200 in the user stack, or restore the field status information of the kernel from the user stack. According to one embodiment, when the processor 200 is in a trusted kernel, the field maintenance unit 240 can store the field status information of the trusted kernel in the user stack of the trusted kernel (especially the super user stack of the trusted kernel), or restore the field status information of the trusted kernel from the user stack of the trusted kernel. Similarly, when the processor 200 is in an untrusted kernel, the field maintenance unit 240 can store the field status information of the untrusted kernel in the user stack of the untrusted kernel (especially the super user stack of the untrusted kernel), or restore the field status information of the untrusted kernel therefrom.

[0069] When the switching control unit 210 processes the kernel switching request, it will instruct the scene maintenance unit 240 to store and / or restore the kernel scene state information. When the switching control unit 240 processes the switching initiation request, before the kernel switching, the scene state information of the current kernel is stored in the user stack of the kernel. Accordingly, when the switching control unit 240 processes the switching return request, the previously stored scene state information can be restored from the user stack of the target kernel after the kernel switching, so as to continue the execution of subsequent instructions.

[0070] The following are Figure 2 The specific process of core switching of each component in the processor 200 shown is described.

[0071] Implementation 1:

[0072] When the processor 200 is in the untrusted kernel 120, the instruction execution unit 220 executes the switching instruction wsc and issues a kernel switching request (a switching initiation request to the trusted kernel). The switching control unit 210 receives the request, instructs the field maintenance unit 240 to store the field status information of the untrusted kernel 120 in the user stack of the untrusted kernel (especially the super user stack of the untrusted kernel), sets the trusted kernel switching state identification bit T_WSSR.TSC in the switching state register to 1 to indicate that the trusted kernel is switched by executing the wsc instruction, and sets the starting kernel identification bit PSR.SP in the program status register PSR to 0 to indicate that the starting kernel is an untrusted kernel. Then, the current kernel identification bit PSR.T in the program status register PSR is set to 1 to indicate that the target kernel is a trusted kernel so as to switch to the trusted kernel 110. Then, the switching control unit 210 instructs the instruction execution unit 220 to execute the instructions in the program corresponding to the cross-core task indicated by the switching instruction wsc. According to one embodiment, the switching control unit 210 obtains the entry address of the program corresponding to the cross-core calling task from the trusted calling program base address register T_EBR 118, and sends the address to the instruction execution unit 220, so that the instruction execution unit 220 starts executing instructions from the address, that is, executes the program instructions corresponding to the cross-core calling task.

[0073] Implementation 2:

[0074] When the processor 200 is in the trusted kernel 110, the instruction execution unit 220 executes the switching instruction wsc and issues a kernel switching request (a switching initiation request to the untrusted kernel). The switching control unit 210 receives the request, instructs the field maintenance unit 240 to store the field status information of the trusted kernel 110 in the user stack of the trusted kernel (especially the super user stack of the trusted kernel), sets the untrusted kernel switching state identification bit T_WSSR.NTSC in the switching state register to 1, to indicate that the switch is made to the untrusted kernel by executing the wsc instruction, and sets the starting kernel identification bit NTPSR.SP in the program status register PSR to 1 to indicate that the starting kernel is a trusted kernel. Then, the current kernel identification bit PSR.T in the program status register PSR is set to 0, to indicate that the target kernel is an untrusted kernel so as to switch to the untrusted kernel 120. Then, the switching control unit 210 instructs the instruction execution unit 220 to execute the instructions in the program corresponding to the cross-core task indicated by the switching instruction wsc. According to one embodiment, the switching control unit 210 obtains the entry address of the program corresponding to the cross-core calling task from the non-trusted calling program base address register NT_EBR128, and sends the address to the instruction execution unit 220, so that the instruction execution unit 220 starts executing instructions from the address, that is, executes the program instructions corresponding to the cross-core calling task.

[0075] Implementation 3:

[0076] When the processor 200 is in the untrusted kernel 120, the interrupt initiation unit 230 generates a trusted interrupt, and accordingly sends a kernel switching request (a switch initiation request to the trusted kernel) to the switching control unit 210. The switching control unit 210 receives the request and instructs the field maintenance unit 240 to store the field status information of the untrusted kernel 120 in the user stack of the untrusted kernel (especially the super user stack of the untrusted kernel). The switching control unit 210 sets the current kernel identification bit PSR.T in the program status register PSR to 1 to indicate that the target kernel is a trusted kernel so as to switch to the trusted kernel 110. Subsequently, in the trusted kernel 110, the value of the trusted kernel program status register T_PSR is backed up, the starting kernel identification bit PSR.SP in the program status register PSR is set to 0 to indicate that the starting kernel is the untrusted kernel 120, and the trusted kernel switching state identification bit T_WSSR.TSC in the switching state register is set to 0 to indicate that the trusted kernel is switched to the trusted kernel by the way of the trusted interrupt trigger. Subsequently, the switching control unit 210 instructs the instruction execution unit 220 to execute the instructions in the interrupt handler corresponding to the trusted interrupt. According to one embodiment, the switching control unit 210 obtains the entry address of the interrupt handler corresponding to the trusted interrupt from the trusted exception program base address register T_VBR 117, and sends the address to the instruction execution unit 220, so that the instruction execution unit 220 starts executing instructions from the address, that is, executes the instructions in the corresponding interrupt handler.

[0077] Implementation 4:

[0078] When the processor 200 is in the trusted kernel 110, the interrupt initiation unit 230 generates an untrusted interrupt, and accordingly issues a kernel switching request (a switch initiation request to the untrusted kernel) to the switching control unit 210. The switching control unit 210 receives the request and instructs the field maintenance unit 240 to store the field status information of the trusted kernel 110 in the user stack of the trusted kernel (especially in the super user stack of the trusted kernel). The switching control unit 210 can also store the contents of each general register in the trusted kernel in the user stack of the trusted kernel, and clear the contents of these general registers. Subsequently, the switching control unit 210 sets the untrusted kernel switching state identification bit T_WSSR.NTSC in the switching state register to 0 to indicate that the field information has been pushed into the stack under the trusted kernel, and it is necessary to switch to the untrusted kernel by triggering an untrusted interrupt. The switching control unit 210 then sets the current kernel identification bit PSR.T in the program status register PSR to 0 to indicate that the target kernel is an untrusted kernel so as to switch to the untrusted kernel 120. Subsequently, in the untrusted kernel 120, the value of the untrusted kernel program status register NT_PSR is backed up, the starting kernel identification bit NTPSR.SP in the program status register PSR is set to 1 to indicate that the starting kernel is the trusted kernel 110, and then the switching control unit 210 instructs the instruction execution unit 220 to execute the instructions in the interrupt handling program corresponding to the untrusted interrupt. According to one embodiment, the switching control unit 210 obtains the entry address of the interrupt handling program corresponding to the untrusted interrupt from the untrusted exception program base address register NT_VBR 127, and sends the address to the instruction execution unit 220, so that the instruction execution unit 220 starts to execute instructions from the address, that is, executes the instructions in the corresponding interrupt handling program.

[0079] Implementation 5:

[0080] The processor 200 is in the trusted core 110, and the instruction execution unit 220 executes the return instruction ret. At this time, if the values ​​of the T bit and the SP bit in the PSR are inconsistent, that is, the value of the T bit is 1 and the value of the SP bit is 0, the instruction execution unit 220 issues a core switching request (that is, a switch return request to the non-trusted core).

[0081] The switching control unit 210 receives the request and performs the next step of processing according to the value of T_WSSR.TSC.

[0082] If the value of T_WSSR.TSC is 1 at this time, it means that the processor 200 enters the current trusted kernel 110 due to executing the wsc instruction. Therefore, the switching control unit sets the value of PSR.T to 0 to instruct the untrusted kernel to switch to the untrusted kernel. After switching to the untrusted kernel 120, the field maintenance unit 240 is instructed to restore the field status information of the untrusted kernel 120 from the user stack of the untrusted kernel (especially the super user stack of the untrusted kernel) so that the instruction execution unit 220 continues to execute instructions.

[0083] If the value of T_WSSR.TSC is 0 at this time, it means that the processor 200 enters the current trusted kernel 110 because of processing the trusted interrupt. Therefore, the switching control unit 210 first restores the value in the previously saved trusted kernel program status register T_PSR, and sets the value of PSR.T to 0 to instruct the untrusted kernel to switch to the untrusted kernel 120. After switching to the untrusted kernel 120, the switching control unit 210 instructs the field maintenance unit 240 to restore the field status information of the untrusted kernel 120 from the user stack of the untrusted kernel (especially the super user stack of the untrusted kernel) so that the instruction execution unit 220 continues to execute instructions.

[0084] Implementation 6:

[0085] The processor 200 is in the untrusted core 120, and the instruction execution unit 220 executes the return instruction ret. At this time, if the values ​​of the T bit and the SP bit in the PSR are inconsistent, that is, the value of the T bit is 0 and the value of the SP bit is 1, the instruction execution unit 220 issues a core switching request (that is, a switch return request to the trusted core).

[0086] The switching control unit 210 receives the request and performs the next step of processing according to the value of T_WSSR.NTSC.

[0087] If the value of T_WSSR.NTSC is 1 at this time, it means that the processor 200 enters the current non-trusted kernel 120 due to the execution of the wsc instruction. Therefore, the switching control unit sets the value of PSR.T to 1 to instruct the trusted kernel to switch to the trusted kernel. After switching to the trusted kernel 110, the field maintenance unit 240 is instructed to restore the field status information of the trusted kernel 110 from the user stack of the trusted kernel (especially the super user stack of the trusted kernel) so that the instruction execution unit 220 continues to execute instructions.

[0088] If the value of T_WSSR.NTSC is 0 at this time, it means that the processor 200 enters the current untrusted kernel 120 because of processing an untrusted interrupt. Therefore, the switching control unit 210 first restores the value in the previously saved untrusted kernel program status register NT_PSR, and sets the value of PSR.T to 1 to instruct the trusted kernel to switch to the trusted kernel 110. After switching to the trusted kernel 110, the switching control unit 210 instructs the field maintenance unit 240 to restore the field status information of the trusted kernel 110 from the user stack of the trusted kernel (especially the super user stack of the trusted kernel) so that the instruction execution unit 220 continues to execute instructions.

[0089] Combined with the above Figure 2 In the description, the components in the processor 100 or 200 are divided in a logical functional manner, and the processing performed by each component in the processor 200 for core switching is described. It should be noted that the above division of each part is schematic, and these components can be combined or split as needed without departing from the scope of protection of the present invention.

[0090] Figure 3 FIG. 3 is a schematic diagram of a core switching method 300 according to an embodiment of the present invention. Figure 1 Or the processor 100 or 200 described in 2 is executed so that the processor can perform core switching.

[0091] The method 300 is suitable for step S310. In step S310, a switch initiation request is received and processed. As described above, the kernel switch request includes a switch initiation request and a switch return request corresponding to the switch initiation request. The switch return request is triggered by the processor 200 executing a switch instruction and an interruption in the processor 200. The switch return request is triggered by the processor 200 executing a return instruction.

[0092] In step S310, when a switch initiation request is received, the starting kernel identification bit PSR.SP in the program status register PSR is set according to the kernel in which the processor is currently located. When the current kernel of the processor 200 is the trusted kernel 110, the value of the PSR.SP bit can be set to 1, and when the current kernel of the processor 200 is the untrusted kernel 120, the value of the PSR.SP bit can be set to 0. Subsequently, in step S310, the switch state identification bit in the switch state register T_WSSR is set according to the kernel switch mode corresponding to the received switch initiation request. According to one embodiment of the present invention, the switch state register T_WSSR includes a trusted kernel switch state identification bit TSC and an untrusted kernel switch state identification bit NTSC. When the processor is currently in the trusted kernel 110 and receives a switch initiation request to switch to the untrusted kernel 120, the value of T_WSSR.NTSC can be set to indicate the corresponding switching method; similarly, when the processor is currently in the untrusted kernel 120 and receives a switch initiation request to switch to the trusted kernel 110, the value of T_WSSR.TSC can be set to indicate the corresponding switching method.

[0093] Then, in step S310, the T bit in the program status register PSR is set to indicate the target core of the core switch to perform the core switch.

[0094] Optionally, in step S310, after the core is switched, a processing program corresponding to the switch initiation request may be executed in the new core to complete a corresponding task.

[0095] According to an embodiment of the present invention, the method 300 further includes step S320. In step S320, a switch return request is received and processed. As described above, the switch return request corresponds to the switch initiation request, and when the processing program corresponding to the switch initiation request is executed and the processor executes the return instruction ret, if the values ​​of the T bit and the SP bit in the program status register PSR are inconsistent at this time, a switch return request is issued to switch the kernel back to the previous kernel state.

[0096] In step S320, the target core of the switch return request is determined according to the value of the start core identification bit PSR.SP, the switch initiation request corresponding to the switch return request is determined according to the switch state identification bit in the switch state register T_WSSR, and the value of the current core identification bit PSR.T is set to indicate the determined target core to perform core switching, so as to return to the core state when the switch initiation request is issued. The judgment logic for the switch return request in step S320 is as described above with reference to Table 1, and will not be repeated here.

[0097] According to an embodiment of the present invention, the core switching method includes executing the switching instruction wsc to trigger the core switching. In step S310, when the switching initiation request is initiated by executing the switching instruction wsc, after the core switching, the instructions in the program corresponding to the cross-core task specified in the wsc instruction are executed.

[0098] Similarly, the core switching mode includes triggering the processing of an interrupt, then in step S310, after the core switching, the instructions in the interrupt processing program corresponding to the interrupt are executed. And when the execution of these programs is completed, the return instruction ret is executed to issue a switch return request, so as to perform the core switching and return to the core state before the switch initiation request is issued.

[0099] Reference below Figure 1 The structure of the processor 100 describes the specific processing of the switching initiation request in step S310.

[0100] Implementation 7:

[0101] When the processor 200 is in the untrusted kernel 120, a kernel switching request (a switch initiation request to the trusted kernel) is issued due to the execution of the switching instruction wsc. At this time, in step S310, the request is received, the field status information of the untrusted kernel 120 is stored in the user stack of the untrusted kernel (especially in the super user stack of the untrusted kernel), the trusted kernel switching state identification bit T_WSSR.TSC in the switching state register is set to 1 to indicate that the trusted kernel is switched by executing the wsc instruction, and the starting kernel identification bit PSR.SP in the program status register PSR is set to 0 to indicate that the starting kernel is an untrusted kernel. Subsequently, the current kernel identification bit PSR.T in the program status register PSR is set to 1 to indicate that the target kernel is a trusted kernel so as to switch to the trusted kernel 110. Subsequently, the instructions in the program corresponding to the cross-kernel task indicated by the switching instruction wsc are executed. According to an embodiment, the entry address of the program corresponding to the cross-kernel call task is obtained from the trusted call program base address register T_EBR 118 so as to start executing instructions from the address, that is, executing the program instructions corresponding to the cross-kernel call task.

[0102] Implementation 8:

[0103] When the processor 200 is in the trusted kernel 110, a kernel switching request (a switch initiation request to the untrusted kernel) is issued due to the execution of the switch instruction wsc. At this time, in step S310, the request is received, the field status information of the trusted kernel 110 is stored in the user stack of the trusted kernel (especially in the super user stack of the trusted kernel), the untrusted kernel switch state identification bit T_WSSR.NTSC in the switch state register is set to 1 to indicate that the switch is made to the untrusted kernel by executing the wsc instruction, and the starting kernel identification bit PSR.SP in the program status register PSR is set to 1 to indicate that the starting kernel is a trusted kernel. Subsequently, the current kernel identification bit PSR.T in the program status register PSR is set to 0 to indicate that the target kernel is an untrusted kernel so as to switch to the untrusted kernel 120. Subsequently, the instructions in the program corresponding to the cross-kernel task indicated by the switch instruction wsc are executed. According to an embodiment, the entry address of the program corresponding to the cross-kernel call task can be obtained from the untrusted call program base address register NT_EBR 128 so as to start executing instructions from the address, that is, executing the program instructions corresponding to the cross-kernel call task.

[0104] Implementation 9:

[0105] When the processor 200 is in the non-trusted kernel 120, a kernel switching request (switching initiation request to the trusted kernel) is issued due to the generation of a trusted interrupt. At this point, in step S310, the request is received, and the field status information of the non-trusted kernel 120 is stored in the user stack of the non-trusted kernel (particularly in the super user stack of the non-trusted kernel). The current kernel identification bit PSR.T in the program status register PSR is set to 1, to indicate that the target kernel is a trusted kernel so as to switch to the trusted kernel 110. Subsequently, in the trusted kernel 110, the value of the trusted kernel program status register T_PSR is backed up, the starting kernel identification bit PSR.SP in the program status register PSR is set to 0 to indicate that the starting kernel is the non-trusted kernel 120, and the trusted kernel switching state identification bit T_WSSR.TSC in the switching state register is set to 0, to indicate that the mode triggered by the trusted interrupt is switched to the trusted kernel. The instruction in the interrupt handler corresponding to the trusted interrupt is then executed. According to one embodiment, the entry address of the interrupt processing program corresponding to the trusted interrupt is obtained from the trusted exception program base address register T_VBR117, and instructions are executed starting from the address, that is, instructions in the corresponding interrupt processing program are executed.

[0106] Implementation 10:

[0107] When the processor 200 is in the trusted kernel 110, a kernel switching request (a switch initiation request to the untrusted kernel) is issued due to the generation of an untrusted interrupt. At this point, in step S310, the request is received, and the field status information of the trusted kernel 110 is stored in the user stack of the trusted kernel (particularly in the super user stack of the trusted kernel). The switching control unit 210 can also store the contents of each general register in the trusted kernel in the user stack of the trusted kernel, and clear the contents of these general registers. Subsequently, in step S310, the untrusted kernel switching state identification bit T_WSSR.NTSC in the switching state register is set to 0 to indicate that the field information push has been completed under the trusted kernel, and to switch to the untrusted kernel by the mode of triggering the untrusted interrupt. Then, in step S310, the current kernel identification bit PSR.T in the program status register PSR is set to 0 to indicate that the target kernel is an untrusted kernel so as to switch to the untrusted kernel 120. Subsequently, in the untrusted kernel 120, the value of the untrusted kernel program status register NT_PSR is backed up, and the starting kernel identification bit PSR.SP in the program status register PSR is set to 1 to indicate that the starting kernel is the trusted kernel 110. Then, the instructions in the interrupt handling program corresponding to the untrusted interrupt are executed. According to one embodiment, the entry address of the interrupt handling program corresponding to the untrusted interrupt is obtained from the untrusted exception program base address register NT_VBR 127, so as to execute instructions starting from the address, that is, to execute the instructions in the corresponding interrupt handling program.

[0108] Reference below Figure 1 The structure of the processor 100 describes the specific processing of the switching return request in step S320.

[0109] Implementation 11:

[0110] The processor 200 is in the trusted core 110. When executing the return instruction ret, if the values ​​of the T bit and the SP bit in the PSR are inconsistent, that is, the value of the T bit is 1 and the value of the SP bit is 0, a core switching request (i.e., a switch return request to the untrusted core) will be issued. At this time, in step S320, the request is received and the next step of processing is performed according to the value of T_WSSR.TSC.

[0111] If the value of T_WSSR.TSC is 1 at this time, it means that the processor 200 enters the current trusted kernel 110 due to executing the wsc instruction. Therefore, the value of PSR.T is set to 0 to indicate that the untrusted kernel is switched to the untrusted kernel. After switching to the untrusted kernel 120, the field state information of the untrusted kernel 120 is restored from the user stack of the untrusted kernel (especially the super user stack of the untrusted kernel) to continue to execute instructions.

[0112] If the value of T_WSSR.TSC is 0 at this time, it means that the processor 200 enters the current trusted kernel 110 because of processing the trusted interrupt. Therefore, the value in the previously saved trusted kernel program status register T_PSR is first restored, and the value of PSR.T is set to 0 to instruct the untrusted kernel to switch to the untrusted kernel 120. After switching to the untrusted kernel 120, the field status information of the untrusted kernel 120 is restored from the user stack of the untrusted kernel (especially the super user stack of the untrusted kernel) to continue to execute instructions.

[0113] Implementation 12:

[0114] The processor 200 is in the untrusted core 120. When executing the return instruction ret, if the values ​​of the T bit and the SP bit in the PSR are inconsistent, that is, the value of the T bit is 0 and the value of the SP bit is 1, a core switch request (that is, a switch return request to the trusted core) will be issued.

[0115] In step S310, the request is received and the next step of processing is performed according to the value of T_WSSR.NTSC.

[0116] If the value of T_WSSR.NTSC is 1 at this time, it means that the processor 200 enters the current non-trusted kernel 120 due to the execution of the wsc instruction. Therefore, the value of PSR.T is set to 1 to instruct the trusted kernel to switch to the trusted kernel. After switching to the trusted kernel 110, the field status information of the trusted kernel 110 is restored from the user stack of the trusted kernel (especially the supervisor stack of the trusted kernel) to continue to execute instructions.

[0117] If the value of T_WSSR.NTSC is 0 at this time, it means that the processor 200 enters the current untrusted kernel 120 because of processing the untrusted interrupt. Therefore, the value in the previously saved untrusted kernel program status register NT_PSR is first restored, and the value of PSR.T is set to 1 to instruct the trusted kernel to switch to the trusted kernel 110. After switching to the trusted kernel 110, the field status information of the trusted kernel 110 is restored from the user stack of the trusted kernel (especially the super user stack of the trusted kernel) to continue to execute instructions.

[0118] Figure 4 FIG. 4 is a schematic diagram of a system on chip (SoC) 400 according to an embodiment of the present invention. The system on chip 400 includes a reference Figure 1The processor 100, various interrupt sources 420, storage space 430 and coprocessor 440, etc. The system on chip can be integrated on a circuit board and constitute a relatively complete processing system. The interrupt source 420 is, for example, various peripheral interfaces, which receive external inputs and output the processed outputs of the processor 100. The storage space 430 can provide an external storage space for the processor 100, which is used to store the code to be executed by the processor 100 and the various output data generated. The coprocessor 440 is a special processor used to perform special processing tasks, such as image operations.

[0119] The system on chip (SoC) according to the present invention can be used in various smart devices to implement corresponding functions in the smart devices. Such smart devices include but are not limited to vehicle-mounted devices, smart speakers, smart display devices, IoT devices, mobile terminals, and personal digital terminals, etc. All systems that can incorporate the accelerated computing system and / or other execution logic disclosed in this specification are within the scope of protection of the present invention.

[0120] It should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the following intention: that the claimed invention requires more features than those explicitly recited in each claim. More specifically, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present invention.

[0121] Those skilled in the art will appreciate that the modules or units or components of the devices in the examples disclosed herein may be arranged in the devices described in the embodiment, or alternatively may be located in one or more devices different from the devices in the examples. The modules in the foregoing examples may be combined into one module or may be divided into multiple submodules.

[0122] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition they may be divided into a plurality of submodules or subunits or subcomponents. Except that at least some of such features and / or processes or units are mutually exclusive, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0123] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, in the claims below, any one of the claimed embodiments may be used in any combination.

[0124] In addition, some of the embodiments are described herein as methods or combinations of method elements that can be implemented by a processor of a computer system or by other devices that perform the functions. Therefore, a processor with necessary instructions for implementing the method or method elements forms a device for implementing the method or method elements. In addition, the elements described herein of the device embodiments are examples of devices for implementing the functions performed by the elements for the purpose of implementing the invention.

[0125] As used herein, unless otherwise specified, the use of ordinal numbers "first," "second," "third," etc. to describe common objects merely indicates that different instances of similar objects are involved, and is not intended to imply that the objects so described must have a given order in time, space, order, or in any other manner.

[0126] Although the present invention has been described according to a limited number of embodiments, it will be apparent to those skilled in the art, with the benefit of the above description, that other embodiments may be envisioned within the scope of the invention thus described. In addition, it should be noted that the language used in this specification is selected primarily for readability and teaching purposes, rather than for explaining or defining the subject matter of the present invention. Therefore, many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the appended claims. The disclosure of the present invention is illustrative, not restrictive, with respect to the scope of the present invention, which is defined by the appended claims.

Claims

1. A processor having a trusted core and an untrusted core, the processor comprising: a program status register, adapted to store a current kernel identification bit and a starting kernel identification bit, wherein the current kernel identification bit indicates whether the current kernel of the processor is a trusted kernel or an untrusted kernel, and the starting kernel identification bit indicates whether the kernel of the processor before switching to the current kernel is a trusted kernel or an untrusted kernel; A switching state register, adapted to store a switching state flag bit, wherein the switching state flag bit indicates a core switching mode; as well as A switching control unit, adapted to receive a kernel switching request, and process the kernel switching request according to the current kernel identification bit, the starting kernel identification bit and the switching state identification bit to perform kernel switching; The program base address register is suitable for storing the address information of the cross-core calling program. The address information is stored in the form of an entry vector table of the cross-core task calling program. The cross-core calling program corresponding to the trusted task or untrusted task specified by the instruction can find the corresponding entry address in the program base address register, thereby facilitating jumping to the entry address to execute the instructions in the cross-core calling program.

2. The processor according to claim 1, wherein the core switching request comprises a switching initiation request and a switching return request corresponding to the switching initiation request, and the switching initiation request has a corresponding core switching mode, and The switching control unit is adapted to, upon receiving the switching initiation request, set the starting core identification bit according to the current core of the processor, set the switching state identification bit according to the core switching mode corresponding to the switching initiation request, and set the current core identification bit according to the target core of the switching initiation request to perform core switching; and The switching control unit is also suitable for determining the target kernel of the switching return request according to the value of the starting kernel identification bit when receiving the switching return request, determining the switching initiation request corresponding to the switching return request according to the switching state identification bit, and setting the current kernel identification bit according to the determined target kernel to perform kernel switching.

3. The processor according to claim 2, wherein the core switching mode includes a mode corresponding to a switching instruction and a mode corresponding to an interrupt, and the processor further comprises: an instruction execution unit, coupled to the handover control unit, adapted to execute the handover instruction to issue a handover initiation request corresponding to the handover instruction to the handover control unit, and to execute a return instruction to issue a handover return request to the handover control unit; as well as The interrupt initiation unit is coupled to the switching control unit and is adapted to generate an interrupt to send a switching initiation request corresponding to the interrupt to the switching control unit.

4. The processor of claim 3, further comprising: A field maintenance unit, coupled to the switching control unit, adapted to store field status information of a current core of the processor into a stack, and adapted to restore the field status information of the core from the stack; as well as The switching control unit is further adapted to instruct the field maintenance unit to store and / or restore the field status information of the kernel when processing the kernel switching request.

5. The processor of claim 4, wherein the program status register comprises a trusted kernel program status register and an untrusted kernel program status register, and when the processor is in a trusted kernel, the trusted kernel program status register is used as the program status register, and when the processor is in an untrusted kernel, the untrusted kernel program status register is used as the program status register; and The switching state identification bit includes a trusted kernel switching state identification bit and an untrusted kernel switching state identification bit, wherein the trusted kernel switching state identification bit indicates a kernel switching mode from an untrusted kernel to a trusted kernel, and the untrusted kernel switching state identification bit indicates a kernel switching mode from a trusted kernel to an untrusted kernel.

6. The processor according to claim 5, wherein the switching control unit is adapted to, when the processor is in a non-trusted core and receives a switching initiation request issued by the instruction execution unit to execute the switching instruction: Instructing the field maintenance unit to store the field status information of the untrusted kernel in the stack of the untrusted kernel; Setting the trusted kernel switching state identification bit to indicate a kernel switching mode corresponding to the switching instruction, setting the starting kernel identification bit to indicate an untrusted kernel, and setting the current kernel identification bit to indicate a trusted kernel so as to switch to a trusted kernel; as well as The instruction execution unit is instructed to execute an instruction in a program corresponding to the switching instruction.

7. The processor according to claim 5 or 6, wherein the switching control unit is adapted to, when the processor is in a trusted kernel and receives a switching initiation request issued by the instruction execution unit to execute the switching instruction: Instructing the field maintenance unit to store the field status information of the trusted kernel into the stack of the trusted kernel; The non-trusted kernel switching state identification bit is set to indicate the kernel switching mode corresponding to the switching instruction, the starting kernel identification bit is set to indicate the trusted kernel, and the current kernel identification bit is set to indicate the non-trusted kernel so as to switch to the non-trusted kernel; as well as The instruction execution unit is instructed to execute an instruction in a program corresponding to the switching instruction.

8. The processor according to claim 5, wherein the switching control unit is adapted to, when the processor is in a non-trusted core and receives a switching initiation request issued by the interrupt initiation unit due to a trusted interrupt: Instructing the field maintenance unit to store the field status information of the untrusted kernel in the stack of the untrusted kernel; Setting the current kernel identification bit to indicate a trusted kernel so as to switch to the trusted kernel; Backing up the value in the trusted kernel program status register; Setting the starting kernel identification bit to indicate an untrusted kernel; Setting the trusted kernel switching state flag bit to indicate a kernel switching mode corresponding to the trusted interrupt; as well as The instruction execution unit is instructed to execute instructions in a program suitable for handling the trusted interrupt.

9. The processor according to claim 8, wherein the switching control unit is adapted to, when the processor is in a trusted core and receives a switching initiation request issued by the interrupt initiation unit due to the generation of an untrusted interrupt: Instructing the field maintenance unit to store the field status information of the trusted kernel into the stack of the trusted kernel; Setting the untrusted kernel switching state flag bit to indicate a kernel switching mode corresponding to the untrusted interrupt; Setting the current kernel identification bit to indicate an untrusted kernel so as to switch to the untrusted kernel; Backing up the value in the untrusted kernel program status register, and setting the starting kernel identification bit to indicate a trusted kernel; as well as The instruction execution unit is instructed to execute instructions in a program suitable for handling the non-trusted interrupt.

10. The processor according to claim 9, wherein when the instruction execution unit executes the return instruction, a switch return request is issued when the values ​​of the current core identification bit and the starting core identification bit are inconsistent.

11. The processor according to claim 10, wherein the switching control unit is adapted to, when the processor is in the trusted core and receives a switching return request issued by the instruction execution unit executing a return instruction: If the value of the trusted kernel switching identification bit indicates a kernel switching mode corresponding to the switching instruction, the kernel identification bit is set to indicate an untrusted kernel so as to switch to the untrusted kernel, and the field maintenance unit is instructed to restore the field status information of the untrusted kernel from the stack of the untrusted kernel so that the instruction execution unit continues to execute instructions; and If the value of the trusted kernel switch identification bit indicates a kernel switch mode corresponding to a trusted interrupt, the value in the saved trusted kernel program status register is restored, the kernel identification bit is set to indicate an untrusted kernel in order to switch to an untrusted kernel, and the field maintenance unit is instructed to restore the field status information of the untrusted kernel from the stack of the untrusted kernel so that the instruction execution unit can continue to execute instructions.

12. The processor according to claim 10, wherein the switching control unit is adapted to, when the processor is in a non-trusted core and receives a switching return request issued by the instruction execution unit executing a return instruction: If the value of the untrusted kernel switching identification bit indicates a kernel switching mode corresponding to the switching instruction, setting the kernel identification bit to indicate a trusted kernel so as to switch to a trusted kernel, and instructing the field maintenance unit to restore the field status information of the trusted kernel from the stack of the trusted kernel so that the instruction execution unit continues to execute instructions; and If the value of the non-trusted kernel switch identification bit indicates a kernel switch mode corresponding to a non-trusted interrupt, the value in the saved non-trusted kernel program status register is restored, the kernel identification bit is set to indicate a trusted kernel so as to switch to a trusted kernel, and the field maintenance unit is instructed to restore the field status information of the trusted kernel from the stack of the trusted kernel so that the instruction execution unit can continue to execute instructions.

13. The processor of claim 5, wherein the program base registers include a trusted caller base register and an untrusted caller base register; The trusted caller base address register is adapted to store address information of a cross-kernel caller in the trusted kernel; The untrusted caller base address register is suitable for storing address information of a cross-kernel caller in the untrusted kernel; as well as The switching control unit is adapted to obtain the address of the cross-core caller corresponding to the switching instruction from the trusted caller base address register or the untrusted caller base address register when processing a kernel switching request triggered by the switching instruction, so as to instruct the instruction execution unit to execute instructions starting from the obtained address.

14. The processor of claim 5, further comprising A trusted exception program base address register, suitable for storing address information of an exception handling program in a trusted kernel; An untrusted exception program base address processor, adapted to store address information of an exception handling program in an untrusted kernel; as well as The switching control unit is adapted to obtain the address of the exception handling program corresponding to the interrupt from the trusted exception program base address register or the untrusted exception program base address register when processing a core switching request triggered by an interrupt, so as to instruct the instruction execution unit to execute instructions starting from the obtained address.

15. The processor of claim 5, wherein the program status register is further adapted to store a supervisor status bit, the supervisor status bit indicating whether the processor is currently in a normal user mode or a supervisor mode; The field maintenance unit is adapted to store field status information of the core in which the processor is currently located in a supervisor stack; and The switching control unit is adapted to set the supervisor state bit to indicate supervisor mode after performing a core switch when processing a switching initiation request.

16. A method for processing a kernel switching request, suitable for execution in a processor having a trusted kernel and an untrusted kernel, the processor comprising a program status register, a switching status register, and a program base address register, the kernel switching request comprising a switching initiation request and a switching return request corresponding to the switching initiation request, and the switching initiation request has a corresponding kernel switching mode, the method comprising the steps of: receiving a switch initiation request and processing it, so as to set a starting kernel identification bit in a program status register according to a kernel in which the processor is currently located, setting a switch status identification bit in a switch status register according to a kernel switch mode corresponding to the switch initiation request, and setting a current kernel identification bit in the program status register according to a target kernel of the switch initiation request to perform kernel switching; Also includes: The entry address of the program corresponding to the cross-core calling task is obtained from the program base address register, so as to execute the program instructions corresponding to the cross-core calling task starting from the address.

17. The method of claim 16, further comprising the steps of: A switch return request is received and processed so as to determine a target kernel of the switch return request according to the value of the starting kernel identification bit, determine a switch initiation request corresponding to the switch return request according to the switch state identification bit, and set the current kernel identification bit according to the determined target kernel to perform kernel switching.

18. The method according to claim 16 or 17, wherein the core switching mode includes a mode corresponding to a switching instruction and a mode corresponding to an interrupt; The switching initiation request includes a switching initiation request issued by the processor when executing the switching instruction and a switching initiation request issued by the processor when generating an interrupt; and The switch return request includes a switch return request issued by the processor when executing a return instruction.

19. The method of claim 18, wherein the program status register comprises a trusted kernel program status register and an untrusted kernel program status register, and when the processor is in a trusted kernel, the trusted kernel program status register is used as the program status register, and when the processor is in an untrusted kernel, the untrusted kernel program status register is used as the program status register; and The switching state identification bit includes a trusted kernel switching state identification bit and an untrusted kernel switching state identification bit, wherein the trusted kernel switching state identification bit indicates a kernel switching mode from an untrusted kernel to a trusted kernel, and the untrusted kernel switching state identification bit indicates a kernel switching mode from a trusted kernel to an untrusted kernel.

20. The method of claim 19, wherein when the processor is in a non-trusted core and the switch initiation request is issued for executing the switch instruction, the step of processing the switch initiation request comprises: Before performing kernel switching, storing the field status information of the untrusted kernel in the stack of the untrusted kernel; Setting the trusted kernel switching state identification bit to indicate a kernel switching mode corresponding to the switching instruction, setting the starting kernel identification bit to indicate an untrusted kernel, and setting the current kernel identification bit to indicate a trusted kernel so as to switch to a trusted kernel; as well as After switching to the trusted kernel, an instruction in the program corresponding to the switching instruction is executed.

21. The method of claim 19, wherein when the processor is in a trusted kernel and the switch initiation request is issued for executing the switch instruction, the step of processing the switch initiation request comprises: Before performing kernel switching, storing the field status information of the trusted kernel in the stack of the trusted kernel; The non-trusted kernel switching state identification bit is set to indicate the kernel switching mode corresponding to the switching instruction, the starting kernel identification bit is set to indicate the trusted kernel, and the current kernel identification bit is set to indicate the non-trusted kernel so as to switch to the non-trusted kernel; as well as After switching to the untrusted kernel, an instruction in the program corresponding to the switching instruction is executed.

22. The method of claim 19, wherein when the processor is in a non-trusted core and the switch initiation request is issued to generate a trusted interrupt, the step of processing the switch initiation request comprises: Before performing kernel switching, storing the field status information of the untrusted kernel in the stack of the untrusted kernel; Setting the current kernel identification bit to indicate a trusted kernel so as to switch to the trusted kernel; Backing up the value in the trusted kernel program status register; Setting the starting kernel identification bit to indicate an untrusted kernel; Setting the trusted kernel switching state flag bit to indicate a kernel switching mode corresponding to the trusted interrupt; as well as Instructions in a program that handles the trusted interrupt are executed.

23. The method of claim 22, wherein when the processor is in a trusted core and the switch initiation request is issued to generate an untrusted interrupt, the step of processing the switch initiation request comprises: Before performing kernel switching, storing the field status information of the trusted kernel in the stack of the trusted kernel; Setting the untrusted kernel switching state flag bit to indicate a kernel switching mode corresponding to the untrusted interrupt; Setting the current kernel identification bit to indicate an untrusted kernel so as to switch to the untrusted kernel; Backing up the value in the untrusted kernel program status register, and setting the starting kernel identification bit to indicate a trusted kernel; as well as Instructions in a program that handles the untrusted interrupt are executed.

24. The method of claim 23, wherein the switch return request is suitable for being issued if the values ​​of the current core identification bit and the starting core identification bit are inconsistent when the processor executes the return instruction.

25. The method of claim 24, wherein when the processor is in a trusted kernel, the step of processing the switch back request comprises: If the value of the trusted kernel switching identification bit indicates a kernel switching mode corresponding to the switching instruction, the kernel identification bit is set to indicate an untrusted kernel so as to switch to the untrusted kernel, and the field state information of the untrusted kernel is restored from the stack of the untrusted kernel so as to continue to execute the instruction; as well as If the value of the trusted kernel switch identification bit indicates a kernel switch mode corresponding to the trusted interrupt, the value in the saved trusted kernel program status register is restored, the kernel identification bit is set to indicate an untrusted kernel so as to switch to an untrusted kernel, and the field status information of the untrusted kernel is restored from the stack of the untrusted kernel so as to continue executing instructions.

26. The method of claim 24, wherein when the processor is in a non-trusted kernel, the step of processing the switch back request comprises: If the value of the non-trusted kernel switching identification bit indicates a kernel switching mode corresponding to the switching instruction, the kernel identification bit is set to indicate a trusted kernel so as to switch to a trusted kernel, and the field state information of the trusted kernel is restored from the stack of the trusted kernel so as to continue to execute the instruction; as well as If the value of the untrusted kernel switch identification bit indicates a kernel switch mode corresponding to the untrusted interrupt, the value in the saved untrusted kernel program status register is restored, the kernel identification bit is set to indicate the trusted kernel so as to switch to the trusted kernel, and the field status information of the trusted kernel is restored from the stack of the trusted kernel so as to continue to execute instructions.

27. The method of any one of claims 20-25, wherein the processor further comprises: A trusted caller base address register, adapted to store address information of a cross-kernel caller in a trusted kernel; An untrusted caller base address register, suitable for storing address information of a cross-kernel caller in an untrusted kernel; as well as The step of executing the instruction in the program corresponding to the switching instruction includes: obtaining the address of the cross-core calling program corresponding to the switching instruction from the trusted calling program base address register or the untrusted calling program base address register, so as to start executing instructions from the obtained address.

28. The method of any one of claims 20-26, wherein the processor further comprises A trusted exception program base address register, suitable for storing address information of an exception handling program in a trusted kernel; An untrusted exception program base address processor, adapted to store address information of an exception handling program in an untrusted kernel; as well as The step of executing the instructions in the program for handling the interrupt includes: acquiring the address of the exception handling program corresponding to the interrupt from the trusted exception program base address register or the untrusted exception program base address register, so as to start executing instructions from the acquired address.

29. The method of claim 16, wherein the program status register is further adapted to store a supervisor status bit, the supervisor status bit indicating whether the processor is currently in a normal user mode or a supervisor mode; Storing the local state information of the core in which the processor is currently located in the user stack includes storing the local state information of the core in which the processor is currently located in the user stack; and The step of processing the switching initiation request comprises: After a core switch is performed, the supervisor state bit is set to indicate supervisor mode.

30. A system on a chip, comprising: A processor as claimed in any one of claims 1 to 15.

31. An intelligent device comprising the system on chip as claimed in claim 30.

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