A chip testability architecture

Abstract

The present invention discloses a testability architecture of a chip, and relates to the technical field of integrated circuits. The testability architecture provided by the present invention includes a test logic module and a functional logic module, wherein the test logic module includes an independent test unit and a mixed test unit, wherein the independent test unit and the functional logic module are separated from each other; the testability architecture has a functional mode and a test mode, wherein in the functional mode, the power supply of the independent test unit is disconnected; in the test mode, the power supply of the independent test unit, the mixed test unit, and the functional logic module is in an on state. Based on the use of clock gating to reduce the dynamic power consumption of a testable design chip, the present invention uses a multi-power domain method to power off the test logic module, thereby achieving the purpose of significantly reducing static power consumption, so that the overall power consumption of the chip during operation is lower.

Description

[Technical field]

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a chip testability architecture. [Background technology]

[0002] Nowadays, with the increase in the scale and complexity of integrated circuits and the decrease in the relative number of pins in chips, the controllability and observability of circuits have been greatly reduced. Traditional testing methods are difficult to fully and effectively verify the correctness of complex integrated circuit design and manufacturing. The design of testability methods provides a solution to this problem. By appropriately adding some test-specific circuits, the controllability and observability of circuits can be improved, thereby reducing the difficulty and complexity of circuit testing, improving the efficiency of circuit testing, and reducing costs. However, these integrated circuits specifically used for testing also generate a lot of power consumption when the chip is working normally. As the scale and speed of digital circuit chips continue to increase, the power consumption of chips is also increasing. In many applications, power consumption has become the primary consideration in chip design. Most of the existing testable designs use clock gating structures to eliminate the dynamic power consumption of the test circuit, but they cannot eliminate the leakage current power consumption caused by leakage current, that is, static power consumption (Static Power). Although the operating voltage of chips is currently at a relatively low level and the leakage current of a single MOS tube is very small, as the scale of chip transistors increases, some of which can reach hundreds of millions or even billions, the scale of circuits introduced by testability design also increases, and leakage current power consumption becomes an important component of power consumption in testable chips. How to reduce or even eliminate the leakage current power consumption of testable integrated circuits is an unsolved problem that cannot be ignored at present. [Summary of the invention]

[0003] To solve the aforementioned problems, the present invention provides a chip testability architecture. Based on the use of clock gating to reduce the dynamic power consumption of the testable design chip, the test logic module is powered off through a multi-power domain method, thereby achieving the purpose of significantly reducing static power consumption, thereby lowering the overall power consumption of the chip during operation.

[0004] In order to achieve the above object, the present invention adopts the following technical solution:

[0005] A chip testability architecture, the testability architecture comprising a test logic module and a functional logic module, the test logic module comprising an independent test unit and a mixed test unit, the mixed test unit and the functional logic module are mixed with each other, and the independent test unit and the functional logic module are separated from each other;

[0006] The testability architecture has a functional mode and a test mode. In the functional mode, the power supply of the independent test unit is disconnected, and the power supply of the mixed test unit and the functional logic module is in the on state; in the test mode, the power supply of the independent test unit, the mixed test unit and the functional logic module is in the on state.

[0007] Optionally, the testability architecture has a test power domain and a functional power domain, the independent test unit is powered by VDD_test in the test power domain, and the mixed test unit and the functional logic module are powered by VDD_func in the functional power domain.

[0008] Optionally, the testability architecture also includes a power switch controller unit and a power switch cells unit, the power switch controller unit is signal-connected to the power switch cells unit, and in a functional mode, the power switch controller unit sends a shutdown control signal to the power switch cells unit, and the power switch cells unit disconnects the power supply between VDD_test and the independent test unit.

[0009] Optionally, the power switch controller unit and the power switch cells unit are powered by VDD_func in the functional power domain.

[0010] Optionally, the power switch cells have an input end and an output end, the input end is connected to VDD_func, and the output end is connected to VDD_test.

[0011] Optionally, the power switch cells unit has a plurality of switch cells, and the plurality of switch cells are connected end to end around the independent test unit to form a closed loop, or the plurality of switch cells are evenly distributed in a matrix around the independent test unit.

[0012] Optionally, the functional mode and the test mode of the testability architecture are determined according to a test_mode signal;

[0013] The default value of the test_mode signal is 0, the testability architecture is in functional mode, and the power switch controller unit sends a shutdown control signal to the power switch cells unit after receiving the test_mode signal;

[0014] The test_mode signal is set to 1, the testability architecture is in test mode, and the power switch controller unit sends an open control signal to the power switch cells unit after receiving the test_mode signal, and the power switch cells unit restores the power supply between VDD_test and the independent test unit.

[0015] Optionally, the test_mode signal is input from an I / O port outside the chip or generated inside the chip.

[0016] Optionally, the testability architecture further includes isolation cells;

[0017] In the functional mode, the isolation cells unit is in an enabled state after receiving a test_mode signal of 0, and the signal output by the independent test cell is locked to a fixed value to isolate the functional logic module;

[0018] In the test mode, the isolation cells are in a disabled state after receiving a test_mode signal of 1, and the isolated test cells are signal-connected to the functional logic module.

[0019] Optionally, the isolation cells are powered by VDD_func in the functional power domain.

[0020] The present invention has the following beneficial effects:

[0021] In the prior art, most of the chips that can be designed for testing use a clock gating structure to reduce the dynamic power consumption of the circuit, but the leakage current cannot be eliminated, and there is still a large static power consumption. The technical solution provided by the present application, based on the prior art, divides as many test logics as possible into independent test logic modules through the division of multiple power domains, and distributes the divided parts to different voltage domains for power supply, so that the independent test logic modules can be completely powered off when the chip is working, so as to achieve the purpose of significantly reducing static power consumption, making the overall power consumption of the circuit lower. At the same time, when the chip needs to be tested, the test power domain can be powered normally, and the independent test logic module can work normally, which will not cause adverse effects on the normal operation of the test mode.

[0022] These features and advantages of the present invention will be disclosed in detail in the following specific embodiments and drawings. The best embodiments or means of the present invention will be described in detail in conjunction with the drawings, but they are not intended to limit the technical solutions of the present invention. In addition, there are multiple features, elements, and components that appear in each of the following texts and drawings, and different symbols or numbers are marked for convenience, but they all represent components with the same or similar structures or functions.

Brief Description of the Drawings

[0023] The present invention will be further described below in conjunction with the accompanying drawings:

[0024] Figure 1 Schematic diagram of the working process of an embodiment of the present invention. [Specific implementation method]

[0025] The technical solutions of the embodiments of the present invention are explained and described below in conjunction with the drawings of the embodiments of the present invention, but the following embodiments are only preferred embodiments of the present invention, not all. Based on the embodiments in the implementation mode, other embodiments obtained by those skilled in the art without creative work are all within the protection scope of the present invention.

[0026] References in this specification to "one embodiment" or "an example" or "an example" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment itself may be included in at least one embodiment of the present patent disclosure. The appearance of the phrase "in one embodiment" in various places in the specification does not necessarily refer to the same embodiment.

[0027] Example:

[0028] This embodiment provides a chip testability architecture.

[0029] In terms of logic modules, the testability architecture provided in this embodiment includes a test logic module, a functional logic module, a power switch controller unit, a power switch cells unit, and an isolation cells unit. The test logic module includes an independent test unit and a mixed test unit. The specific circuits of the aforementioned logic units and logic modules belong to the prior art known to those skilled in the art and will not be repeated here. The mixed test unit and the functional logic module are mixed with each other, and the independent test unit and the functional logic module are separated from each other. Since there are overlapping parts between the test logic module and the functional logic module in the prior art, it is necessary to divide the test logic module into independent test units and mixed test units as much as possible without affecting the functional logic module, so that the independent test unit can use a separate power domain, thereby realizing independent control of its power supply to minimize the power consumption of the chip. The power switch controller unit is connected to the power switch cells unit signal. The power switch cells unit has a number of switch cells. The unit is implemented by a CMOS circuit. Since the on-current of a MOS is very small, when the logic controlled by it works normally, the required current is relatively large, so a large number of cells are required to work together to bear this current. Therefore, in this embodiment, a plurality of switch cells are connected end to end around the independent test unit to form a closed loop. In other embodiments, a plurality of switch cells may also be evenly distributed in a matrix around the independent test unit, which is not limited here. There is a signal transmission relationship between the functional logic module and the independent test unit. When the power of the independent test unit is turned off, its output signal may be unstable, that is, an unpredictable value, which affects the circuit function. Therefore, isolation cells are used to isolate the output signal of the independent test unit with the power turned off from the functional logic module.

[0030] In terms of power supply, the testability architecture provided in this embodiment has a test power domain and a functional power domain. The independent test unit is powered by VDD_test in the test power domain; the mixed test unit, functional logic module, powerswitch controller unit, power switch cells unit and isolation cells unit are all powered by VDD_func in the functional power domain. The power switch cells unit has an input end and an output end, the input end is connected to VDD_func, and the output end is connected to VDD_test. Without changing the functional logic, the independent test unit is separated to facilitate the power supply of a separate power domain to it, thereby achieving the purpose of individually shutting down this part of the test logic.

[0031] like Figure 1 As shown, the testability architecture provided in this embodiment has a functional mode and a test mode. The functional mode and the test mode are determined according to a test_mode signal. The test_mode signal can be input from the I / O port outside the chip, or generated inside the chip, which is not limited here.

[0032] The default value of the test_mode signal is 0. At this time, the testability architecture is in functional mode. After the power switch controller unit receives the test_mode signal of 0, it sends a shutdown control signal to the power switch cells unit. After receiving the shutdown control signal, the power switch cells unit disconnects the power supply between VDD_test and the independent test unit, so that the power supply of the independent test unit is cut off, while the hybrid test unit and the functional logic module are powered on, so as to realize the independent control of the power supply of this part of the logic in different working modes. The logic module inside the functional power domain works normally, while the independent test unit is completely powered off and will not generate any power consumption. At this time, the power consumption of the chip only comes from the logic module in the functional power domain. At the same time, the isolation cells unit is in an enabled state after receiving the test_mode signal of 0, and the signal output by the independent test cell is locked to a fixed value to isolate the functional logic module and ensure that its output will not interfere with the normal operation of the functional logic module;

[0033] When the testability architecture needs to be tested, the test_mode signal is set to 1. At this time, the testability architecture is in test mode. After the power switch controller unit receives the test_mode signal of 1, it sends an open control signal to the power switch cells unit. After receiving the open control signal, the power switch cells unit restores the power supply between VDD_test and the independent test unit. The power supply of the independent test unit, the mixed test unit and the functional logic module is in the on state, and all logic modules are working normally. At the same time, the isolation cells unit is in a disabled state after receiving the test_mode signal of 1. The independent test unit is connected to the functional logic module signal for normal data transmission.

[0034] In the prior art, the chip architecture that can be designed for testing mostly adopts a clock gating structure to achieve the purpose of reducing the dynamic power consumption of the circuit, but it cannot eliminate the leakage current and there is still a large static power consumption. The technical solution provided in this embodiment, on the basis of the prior art, divides as many test logics as possible into independent test logic modules through the division of multiple power domains, and distributes the divided parts to different voltage domains for power supply, so that the independent test logic modules can be completely powered off when the chip is working, so as to achieve the purpose of greatly reducing the static power consumption and making the overall power consumption of the circuit lower. At the same time, when the chip needs to be tested, the test power domain can be powered normally, and the independent test logic module can work normally, which will not cause adverse effects on the normal operation of the test mode.

[0035] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that the present invention includes but is not limited to the contents described in the drawings and the above specific embodiments. Any modification that does not deviate from the functional and structural principles of the present invention will be included in the scope of the claims.

Claims

1. A chip testability architecture system, the testability architecture system comprising a test logic module and a functional logic module, characterized in that: The test logic module includes an independent test unit and a mixed test unit, the mixed test unit is mixed with the functional logic module, and the independent test unit is separated from the functional logic module; The testability architecture system has a functional mode and a test mode. In the functional mode, the power supply of the independent test unit is disconnected, and the power supply of the hybrid test unit and the functional logic module is in an on state; in the test mode, the power supply of the independent test unit, the hybrid test unit and the functional logic module is in an on state; The testability architecture system has a test power domain and a functional power domain, the independent test unit is powered by VDD_test in the test power domain, and the mixed test unit and the functional logic module are powered by VDD_func in the functional power domain; The testability architecture system further includes a power switch controller unit and a power switch cells unit, wherein the power switch controller unit is signal-connected to the power switch cells unit, and in a functional mode, the power switch controller unit sends a shutdown control signal to the power switch cells unit, and the power switch cells unit disconnects the power supply between VDD_test and the independent test unit; The power switch controller unit and the power switch cells unit are powered by VDD_func in the functional power domain; The power switch cells have an input end and an output end, the input end is connected to VDD_func, and the output end is connected to VDD_test; The functional mode and test mode of the testability architecture system are determined according to the test_mode signal; The default value of the test_mode signal is 0, the testability architecture system is in functional mode, and the power switch controller unit sends a shutdown control signal to the power switch cells unit after receiving the test_mode signal; The test_mode signal is set to 1, the testability architecture system is in test mode, and the power switch controller unit sends an open control signal to the power switch cells unit after receiving the test_mode signal, and the power switch cells unit restores the power supply between VDD_test and the independent test unit.

2. The testability architecture system according to claim 1, characterized in that: The power switch cells unit has a plurality of switch cells, and the plurality of switch cells are connected end to end around the independent test unit to form a closed loop, or the plurality of switch cells are evenly distributed in a dot matrix around the independent test unit.

3. The testability architecture system according to claim 1, characterized in that: The test_mode signal is input from the outside of the chip through an I / O port or generated inside the chip.

4. The testability architecture system according to claim 1, characterized in that: The testability architecture system also includes isolation cells units; In the functional mode, the isolation cells unit is in an enabled state after receiving a test_mode signal of 0, and the signal output by the independent test cell is locked to a fixed value to isolate the functional logic module; In the test mode, the isolation cells are in a disabled state after receiving a test_mode signal of 1, and the isolated test cells are signal-connected to the functional logic module.

5. The testability architecture system according to claim 4, characterized in that: The isolation cells are powered by VDD_func in the functional power domain.

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