Semiconductor device and method for forming the same

Abstract

The present invention provides a semiconductor device and a method for forming the same, the method comprising: providing a substrate, the substrate having an interlayer dielectric layer; forming an etching barrier layer on the interlayer dielectric layer; etching the etching barrier layer until the surface of the interlayer dielectric layer is exposed to form an opening; and filling the opening with a high resistance layer. The present invention improves the performance and stability of the formed semiconductor device; and at the same time ensures that the formed high resistance layer has a high quality.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. As the most basic semiconductor device, the device is currently being widely used. The control ability of traditional planar devices on channel current has weakened, resulting in short channel effect and leakage current, which ultimately affects the electrical performance of semiconductor devices.

[0003] In the process of manufacturing semiconductor devices, it is necessary to form contact holes on the source region, drain region or gate structure of the transistor, and then fill the contact holes with conductive materials to form metal plugs, so that the transistor and other components can be electrically connected to the interconnection metal layer through the metal plugs. As the size of semiconductor devices decreases, the size of contact holes also decreases. However, as the size of contact holes decreases, it is not possible to ensure the formation of good quality metal plugs, which affects the quality of the formed semiconductor devices.

[0004] How to form semiconductor devices with good quality is an urgent problem that needs to be solved. Summary of the invention

[0005] The problem solved by the present invention is to provide a semiconductor device and a method for forming the same, thereby ensuring that the formed semiconductor device has higher quality.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor device, comprising: providing a substrate having an interlayer dielectric layer; forming an etch barrier layer on the interlayer dielectric layer; etching the etch barrier layer until the surface of the interlayer dielectric layer is exposed to form an opening; and filling the opening with a high resistance layer.

[0007] Optionally, the high resistance layer is filled by a selective growth method.

[0008] Optionally, the material of the high resistance layer is TiN or TaN or TiO2 or WN or WSi.

[0009] Optionally, the opening is formed by dry etching or wet etching.

[0010] Optionally, the etch stop layer material includes one or more of silicon nitride, silicon oxynitride or silicon oxide.

[0011] Optionally, the method of forming the etch stop layer includes one or more of chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0012] Optionally, before forming the etching barrier layer on the interlayer dielectric layer, a metal plug is further formed, and the steps of forming the metal plug include: forming a contact hole in the interlayer dielectric layer, the bottom of the contact hole exposing the surface of the substrate; forming a diffusion barrier layer on the bottom, sidewall and interlayer dielectric layer of the contact hole; filling the contact hole with a metal layer to form a metal plug.

[0013] Optionally, the method of forming the metal layer includes one or more of selective growth and chemical vapor deposition.

[0014] Optionally, the material of the metal layer is tungsten or cobalt.

[0015] Optionally, the step of forming the metal plug further includes: removing the diffusion barrier layer before filling the metal layer in the contact hole.

[0016] Correspondingly, the present invention also provides a semiconductor device, comprising: a substrate; an interlayer dielectric layer located on the substrate; an etch stop layer located on the interlayer dielectric layer; an opening located in the etch stop layer, with the bottom exposing the surface of the interlayer dielectric layer; and a high resistance layer located in the opening and filling the opening.

[0017] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0018] First, an opening is formed in the etching barrier layer, and then the opening is filled with a high resistance layer; the position where the high resistance layer is to be formed is set first, and there is no need to etch and remove part of the high resistance layer after the high resistance layer is formed, but the high resistance layer is left at the set position at one time; in this way, it is ensured that the etching barrier layer will not be damaged when the high resistance layer is formed, thereby ensuring the surface quality of the etching barrier layer and the semiconductor components covered by the etching barrier layer are not damaged, so that the performance and stability of the formed semiconductor device are improved; at the same time, since the high resistance layer is directly formed on the surface of the interlayer dielectric layer, after the stacked metal layers are subsequently formed, when flattening is performed, since the high resistance layer is far away from the plane to be flattened, the high resistance layer will not be damaged during flattening, thereby ensuring the quality of the formed high resistance layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figures 1 to 5 is a structural schematic diagram of a semiconductor device forming process in one embodiment;

[0020] Figures 6 to 16 is a structural schematic diagram of a semiconductor device forming process in a first embodiment of the present invention;

[0021] Figure 17 to Figure 18 It is a structural schematic diagram of the semiconductor device forming process in the second embodiment of the present invention. DETAILED DESCRIPTION

[0022] In the process of forming semiconductor devices, metal plugs need to be formed so as to form electrical connections with interconnect metal layers using the metal plugs. However, in the process of forming metal plugs, it is easy to cause the metal plugs to be missing, resulting in poor performance of the formed semiconductor devices. For the specific formation process, please refer to Figures 1 to 5 .

[0023] First reference Figure 1 , a substrate 1 is provided, on which an interlayer dielectric layer 2 is formed.

[0024] refer to Figure 2 , etching the interlayer dielectric layer 2 to form a contact hole 3 in the dielectric 2.

[0025] refer to Figure 3 , a metal material is filled in the contact hole 3 to form a metal plug 4 , and the top surface of the metal plug 4 is flush with the top surface of the interlayer dielectric layer 2 .

[0026] refer to Figure 4 , an etching stop layer 5 is formed on the surfaces of the interlayer dielectric layer 2 and the metal plug 4.

[0027] refer to Figure 5 , a high resistance material is deposited on the etching stop layer 5 , and the high resistance material is etched to form a high resistance layer 6 .

[0028] The inventors have found that the semiconductor device formed by this method has poor stability in performance and is prone to failure, which limits the use of semiconductor devices. This is because when etching the high-resistance material to form the high-resistance layer 6, it is easy to over-etch part of the etching barrier layer 5, damaging the etching barrier layer 5 and the metal plug 4 covered under the etching barrier layer 5, resulting in the formed metal plug 4 and the etching barrier layer 5 having poor quality, thereby making the formed semiconductor device have poor performance stability, which limits the use of semiconductor devices.

[0029] The inventors have found that after the etch barrier layer is formed on the interlayer dielectric layer, the etch barrier layer is etched to form an opening in the etch barrier layer, and a high resistance layer is filled in the opening. Since there is no need to etch the high resistance layer, the formed etch barrier layer and the semiconductor components covered by the etch barrier layer are not damaged, thereby improving the quality and stability of the formed semiconductor device.

[0030] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0031] First embodiment

[0032] Figures 6 to 16 It is a structural schematic diagram of the semiconductor device forming process in the first embodiment of the present invention.

[0033] First reference Figure 6 , providing the substrate 100, and the substrate 100 has an interlayer dielectric layer 200.

[0034] In this embodiment, the base 100 includes a substrate, and storage devices and logic devices located on the substrate.

[0035] In this embodiment, the material of the interlayer dielectric layer 200 is silicon oxide.

[0036] In other embodiments, the material of the interlayer dielectric layer 200 may also be silicon nitride, silicon boron nitride, silicon carbon nitride oxide, or silicon nitride oxide.

[0037] In this embodiment, the interlayer dielectric layer 200 is formed on the substrate 100 by chemical vapor deposition. The process parameters of the chemical vapor deposition process include the gases used including oxygen, ammonia (NH3), and N(SiH3)3 gas, the flow rate of oxygen is 20sccm-10000sccm, the flow rate of ammonia (NH3) gas is 20sccm-10000sccm, the flow rate of N(SiH3)3 gas is 20sccm-10000sccm, the chamber pressure is 0.01-10 Torr, and the temperature is 30°C-90°C.

[0038] refer to Figure 7 , the interlayer dielectric layer 200 is etched to form a contact hole 210 in the interlayer dielectric layer 200 , and the bottom of the contact hole 210 exposes the surface of the substrate 100 .

[0039] In this embodiment, the contact hole 210 is formed by a dry etching process; the parameters of the dry etching process include: the gases used include CF4 and CH3F, the flow rate of CF4 is 20sccm~200sccm, the flow rate of CH3F is 20sccm~50sccm, the source RF power is 200W~500W, and the chamber pressure is 1torr~10torr.

[0040] refer to Figure 8 A diffusion barrier layer 220 is formed on the bottom and sidewall of the contact hole 210 and the interlayer dielectric layer 200 .

[0041] In this embodiment, before forming the diffusion barrier layer 220 , a reactive metal layer (not shown) is formed on the bottom and sidewalls of the contact hole 210 and the interlayer dielectric layer 200 , and the reactive metal layer reacts with the substrate 100 to form a silicide layer 230 .

[0042] In this embodiment, the silicide layer 230 is formed during a heat treatment process.

[0043] In this embodiment, the material of the diffusion barrier layer 220 is TiN; in other embodiments, the material of the diffusion barrier layer 220 may also be TaN or the like.

[0044] refer to Fig. 9 , a metal layer 211 is filled in the contact hole 210 to form a metal plug 300 .

[0045] In this embodiment, the material of the metal layer 211 is tungsten (W); in other embodiments, the material of the metal layer 211 may also be cobalt (Co), copper, aluminum, etc.

[0046] In this embodiment, the metal layer 211 is formed by combining selective growth and chemical vapor deposition.

[0047] In other embodiments, chemical vapor deposition may be used to form the metal layer 211 , and the metal layer 211 may be planarized to form the metal plug 300 .

[0048] In this embodiment, after the metal layer 211 is formed, the metal layer 211 is planarized so that the top surface of the metal layer 211 is flush with the top of the diffusion barrier layer 220 .

[0049] refer to Figure 9a to Figure 9b The process of forming the metal layer 211 is specifically referred to Figure 9a First, a first metal layer 212 is formed by a selective growth method to fill the contact hole 210, and the top of the first metal layer 212 is higher than the surface of the diffusion barrier layer 220; Figure 9b , a second metal layer 213 is formed on the surface of the diffusion barrier layer 220 by chemical vapor deposition. After the first metal layer 212 and the second metal layer 213 are formed, the surfaces of the first metal layer 212 and the second metal layer 213 are planarized by chemical mechanical polishing until the surface of the diffusion barrier layer 220 is exposed (refer to Fig. 9 ).

[0050] In the present embodiment, the metal layer 211 is formed by combining a selective growth method with a chemical vapor deposition method. The reason is that the first metal layer 212 is first formed by a selective growth method to ensure that the first metal layer 212 is dense inside and has no holes inside, thereby ensuring the performance of the formed semiconductor device. In addition, the second metal layer 213 is formed by a chemical vapor deposition method in order to flatten the metal layer 211 to provide an excess portion, thereby facilitating the formation of the metal layer 211 with good surface quality.

[0051] refer to Fig.10 , an etching barrier layer 400 is formed on the diffusion barrier layer 220 .

[0052] In this embodiment, the material of the etch stop layer 400 is silicon nitride; in other embodiments, the material of the etch stop layer 400 may also be one or more combinations of silicon nitride, silicon oxynitride or silicon oxide.

[0053] In this embodiment, the etching stop layer 400 is formed by chemical vapor deposition.

[0054] In other embodiments, the etching stop layer 400 may be formed by physical vapor deposition, atomic layer deposition, or the like.

[0055] refer to Fig.11 , the etch barrier layer 400 is etched until the surface of the diffusion barrier layer 220 is exposed, thereby forming an opening 500 .

[0056] In this embodiment, the opening 500 is formed by dry etching; in other embodiments, the opening 500 may also be formed by wet etching.

[0057] In this embodiment, the process parameters for forming the opening 500 include selecting helium (He), ammonia (NH3) and CF4 gases as etching atmospheres, wherein the gas flow range of the helium (He) is 600sccm~2000sccm, the gas flow range of the ammonia (NH3) is 200sccm~5000sccm, the CF4 gas flow range is 10sccm~2000sccm, the etching pressure is 2~100 mTorr, and the etching processing time is 20~1000s.

[0058] refer to Fig.12 , the opening 500 is fully filled with a high resistance layer 600 .

[0059] In this embodiment, the high resistance layer 600 is formed by a selective growth method.

[0060] In this embodiment, the material of the high resistance layer 600 is TiN; in other embodiments, the material of the high resistance layer 600 may also be TaN or TiO 2 or WN or WSi.

[0061] In this embodiment, the process parameters for forming the high resistance layer 600 by the selective growth method include: the reaction gases used include TiCl4 and ammonia (NH3), wherein the gas flow rate of the ammonia (NH3) is 10sccm~2000sccm, and the gas flow rate of the TiCl4 is 10sccm~1000sccm; the power is 200~1000W; the growth temperature is 50℃~500℃; and the growth pressure is 2~100 mTorr.

[0062] In the present embodiment, since the high resistance layer 600 is filled in the opening 500 by selective growth, the growth of the high resistance layer 600 starts from the bottom of the opening 500 and gradually grows upward without damaging the formed etching barrier layer 400 and the metal plug 300 covered by the etching barrier layer 400, thereby improving the quality of the formed semiconductor device; at the same time, since the high resistance layer 600 is directly formed on the surface of the diffusion barrier layer 220, it is subsequently planarized after the stacked metal layers are formed. Since the high resistance layer 600 is far away from the planarized surface, the high resistance layer 600 will not be recessed during the planarization process, thereby ensuring the quality of the formed high resistance layer 600, thereby improving the performance of the formed semiconductor device.

[0063] A semiconductor device formed by the above method includes: a substrate 100; an interlayer dielectric layer 200, located on the substrate 100; a contact hole 210, located in the interlayer dielectric layer 200; a silicide layer 230, located on the substrate 100; a diffusion barrier layer 220, located at the bottom and sidewall of the contact hole 210 and on the interlayer dielectric layer 200; a metal plug 300 composed of a metal layer 211; the metal layer 211, located in the contact hole 210 and on the diffusion barrier layer 220; an etching barrier layer 400, located on the interlayer dielectric layer 200 and the metal plug 300; an opening 500, located in the etching barrier layer 400; and a high resistance layer 600, located in the opening 500 and filling the opening 500.

[0064] refer to Fig.13 , a dielectric layer 700 is formed on the high resistance layer 600 and the etching stop layer 400 .

[0065] In this embodiment, the dielectric layer 700 is formed by chemical vapor deposition. In other embodiments, the dielectric layer 700 may be formed by physical vapor deposition or atomic layer vapor deposition.

[0066] In this embodiment, the material of the dielectric layer 700 is silicon oxide; in other embodiments, the material of the dielectric layer 700 may also be silicon carbide, silicon oxynitride, silicon nitride, etc.

[0067] refer to Fig.14 , a patterned layer 800 is formed on the dielectric layer 700 , and the dielectric layer 700 and a portion of the etch stop layer 400 are etched using the patterned layer 800 as a mask to form a first opening 710 , a second opening 720 and a third opening 730 .

[0068] The first opening 710 exposes the surface of the metal plug 300 , and the second opening 720 and the third opening 730 expose a portion of the surface of the high resistance layer 600 .

[0069] refer to Fig.15 , remove the patterned layer 800.

[0070] In this embodiment, the patterned layer 800 is removed by an ashing process; in other embodiments, a chemical solution may be used to remove the patterned layer 800.

[0071] refer to Fig.16 , a first metal layer 900 is filled in the first opening 710 , the second opening 720 , and the third opening 730 .

[0072] In this embodiment, after the first metal layer 900 is formed, the first metal layer 900 is planarized until the surface is flat.

[0073] In this embodiment, the first metal layer 900 is formed by a selective growth method; in other embodiments, the first metal layer 900 may also be formed by a chemical vapor deposition method or an atomic layer vapor deposition method.

[0074] Second embodiment

[0075] Figure 17 to Figure 18 It is a structural schematic diagram of the semiconductor device forming process in the second embodiment of the present invention.

[0076] The difference between this embodiment and the first embodiment is that the diffusion barrier layer is removed before the metal layer is filled in the contact hole. Figure 17 to Figure 18 .

[0077] The steps from providing the substrate 100 to forming the diffusion barrier layer 220 are the same as those of the first embodiment, and the specific reference is made to Figures 6 to 8 .

[0078] refer to Fig.17 , removing the diffusion barrier layer 220.

[0079] In this embodiment, wet etching is used to remove the diffusion barrier layer 220 ; in other embodiments, dry etching or wet cleaning may be used to remove the diffusion barrier layer 220 .

[0080] refer to Fig.18 , a metal layer 211 is filled in the contact hole 210 to form a metal plug 300 .

[0081] In this embodiment, the metal layer 211 is located on the surface of the silicide layer 230. Since the metal layer 211 and the silicide layer 230 are in direct contact, the contact resistance between the metal layer 211 and the silicide layer 230 is reduced, thereby reducing the heat generation of the semiconductor device during use and improving the quality and service life of the semiconductor device.

[0082] After the metal plug 300 is formed, the process of forming the high resistance layer 600 is the same as that in the first embodiment, and will not be described here in detail. Figures 10 to 12 .

[0083] A semiconductor device formed by the above method includes: a substrate 100; an interlayer dielectric layer 200, which is located on the substrate 100; a contact hole 210, which is located in the interlayer dielectric layer 200; a silicide layer 230, which is located on the substrate 100; a metal plug 300 composed of a metal layer 211; the metal layer 211 is located in the contact hole 210 and on the silicide layer 230; an etch stop layer 400, which is located on the interlayer dielectric layer 200 and the metal plug 300; an opening 500, which is located in the etch stop layer 400; and a high resistance layer 600, which is located in the opening 500 and fills the opening 500.

[0084] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor device, characterized in that: include: Providing a substrate, wherein the substrate has an interlayer dielectric layer, and forming a metal plug in the interlayer dielectric layer; forming an etching stop layer on the interlayer dielectric layer; Etching the etching stop layer until the surface of the interlayer dielectric layer is exposed to form an opening; The opening is filled with a high resistance layer.

2. The forming method according to claim 1, characterized in that: The high resistance layer is filled by a selective growth method.

3. The forming method according to claim 1, characterized in that: The material of the high resistance layer is TiN or TaN or TiO2 or WN or WSi.

4. The forming method according to claim 1, characterized in that: The opening is formed by dry etching or wet etching.

5. The forming method according to claim 1, characterized in that: The etch stop layer material includes one or more of silicon nitride, silicon oxynitride or silicon oxide.

6. The forming method according to claim 1, characterized in that: The method of forming the etch stop layer includes one or more of chemical vapor deposition, physical vapor deposition or atomic layer deposition.

7. The forming method according to claim 1, characterized in that: Before forming the etching stop layer on the interlayer dielectric layer, a metal plug is formed. The steps of forming the metal plug include: forming a contact hole in the interlayer dielectric layer, wherein the bottom of the contact hole exposes the surface of the substrate; forming a diffusion barrier layer on the bottom and sidewall of the contact hole and the interlayer dielectric layer; A metal layer is filled in the contact hole to form a metal plug.

8. The forming method according to claim 7, characterized in that: The method of forming the metal layer includes one or more of selective growth and chemical vapor deposition.

9. The forming method according to claim 7, characterized in that: The material of the metal layer is tungsten or cobalt.

10. The forming method according to claim 7, characterized in that: The step of forming the metal plug further includes: removing the diffusion barrier layer before filling the metal layer in the contact hole.

11. A semiconductor device formed by the forming method according to any one of claims 1 to 10, characterized in that: include: substrate; An interlayer dielectric layer, located on the substrate; An etching stop layer, located on the interlayer dielectric layer; An opening, located in the etching stop layer, with the bottom thereof exposing the surface of the interlayer dielectric layer; The high resistance layer is located in the opening and completely fills the opening.

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