Antenna semiconductor packaging device and manufacturing method thereof

Abstract

The present disclosure provides an antenna semiconductor packaging device and a manufacturing method thereof. A specific embodiment of the antenna semiconductor packaging device includes: a circuit layer having a first area and a second area; an antenna layer, which is arranged on the second area and away from the first area, wherein the packaging materials of the first area and the second area are different, the packaging materials of the first area and the antenna layer are the same, and the thickness of the first area and the antenna layer is the same. The antenna semiconductor packaging device adopts a combination of different packaging materials and a symmetrical structure to obtain a final antenna semiconductor packaging device, which can reduce warping and achieve both reducing the thickness of the antenna semiconductor packaging device without significantly increasing the cost and not reducing the RF performance of the antenna.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor packaging devices, and in particular to an antenna semiconductor packaging device and a manufacturing method thereof. Background Art

[0002] As people rely more on mobile networks and wireless communication technology evolves, available frequency bands are becoming increasingly limited. Therefore, in the fifth generation mobile networks (5G), the industry has begun to pay attention to the important key factor of millimeter wave (mmWave). Compared with the currently commonly used limited frequency bands such as 2.4GHz and 5GHz, the 30-300GHz frequency band defined by millimeter wave is relatively abundant and clean, and its antenna design can also be more miniaturized to enhance the convenience of portable products.

[0003] At present, various antenna structures have the following problems:

[0004] First, the asymmetric structure causes warping: AoP (Antenna on Package) has adopted a low dielectric (low dk / df) material for the substrate on the antenna side in consideration of the antenna radiation effect. However, due to the asymmetric structure of the upper and lower substrates, the overall structure warps more than 5 mm, making it impossible to continue the subsequent process.

[0005] Second, the thickness of the traditional PP (PrePreg, prepreg material or semi-cured resin, semi-cured sheet) substrate is relatively thick: Due to the thickness of the traditional PP substrate, it is not suitable for application to high-frequency circuits and is not suitable for application in portable products that require a smaller thickness (for example, smart phones).

[0006] Third, low dielectric materials are expensive: If all substrates are made of low dielectric materials, due to the high price of low dielectric materials, there is a problem that they cannot be used in large quantities due to high economic conditions.

[0007] Fourth, composite structure: The different coefficients of thermal expansion (CTE) of the materials in the composite structure lead to a mismatch in thermal expansion coefficients, which can also cause warping. It may also cause delamination of the dielectric material due to different properties, and the yield will be close to 0%. Summary of the invention

[0008] The present disclosure provides an antenna semiconductor package device and a method for manufacturing the same.

[0009] In a first aspect, the present disclosure provides an antenna semiconductor packaging device, which includes: a circuit layer having a first area and a second area; an antenna layer, which is arranged on the second area and away from the first area, wherein the packaging materials of the first area and the second area are different, the packaging materials of the first area and the antenna layer are the same, and the thickness of the first area and the antenna layer are the same.

[0010] In some optional embodiments, the antenna semiconductor packaging device also includes: a first buffer layer, arranged between the first zone and the second zone, wherein the thermal expansion coefficient of the first buffer layer is greater than or equal to the first thermal expansion coefficient and less than or equal to the second thermal expansion coefficient, the first thermal expansion coefficient is the smaller of the thermal expansion coefficient of the packaging material of the first zone and the thermal expansion coefficient of the packaging material of the second zone, and the second thermal expansion coefficient is the larger of the thermal expansion coefficient of the packaging material of the first zone and the thermal expansion coefficient of the packaging material of the second zone.

[0011] In some optional embodiments, the antenna semiconductor packaging device also includes: a second buffer layer, arranged between the second zone and the antenna layer, wherein the thermal expansion coefficient of the second buffer layer is greater than or equal to a third thermal expansion coefficient and less than or equal to a fourth thermal expansion coefficient, the third thermal expansion coefficient is the smaller of the thermal expansion coefficient of the packaging material of the second zone and the thermal expansion coefficient of the packaging material of the antenna layer, and the fourth thermal expansion coefficient is the larger of the thermal expansion coefficient of the packaging material of the second zone and the thermal expansion coefficient of the packaging material of the antenna layer.

[0012] In some optional embodiments, a core board is disposed in the second zone, and the core board divides the second zone into a third zone and a fourth zone, and the number of circuit layers in the third zone is the same as the number of circuit layers in the fourth zone.

[0013] In some optional embodiments, the dielectric constant of the packaging material of the second zone is greater than the dielectric constant of the packaging material of the first zone and the antenna layer, and / or the dielectric loss of the packaging material of the second zone is greater than the dielectric loss of the packaging material of the first zone and the antenna layer.

[0014] In some optional embodiments, the packaging material of the antenna layer is a low dielectric constant / dielectric loss material.

[0015] In some optional embodiments, the diameter of the guide holes in the first region is smaller than that of the guide holes in the second region, and / or the density of the guide holes in the first region is greater than that of the guide holes in the second region.

[0016] In some optional embodiments, the surface roughness of the first buffer layer near the second region is less than 1.3 microns, and / or the surface roughness of the second buffer layer near the second region is less than 1.3 microns.

[0017] In some optional embodiments, the thickness of the antenna layer is greater than the thickness of the fourth region.

[0018] In some optional embodiments, the antenna semiconductor package device further includes a radio frequency chip electrically connected to the circuits in the first region.

[0019] In a second aspect, the present disclosure provides a method for manufacturing an antenna semiconductor packaging device, the method comprising: providing a first circuit layer to form a second area, the second area having a first surface and a second surface; setting a second circuit layer on the first surface as the first area, wherein the first area and the second area constitute a circuit layer, wherein the packaging materials of the first area and the second area are different; setting an antenna layer on the second surface, the first area and the antenna layer have the same packaging material, and the first area and the antenna layer have the same thickness.

[0020] In some optional embodiments, providing a first circuit layer to form a second zone includes: providing a core board, wherein the core board has a third surface, a fourth surface and a through hole, and the through hole of the core board extends from the third surface to the fourth surface; forming a third circuit layer on the third surface as a third zone; forming a fourth circuit layer on the fourth surface as a fourth zone, wherein the number of circuit layers in the third zone is the same as the number of circuit layers in the fourth zone, and the third zone, the core board and the fourth zone form the second zone.

[0021] In some optional embodiments, before disposing the antenna layer on the second surface, the method further includes: disposing a second buffer layer on the second surface of the second region; and disposing the antenna layer on the second buffer layer.

[0022] In order to solve the problems of warping, thick thickness, high cost and delamination that may exist in the antenna semiconductor packaging structure in the prior art, the antenna semiconductor packaging device and its manufacturing method provided by the present disclosure are obtained by combining different packaging materials and adopting a symmetrical structure to obtain the final antenna semiconductor packaging device. Furthermore, the antenna semiconductor packaging device can achieve technical effects including but not limited to the following:

[0023] (1) Reduce warping by adopting a symmetrical structure.

[0024] (2) By using different packaging materials, instead of using all low-cost non-low-dielectric materials (e.g., PP) or all high-cost low-dielectric materials, the thickness of the antenna semiconductor packaging device is reduced without significantly increasing the cost and without reducing the RF performance of the antenna. It should be noted that here, the dielectric constant / dielectric loss of the non-low-dielectric material is greater than the dielectric constant / dielectric loss of the low-dielectric material. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Other features, objects and advantages of the present disclosure will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0026] Figure 1A is a cross-sectional schematic diagram of an embodiment of an antenna semiconductor package device according to the present disclosure;

[0027] Figure 1B is a cross-sectional schematic diagram of another embodiment of an antenna semiconductor package device according to the present disclosure;

[0028] Figure 1C is a cross-sectional schematic diagram of another embodiment of an antenna semiconductor package device according to the present disclosure;

[0029] Figure 1D is a cross-sectional schematic diagram of another embodiment of an antenna semiconductor package device according to the present disclosure;

[0030] Figure 1E is a cross-sectional schematic diagram of another embodiment of an antenna semiconductor package device according to the present disclosure;

[0031] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F and Figure 2G are cross-sectional schematic diagrams of antenna semiconductor package devices 2a, 2b, 2c, 2d, 2e, 2f, and 2g manufactured at various stages according to some embodiments of the present disclosure;

[0032] Figure 2A1 , Figure 2A2 , Figure 2A3 is a schematic cross-sectional view of an antenna semiconductor package device 2a at various manufacturing stages according to some embodiments of the present disclosure.

[0033] Explanation of symbols:

[0034] 1 Circuit layer 13 First buffer layer

[0035] 11. Zone 1 2 Antenna layer

[0036] 11a External electrical connection 2a Antenna

[0037] 11b Through hole 3 Second buffer layer

[0038] 12 Second Zone 4 RF Chip

[0039] 12a Wire 123 Core Board

[0040] 12b buried hole 123a third side

[0041] 12c first side 123b fourth side

[0042] 12d Second surface 123c Through hole

[0043] 121 Third zone 123d Electrical connector

[0044] 122 District 4 DETAILED DESCRIPTION

[0045] The specific implementation methods of the present disclosure are described below in conjunction with the accompanying drawings and embodiments. Through the contents recorded in this specification, those skilled in the art can easily understand the technical problems solved by the present disclosure and the technical effects produced. It is understood that the specific embodiments described herein are only used to explain the relevant inventions, rather than to limit the inventions. In addition, for ease of description, only the parts related to the relevant inventions are shown in the accompanying drawings.

[0046] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present disclosure, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects and purposes that can be achieved by the present disclosure, should still fall within the scope of the technical content disclosed by the present disclosure. At the same time, the terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present disclosure. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present disclosure without substantially changing the technical content.

[0047] In addition, the embodiments and features in the embodiments of the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0048] An antenna semiconductor package device including an antenna or an antenna structure may also be referred to as an antenna in package (AiP) or an antenna on package (AoP).

[0049] refer to Figure 1A , Figure 1A A cross-sectional view of an embodiment of an antenna semiconductor package device 1a according to the present disclosure is shown. The antenna semiconductor package device 1a may be an example of AiP / AoP. The antenna semiconductor package device 1a includes a circuit layer 1 and an antenna layer 2. The circuit layer 1 has a first area 11 and a second area 12. The antenna layer 2 is disposed on the second area 12 and away from the first area 11. The packaging materials of the first area 11 and the second area 12 are different, the packaging materials of the first area 11 and the antenna layer 2 are the same, and the thickness of the first area 11 and the antenna layer 2 is the same.

[0050] An external electrical connector 11a may be disposed on the surface of the first region 11. The external electrical connector 11a is used to realize electrical connection between the first region and the outside, for example, the external electrical connector 11a may be a wire, a bump, a solder ball, etc.

[0051] In some optional implementations, through holes, buried holes or blind holes may also be provided in the first region 11 to achieve line connection. Figure 1A The through hole 11b is shown in FIG.

[0052] At least one conductive wire 12a may be disposed in the second region 12. In some optional embodiments, a through hole, a buried hole or a blind hole may also be disposed in the second region 12 to achieve line connection. Figure 1A It should be noted that the size or direction of the through hole, buried via or blind via is not specifically limited here.

[0053] If a through hole, a buried hole or a blind hole is provided in the first area 11 or the second area 12, the through hole, the buried hole or the blind hole may be filled with a conductive material such as a metal or a metal alloy, or may contain a conductive material such as a metal or a metal alloy. Here, the metal may be, for example, gold (Au), silver (Ag), aluminum (Al), copper (Cu) or an alloy thereof.

[0054] At least one antenna 2a may be provided in the antenna layer 2. The external electrical connector 11a, the wire 12a and the antenna 2a may be a conductive material such as a metal or a metal alloy, or may include a conductive material such as a metal or a metal alloy. Here, the metal may be, for example, gold (Au), silver (Ag), aluminum (Al), copper (Cu) or an alloy thereof.

[0055] The technical effects that the antenna semiconductor packaging device 1a can achieve include but are not limited to:

[0056] (1) By using the same packaging material as the first region 11 and the antenna layer 2 and having the same thickness as the first region 11 and the antenna layer 2, a symmetrical structure is achieved and warping is reduced.

[0057] (2) By using different packaging materials for the first area 11 and the second area 12, and using the same packaging material for the first area 11 and the antenna layer 2, instead of using all low-cost non-low-dielectric materials or all high-cost low-dielectric materials, the thickness of the antenna semiconductor packaging device can be reduced without significantly increasing the cost and without reducing the RF performance of the antenna.

[0058] In summary, the RF performance requirements of the antenna semiconductor package device 1a are taken into consideration, warping is reduced, thickness is reduced, and cost is lowered.

[0059] Continue to refer Figure 1B , Figure 1B The antenna semiconductor package device 1b shown in FIG. Figure 1A The antenna semiconductor package device 1a shown in the figure is different in that the antenna semiconductor package device 1b further includes: a first buffer layer 13, which is arranged between the first area 11 and the second area 12. The thermal expansion coefficient of the first buffer layer 13 is greater than or equal to the first thermal expansion coefficient and less than or equal to the second thermal expansion coefficient. The first thermal expansion coefficient is the smaller of the thermal expansion coefficient of the packaging material of the first area 11 and the thermal expansion coefficient of the packaging material of the second area 12, and the second thermal expansion coefficient is the larger of the thermal expansion coefficient of the packaging material of the first area 11 and the thermal expansion coefficient of the packaging material of the second area 12. That is, the thermal expansion coefficient of the first buffer layer 13 is between the thermal expansion coefficient of the packaging material of the first area 11 and the thermal expansion coefficient of the packaging material of the second area 12. As an example, the first buffer layer 13 can be made of the following materials: ABF (Ajinomoto Build-up Film), PBO (Polybenzoxazole), PI (polyimide) or Epoxy.

[0060] The antenna semiconductor package device 1b can further reduce the warpage that may be caused by the different packaging materials and thus different thermal expansion coefficients of the first and second regions by providing the first buffer layer 13. In addition, in practice, the first buffer layer is usually viscous, so by providing the first buffer layer 13, the packaging materials of the first region 11 and the packaging materials of the second region 12 can be better bonded, thereby improving the impact resistance of the antenna semiconductor package device 1b and further reducing warpage.

[0061] Continue to refer Figure 1C , Figure 1C The antenna semiconductor package device 1c shown in FIG. Figure 1A or Figure 1BThe antenna semiconductor packaging device 1a or 1b shown in the figure is different in that the antenna semiconductor packaging device 1c also includes: a second buffer layer 3, which is arranged between the first zone 11 and the antenna layer 2. Among them, the thermal expansion coefficient of the second buffer layer 3 is greater than or equal to the third thermal expansion coefficient and less than or equal to the fourth thermal expansion coefficient. The third thermal expansion coefficient is the smaller of the thermal expansion coefficient of the packaging material of the second zone 12 and the thermal expansion coefficient of the packaging material of the antenna layer 2, and the fourth thermal expansion coefficient is the larger of the thermal expansion coefficient of the packaging material of the second zone 12 and the thermal expansion coefficient of the packaging material of the antenna layer 2. That is, the thermal expansion coefficient of the second buffer layer 3 is between the thermal expansion coefficient of the packaging material of the second zone 12 and the thermal expansion coefficient of the packaging material of the antenna layer 2. As an example, the second buffer layer 3 can be made of the following materials: ABF, PBO, PI or Epoxy.

[0062] The antenna semiconductor package device 1c can further reduce the warpage that may be caused by the different packaging materials and thus different thermal expansion coefficients of the second area 12 and the antenna layer 2 by providing the second buffer layer 3. In addition, in practice, the second buffer layer 3 is usually sticky, so by providing the second buffer layer 3, the packaging material of the second area 12 and the packaging material of the antenna layer 2 can be better bonded, thereby improving the impact resistance of the antenna semiconductor package device 1c and further reducing warpage.

[0063] Continue to refer Figure 1D , Figure 1D The antenna semiconductor package device 1d shown in FIG. Figure 1A , Figure 1B or Figure 1C The antenna semiconductor packaging device 1a, 1b or 1c shown in the figure is different in that a core board 123 can be arranged in the second area 12, and the core board 123 separates the second area 12 into a third area 121 and a fourth area 122. The number of circuit layers in the third area 121 is the same as the number of circuit layers in the fourth area 122, that is, the thickness of the third area 121 is the same as the thickness of the fourth area 122.

[0064] The core board 123 may be provided with at least one through hole 123a, and the through hole 123a may realize electrical connection between the third area 121 and the fourth area 122. Here, the material of the core board 123 is, for example, glass fiber (such as fiber cotton pad or special fiber filling) and resin. When making, the glass fiber is immersed in the resin liquid, and the formed core board 123 is made of glass fiber with warp and weft interlaced and impregnated with resin. The resin material is, for example, ABF resin, BT (Bismaleimide Triazine, bismaleimide triazine) resin, glass cloth-based epoxy resin (FR4, FR5), PI resin, liquid crystal polymer resin (LCP), or epoxy resin (Epoxy). The through hole 123a may be filled with a conductive material such as a metal or a metal alloy, or a conductive material such as a metal or a metal alloy. Here, the metal may be, for example, gold (Au), silver (Ag), aluminum (Al), copper (Cu) or an alloy thereof.

[0065] The antenna semiconductor package device 1d can improve the strength and support of the antenna semiconductor package device 1c and resist warping by setting the core board 123 in the second area 12. In addition, the through hole 123a set in the core board 123 can also become a line connecting the third area 121 and the fourth area 122, thereby forming a part of the antenna semiconductor package device 1d. Moreover, since the core board 123 divides the second area into the third area 121 and the fourth area 122, and the number of line layers in the third area 121 is the same as the number of line layers in the fourth area 122, that is, the thickness of the third area 121 is the same as the thickness of the fourth area 122, thereby ensuring the symmetrical structure of the antenna semiconductor package device 1d and reducing warping.

[0066] In some optional embodiments, the dielectric constant of the packaging material of the second area 12 may be greater than the dielectric constant of the packaging material of the first area 11 and the antenna layer 2, and / or the dielectric loss of the packaging material of the second area 12 may be greater than the dielectric loss of the packaging material of the first area 11 and the antenna layer 2. In this way, the packaging material of the antenna layer 2 has better RF performance than the packaging material of the second area 12, which can ensure the RF performance of the antenna semiconductor packaging device. And because the packaging material of the first area 11 is the same as that of the antenna layer 2, the symmetry of the overall structure of the antenna semiconductor packaging device can be ensured.

[0067] In some optional embodiments, the packaging material of the antenna layer 2 can be a low dielectric constant / dielectric loss material, that is, a low dielectric material. For example, it can include but is not limited to triazine, polyphenylene oxide (PPO), polytetrafluoroethylene (PTFE), Teflon, and polystyrene. The packaging material of the second area 12 can be a non-low dielectric material, such as PP. The technical effects that can be achieved by this optional embodiment further include:

[0068] (1) By using a non-low dielectric material in the second region 12, the cost can be reduced.

[0069] (2) By using low dielectric material as the packaging material in the antenna layer 2, the radio frequency performance of the antenna layer can be ensured and the thickness can be reduced.

[0070] (3) By using the same low dielectric material as the packaging material of the antenna layer 2 in the first region 11 and making the first region 11 and the antenna layer 2 have the same thickness, the symmetrical structure of the antenna semiconductor packaging device 1a can be ensured, thereby reducing warpage.

[0071] Based on the above optional embodiments, in some optional embodiments, the aperture of the guide hole in the first area 11 can be smaller than the aperture of the guide hole in the second area 12, and / or the density of the guide holes in the first area 11 is greater than the density of the guide holes in the second area 12. This is because if a low dielectric material is used in the first area 11, since there is no fiber in the low dielectric material, the aperture of the guide hole that can be drilled in the low dielectric material will be smaller than that of the non-low dielectric material (e.g., PP) in the second area 12, so that the density of the guide holes can be greater. In this way, since the density of the guide holes in the first area 11 is greater, in order to achieve the same circuit connection function, the number of circuit layers required for connecting the circuits in the first area 11 can be less, that is, the thickness of the first area 11 can be thinner, thereby reducing the overall thickness of the antenna semiconductor packaging device.

[0072] In some optional embodiments, the surface roughness of the surface of the first buffer layer 13 near the second area 12 in the antenna semiconductor package device 1b, 1c or 1d can be less than 1.3 microns, and / or the surface roughness of the surface of the second buffer layer 3 near the second area 12 can be less than 1.3 microns. For example, it can be achieved by using plasma or chemicals to pre-treat the surface of the first buffer layer 13 near the second area 12 or the surface of the second buffer layer 3 near the second area 12 to make the surface roughness larger. This optional embodiment can make the antenna semiconductor package device produce a better skin effect and improve the performance of the antenna semiconductor package device by controlling the surface roughness of the first buffer layer 13 and / or the second buffer layer 3 near the second area. At the same time, this optional implementation method can also form an A / B interface between the second area 12 and the first area 11, and / or between the second area 12 and the antenna layer 2 to improve the bonding strength between the second area 12 and the first area 11, and / or between the second area 12 and the antenna layer 2 to resist the internal stress that may be generated by warping, thereby reducing the occurrence of warping.

[0073] In some optional embodiments, the thickness of the antenna layer 2 may be greater than the thickness of the fourth region 122. This optional embodiment can adjust the warpage of the antenna semiconductor package device by making the inner layer thinner and the outer layer thicker.

[0074] In some optional embodiments, the antenna semiconductor package device 1a, 1b, 1c or 1d may further include a radio frequency chip electrically connected to the circuit in the first region.

[0075] Continue to refer Figure 1E , Figure 1E The antenna semiconductor package device 1e shown in FIG. Figure 1A , Figure 1B , Figure 1C The antenna semiconductor package device 1a, 1b, 1c or 1d shown in or 1D is different in that: the antenna semiconductor package device 1e also includes a radio frequency chip 4 electrically connected to the first area 11. When transmitting a signal, the radio frequency chip 4 acts as a wireless transmitter to provide an oscillating radio frequency current to the antenna layer 2 through the first area 11 and the second area 12, and the antenna layer 2 radiates the received oscillating radio frequency current radiation energy as an electromagnetic wave. When receiving a signal, the antenna layer 2 transmits the electromagnetic wave signal to the second area 12 and the first area 11, and the second area 12 and the first area 11 convert the electromagnetic wave signal into a voltage and provide it to the radio frequency chip 4.

[0076] The RF chip 4 can be electrically connected to the first region 11 in various ways, for example, by wire bonding. In some embodiments, the RF chip 4 can also be electrically connected to the first region 11 by flip-chip mounting.

[0077] In some embodiments, the exposed external electrical connector 11a of the first area 11 can also be soldered to other external devices through solder balls, for example, can be soldered to a printed circuit board (PCB) to become an antenna part of the electronic device.

[0078] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F and Figure 2G are cross-sectional schematic diagrams of antenna semiconductor package devices 2a, 2b, 2c, 2d, 2e, 2f, and 2g at various stages of manufacture according to some embodiments of the present disclosure. The figures have been simplified for better understanding of various aspects of the present disclosure.

[0079] refer to Figure 2A , providing a first circuit layer to form a second area 12. Here, the second area 12 may have a first surface 12c and a second surface 12d. At least one conductive line 12a may be provided in the second area 12. In some optional embodiments, a through hole, a buried hole or a blind hole may also be provided in the second area 12 to achieve circuit connection. Figure 2A The buried via 12b is shown in FIG.

[0080] refer to Figure 2B , a second circuit layer is arranged on the first surface 12c as the first area 11. The first area 11 and the second area 12 constitute the circuit layer 1. Here, the packaging materials of the first area 11 and the second area 12 are different.

[0081] An external electrical connector 11a may be provided on the surface of the first region 11. The external electrical connector 11a is used to realize electrical connection between the first region and the outside, for example, the external electrical connector 11a may be a wire, a bump, a solder ball, etc.

[0082] In some optional implementations, through holes, buried holes or blind holes may also be provided in the first region 11 to achieve line connection. Figure 1A The through hole 11b is shown in FIG.

[0083] refer to Figure 2CThe antenna layer 2 is disposed on the second surface 12d. The first area 11 and the antenna layer 2 have the same packaging material, and the first area 11 and the antenna layer 2 have the same thickness. The antenna layer 2 may be provided with at least one antenna 2a.

[0084] The external electrical connector 11a, the wire 12a and the antenna 2a may be, or include, a conductive material such as a metal or a metal alloy. Here, the metal may be, for example, gold (Au), silver (Ag), aluminum (Al), copper (Cu) or an alloy thereof.

[0085] In some optional embodiments, Figure 2A The first circuit layer is provided, and the second area 12 can be formed by the following method:

[0086] First, refer to Figure 2A1 , providing a core board 123, wherein the core board 123 has a third surface 123a and a fourth surface 123b, and the core board 123 also has at least one through hole 123c, and the through hole 123c extends from the third surface 123a to the fourth surface 123b. The core board 123 may also have at least one electrical connector 123d, and the electrical connector 123d is used to realize the connection between the through hole 123c and the outside.

[0087] Then, refer to Figure 2A2 A second circuit layer is disposed on the third surface 123 a of the core board 123 to form the third area 121 .

[0088] Next, refer to Figure 2A3 A third circuit layer is disposed on the fourth surface 123 b of the core board 123 to form the fourth area 122 , and the third area 121 , the core board 123 and the fourth area 122 together constitute the second area 12 .

[0089] Here, the packaging materials of the third area 121 and the fourth area 122 may be the same. The number of circuit layers in the third area 121 is the same as the number of circuit layers in the fourth area 122.

[0090] The antenna semiconductor package device 2d generated in the second area 12 generated in the above optional implementation manner can be as follows Figure 2D shown.

[0091] refer to Figure 2E In some embodiments, Figure 2D Before setting the second circuit layer on the first surface 12c of the second area as the first area 11, a first buffer layer 13 may be set on the first surface 12c, that is, the third area 121. Then, a second circuit layer is set on the first buffer layer 13 as the first area 11. The antenna semiconductor package device 2e formed can be as follows Figure 2E As shown. As an example, the first buffer layer 13 may be made of the following materials: ABF, PBO, PI or Epoxy.

[0092] In some embodiments, Figure 2D or Figure 2E Before the antenna layer 2 is disposed on the second surface 12d of the second region, a second buffer layer 3 may be disposed on the second surface 12d, that is, the fourth region 122. Then, the antenna layer 2 is disposed on the second buffer layer 3. The antenna semiconductor package device 2f formed may be as shown in FIG. Figure 2F As shown. As an example, the second buffer layer 3 can be made of the following materials: ABF, PBO, PI or Epoxy.

[0093] Here, the first circuit layer, the second circuit layer, the third circuit layer, and the fourth circuit layer may be a redistribution layer (RDL). The first circuit layer, the second circuit layer, the third circuit layer, and the fourth circuit layer may include, for example, gold (Au), silver (Ag), nickel (Ni), copper (Cu), other metals or alloys, or a combination of two or more of the above. The first circuit layer, the second circuit layer, the third circuit layer, and the fourth circuit layer may include conductive wires, and may also include various guide holes, such as through holes, blind holes, and blind vias.

[0094] refer to Figure 2G The first region 11 can also be electrically connected to the RF chip 4. For example, the first region 11 can be electrically connected to the RF chip 4 by wire bonding. In some embodiments, the first region 11 can also be flip-chip soldered to the RF chip 4. The antenna semiconductor package device 2g formed can be as follows: Figure 2G As shown, the antenna semiconductor package device 2g formed can also be Figure 1E The antenna semiconductor package device 1e is the same as or similar to that in FIG.

[0095] Although the present disclosure has been described and illustrated with reference to the specific embodiments of the present disclosure, these descriptions and illustrations do not limit the present disclosure. It is clearly understood by those skilled in the art that various changes can be made, and equivalent elements can be substituted in the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the artistic reproduction in the present disclosure and the actual equipment. There may be other embodiments of the present disclosure that are not specifically described. The specification and drawings should be regarded as illustrative, not restrictive. Modifications may be made to adapt specific situations, materials, material compositions, methods or processes to the goals, spirits and scopes of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations can be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the present disclosure.

Claims

1. An antenna semiconductor packaging device, comprising: The circuit layer has a first area and a second area; an antenna layer, disposed on the second region and away from the first region, wherein the first region and the second region have different packaging materials, the first region and the antenna layer have the same packaging material, and the first region and the antenna layer have the same thickness; A core board is arranged in the second area, and the core board divides the second area into a third area and a fourth area, and the number of circuit layers in the third area is the same as the number of circuit layers in the fourth area; The thickness of the antenna layer is greater than the thickness of the fourth region; The packaging material of the antenna layer is polytetrafluoroethylene, Teflon or polystyrene, the packaging material of the second zone is PP, and the material of the core board is composed of glass fiber and resin.

2. The antenna semiconductor package device according to claim 1, wherein: The antenna semiconductor package device further includes: A first buffer layer is arranged between the first zone and the second zone, wherein the thermal expansion coefficient of the first buffer layer is greater than or equal to the first thermal expansion coefficient and less than or equal to the second thermal expansion coefficient, the first thermal expansion coefficient is the smaller of the thermal expansion coefficient of the packaging material of the first zone and the thermal expansion coefficient of the packaging material of the second zone, and the second thermal expansion coefficient is the larger of the thermal expansion coefficient of the packaging material of the first zone and the thermal expansion coefficient of the packaging material of the second zone.

3. The antenna semiconductor package device according to claim 2, wherein: The antenna semiconductor package device further includes: A second buffer layer is arranged between the second zone and the antenna layer, wherein the thermal expansion coefficient of the second buffer layer is greater than or equal to a third thermal expansion coefficient and less than or equal to a fourth thermal expansion coefficient, the third thermal expansion coefficient is the smaller of the thermal expansion coefficient of the packaging material of the second zone and the thermal expansion coefficient of the packaging material of the antenna layer, and the fourth thermal expansion coefficient is the larger of the thermal expansion coefficient of the packaging material of the second zone and the thermal expansion coefficient of the packaging material of the antenna layer.

4. The antenna semiconductor package device according to claim 1, wherein: The guide hole diameter of the first region is smaller than the guide hole diameter of the second region, and / or the guide hole density of the first region is greater than the guide hole density of the second region.

5. The antenna semiconductor package device according to claim 4, wherein: The dielectric constant of the packaging material of the second zone is greater than the dielectric constant of the packaging material of the first zone and the antenna layer, and / or the dielectric loss of the packaging material of the second zone is greater than the dielectric loss of the packaging material of the first zone and the antenna layer.

6. The antenna semiconductor package device according to claim 3, wherein: The surface roughness of a surface of the first buffer layer close to the second region is less than 1.3 micrometers, and / or the surface roughness of a surface of the second buffer layer close to the second region is less than 1.3 micrometers.

7. A method for manufacturing an antenna semiconductor package device, comprising: Providing a first circuit layer to form a second area, wherein the second area has a first surface and a second surface; A second circuit layer is arranged on the first surface as a first area, wherein the first area and the second area constitute a circuit layer, and wherein the first area and the second area are made of different packaging materials; An antenna layer is disposed on the second surface, the first region and the antenna layer are made of the same packaging material, and the first region and the antenna layer are made of the same thickness; Wherein, providing a first circuit layer to form a second area comprises: Providing a core plate, wherein the core plate has a third surface, a fourth surface, and a through hole, and the through hole of the core plate extends from the third surface to the fourth surface; forming a third circuit layer on the third surface as a third region; Forming a fourth circuit layer on the fourth surface as a fourth area, wherein the number of circuit layers in the third area is the same as the number of circuit layers in the fourth area, and the third area, the core board and the fourth area form the second area; The thickness of the antenna layer is greater than the thickness of the fourth region; The packaging material of the antenna layer is polytetrafluoroethylene, Teflon or polystyrene, the packaging material of the second zone is PP, and the material of the core board is composed of glass fiber and resin.

8. The method for manufacturing an antenna semiconductor package device according to claim 7, wherein: Before providing the antenna layer on the second surface, the method further includes: Disposing a second buffer layer on the second surface of the second region; and An antenna layer is disposed on the second buffer layer.

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