A broadband high-efficiency power amplifier based on a terminated coupled line structure and a design method thereof

Abstract

The present invention discloses a broadband high-efficiency power amplifier based on a terminated coupled line structure and a design method thereof, comprising an input matching network, a gate DC feeding network, a transistor, a drain DC feeding network and an output matching network. Compared with the prior art, the present invention proposes a new output matching network topology structure, and the cascaded terminated coupled line structure is used to design the output matching network of the power amplifier. By selecting different terminal impedance conditions at the four ports of the coupled microstrip line, the terminated coupled line can not only realize impedance transformation, but also control the harmonic impedance, thereby improving the efficiency of the designed power amplifier, and utilizing two sections of coupled lines in cascade to expand the bandwidth of the designed power amplifier. Compared with the traditional design method, there is no need to design the harmonic control circuit and the fundamental matching circuit separately, thereby simplifying the design of the power amplifier while maintaining high efficiency performance.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technology, and in particular to a broadband high-efficiency power amplifier based on a terminated coupled line structure and a design method thereof. Background Art

[0002] With the rapid development of wireless communication technology, the requirements for RF front-end circuits are getting higher and higher. As a key module in the RF front-end circuit, the performance and characteristics of the power amplifier have an extremely important impact on the entire wireless communication system. In particular, the advent of 5G communication has put forward higher requirements on the bandwidth of the wireless communication system. As an important part of the wireless communication system, the bandwidth characteristics of the power amplifier have become an important indicator for measuring the power amplifier. The power amplifier is also the most energy-consuming part of the wireless communication system. It has an important impact on the energy consumption of the entire system, the working time of the equipment, and the pressure of the heat dissipation device. Therefore, the efficiency of the power amplifier is also another important indicator for measuring the power amplifier. Therefore, how to design a power amplifier with a wide bandwidth while maintaining high efficiency has become a hot issue in the field of wireless communication technology today.

[0003] However, in the design of power amplifiers, the designed power amplifiers usually have high efficiency but narrow bandwidth, or have wide bandwidth but low efficiency. In existing designs, most of them first use a harmonic control network to control harmonics, and then match them through a fundamental matching network. This design method increases the complexity of circuit design to a certain extent, and the volume is large and the cost is high.

[0004] Therefore, in view of the above-mentioned defects, it is necessary to conduct research to provide a broadband and high-efficiency power amplifier design solution with better performance to solve the defects in the prior art. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide a broadband high-efficiency power amplifier based on a terminated coupled line structure and a design method thereof, and a new output matching network topology is proposed. The cascaded terminated coupled line is used as the output matching network of the power amplifier. By selecting different terminal impedance conditions at the four ports of the coupled line, not only impedance transformation can be achieved, but also harmonic control can be achieved. At the same time, two sections of coupled microstrip lines are cascaded to expand the working bandwidth of the power amplifier. Compared with traditional power amplifiers, this output matching network has a simple structure and is easy to implement. There is no need to design harmonic control circuits and fundamental matching circuits separately. While achieving high performance, the complexity of circuit design is greatly simplified, and the volume of the circuit is further reduced, reducing production costs.

[0006] In order to overcome the defects of the prior art, the present invention adopts the following technical solutions:

[0007] A broadband high-efficiency power amplifier based on a terminated coupled line structure comprises an input matching network, a gate DC feeding network, a transistor, a drain DC feeding network and an output matching network, wherein:

[0008] The input matching network is connected to the input end of the transistor, matching the 50 ohm impedance to the conjugate of the optimal source impedance obtained by the transistor through source pulling, so that the power amplifier obtains the maximum input power;

[0009] The gate DC feeding network and the drain DC feeding network are connected to the gate and drain of the transistor respectively, and voltage is applied to the gate and drain of the transistor to block the RF signal from flowing into the power supply and set the static operating point;

[0010] The transistor is used to amplify the input signal;

[0011] The output matching network is connected to the output end of the transistor and is used to match the optimal output impedance obtained by the transistor load pulling to 50 ohms, so that the power amplifier can achieve maximum efficiency transmission. The output matching network not only has the function of impedance matching, but also has the function of suppressing harmonics.

[0012] The output matching network is a network topology of a terminated coupled line cascade structure, including a first parallel open transmission line TL9, a second parallel open transmission line TL10, a third parallel open transmission line TL11, a fourth parallel open transmission line TL12, a first parallel coupled line CLin1 and a second parallel coupled line CLin2, wherein the first parallel open transmission line TL9 is connected to the 2nd port of the first parallel coupled line CLin1, the 3rd port of the first parallel coupled line CLin1 is connected to the 2nd port of the second parallel coupled line CLin2 and the second parallel open transmission line TL10, the 4th port of the first parallel coupled line CLin1 is connected to the 1st port of the second parallel coupled line CLin2 and the third parallel open transmission line TL11. The second parallel open transmission line TL10 is connected to the 3-port of the first parallel coupling line CLin1 and the 2-port of the second parallel coupling line CLin2, the third parallel open transmission line TL11 is connected to the 4-port of the first parallel coupling line CLin1 and the 1-port of the second parallel coupling line CLin2, the 2-port of the second parallel coupling line CLin2 is connected to the 3-port of the first parallel coupling line CLin1 and the second parallel open transmission line TL10, the 1-port of the second parallel coupling line CLin2 is connected to the 4-port of the first parallel coupling line CLin1 and the third parallel open transmission line TL11, and the fourth parallel open transmission line TL12 is connected to the 3-port of the second parallel coupling line CLin2 as a load end.

[0013] As a further improvement scheme, the input matching network includes a DC blocking capacitor C1, a first series transmission line TL1, a second series transmission line TL2, a third series transmission line TL3, a fourth series transmission line TL5 and an RC parallel stabilization circuit, wherein one end of the DC blocking capacitor C1 is connected to the input end of the RF source, the other end of the DC blocking capacitor C1 is connected to one end of the first series transmission line TL1, the other end of the first series transmission line TL1 is connected to one end of the second series transmission line TL2, the other end of the second series transmission line TL2 is connected to one end of the RC parallel stabilization circuit, the other end of the RC parallel stabilization circuit is connected to one end of the third series transmission line TL 3, the other end of the third series transmission line TL 3 is connected to one end of the fourth series transmission line TL 5, and the other end of the fourth series transmission line is connected to the input end of the transistor.

[0014] As a further improvement, the gate DC feeding network includes a microstrip transmission line TL4, a stabilizing resistor R2 and a coupling capacitor C3, wherein one end of the microstrip transmission line is connected to a power supply and one end of the capacitor C3, the other end of the capacitor C3 is grounded, the other end of the microstrip transmission line TL4 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to the input end of the transistor, and the bias voltage of the gate DC feeding network is -2.8V; the drain DC feeding network includes a microstrip transmission line TL7 and a capacitor C4, wherein one end of the microstrip transmission line TL7 is connected to a power supply and one end of the capacitor C4, one end of the capacitor C4 is grounded, the other end of the microstrip transmission line TL7 is connected to the output end of the transistor, and the bias voltage of the drain DC feeding network is 28V.

[0015] As a further improvement, the output matching network is a symmetrical matching network formed by loading open-circuit stubs on different ports of the coupling lines and then cascading the coupling lines.

[0016] As a further improvement, the transistor adopts a GaN HEMT CGH40010F transistor.

[0017] In order to solve the technical problems existing in the prior art, the present invention also discloses a design method of a broadband high-efficiency power amplifier based on a terminated coupled line structure, which is implemented by the following steps:

[0018] Step S1: performing source pulling and load pulling on the gate and drain of the transistor at the center frequency to obtain an optimal source impedance and an optimal load impedance;

[0019] Step S2: According to the optimal source impedance obtained in step S1, a step impedance matching method is used to achieve conjugate matching from the input port to the optimal source impedance, and an input matching network is designed;

[0020] Step S3: designing a bias circuit using a quarter-wavelength transmission line;

[0021] Step S4: designing an output filter matching network according to the optimal load impedance obtained in step S1; wherein two sections of parallel coupled microstrip lines are cascaded to expand the working bandwidth, and four open short stubs TL9, TL10, TL11, and TL12 are loaded on different port branches of the parallel coupled microstrip lines to form an output filter matching network;

[0022] Step S5: Build the designed modules into an integrated circuit.

[0023] Compared with the prior art, the present invention has the following technical effects:

[0024] The present invention adopts a novel output matching network structure topology, utilizes coupled line cascade to expand the bandwidth of the designed power amplifier, and by loading open-circuit stubs at different port branches of the coupled line, not only impedance matching can be achieved, but also harmonics can be controlled, which can improve the efficiency of the power amplifier. There is no need to design harmonic control circuits and fundamental matching circuits separately, which greatly simplifies the complexity of circuit design, and the designed output matching network is a symmetrical structure, which simplifies the structure and process, and also further reduces the volume of the circuit, reduces the production cost, and has a good application prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the structure of a broadband high-efficiency power amplifier based on a terminated coupled line structure of the present invention;

[0026] Figure 2 It is a schematic diagram of the input matching network and the gate DC feeding network in the present invention;

[0027] Figure 3 It is a topological structure diagram of the cascaded terminated coupled line output matching network in the present invention;

[0028] Figure 4 It is a schematic diagram of the conventional coupled microstrip line structure;

[0029] Figure 5a The present invention is for Figure 3 The odd-mode equivalent circuit schematic diagram of the output matching network topology;

[0030] Figure 5b The present invention is for Figure 3 Even-mode equivalent circuit schematic diagram of the output matching network topology;

[0031] Figure 6 It is a schematic diagram of the S parameter simulation results of the output matching network filtering of the present invention;

[0032] Figure 7It is a diagram of the output power, efficiency and gain simulation results of the broadband high-efficiency power amplifier based on the terminated coupled line structure of the present invention. DETAILED DESCRIPTION

[0033] The following are specific embodiments of the present invention and the accompanying drawings to further describe the technical solution of the present invention, but the present invention is not limited to these embodiments.

[0034] In view of the defects of the prior art, the applicant has conducted an in-depth study on the structure of the traditional broadband high-efficiency power amplifier in the prior art. The applicant found in the study that the output matching circuit of the traditional broadband high-efficiency power amplifier in the prior art generally designs the harmonic control circuit first, and then designs the fundamental matching circuit on this basis. This design method not only increases the complexity of the design process and structure, but also has a large overall volume after the design is completed, which is not conducive to miniaturized design and has a relatively high cost.

[0035] In order to solve the defects of the prior art, the present invention proposes a broadband and high-efficiency power amplifier based on a terminated coupled line structure and a design method thereof, which utilizes coupled line cascading to expand the bandwidth of the designed power amplifier, and loads open-circuit stubs at different port branches of the coupled line, which can not only achieve impedance matching but also control harmonics.

[0036] See also Figure 1 , which is a schematic diagram of the structure of a broadband high-efficiency power amplifier based on a terminated coupled line structure of the present invention, including an input matching network, a gate DC feeding network, a transistor, a drain DC feeding network and an output matching network, wherein,

[0037] The input matching network is connected to the input end of the transistor, matching the 50 ohm impedance to the conjugate of the optimal source impedance obtained by the transistor through source pulling, so that the power amplifier obtains the maximum input power;

[0038] The gate DC feeding network and the drain DC feeding network are connected to the gate and drain of the transistor respectively, and voltage is applied to the gate and drain of the transistor to block the RF signal from flowing into the power supply and set the static operating point;

[0039] The output matching network is connected to the output end of the transistor and is used to match the optimal output impedance obtained by the transistor load pulling to 50 ohms, so that the power amplifier can achieve maximum efficiency transmission. The output matching network not only has the function of impedance matching, but also has the function of suppressing harmonics.

[0040] See also Figure 2, shown is a principle block diagram of an input matching network, including a DC blocking capacitor C1, a first series transmission line TL1, a second series transmission line TL2, a third series transmission line TL3, a fourth series transmission line TL5 and an RC parallel stabilization circuit, wherein one end of the DC blocking capacitor C1 is connected to the input end of the RF source, the other end of the DC blocking capacitor C1 is connected to one end of the first series transmission line TL1, the other end of the first series transmission line TL1 is connected to one end of the second series transmission line TL2, the other end of the second series transmission line TL2 is connected to one end of the RC parallel stabilization circuit, the other end of the RC parallel stabilization circuit is connected to one end of the third series transmission line TL3, the other end of the third series transmission line TL3 is connected to one end of the fourth series transmission line TL5, and the other end of the fourth series transmission line is connected to the input end of the transistor.

[0041] See also Figure 3 , which is a schematic diagram of the topological structure of the output matching network, and the matching of the circuit is achieved through the cascade termination coupling line structure. It includes a first parallel open transmission line TL9, a second parallel open transmission line TL10, a third parallel open transmission line TL11, a fourth parallel open transmission line TL12, a first parallel coupling line CLin1 and a second parallel coupling line CLin2, wherein the first parallel open transmission line TL9 is connected to the 2nd port of the first parallel coupling line CLin1, the 3rd port of the first parallel coupling line CLin1 is connected to the 2nd port of the second parallel coupling line CLin2 and the second parallel open transmission line TL10, the 4th port of the first parallel coupling line CLin1 is connected to the 1st port of the second parallel coupling line CLin2 and the third parallel open transmission line TL11, and the second parallel open transmission line CLin2 is connected to the 4th port of the first parallel coupling line CLin1. L10 is connected to port 3 of the first parallel coupling line CLin1 and port 2 of the second parallel coupling line CLin2, the third parallel open transmission line TL11 is connected to port 4 of the first parallel coupling line CLin1 and port 1 of the second parallel coupling line CLin2, port 2 of the second parallel coupling line CLin2 is connected to port 3 of the first parallel coupling line CLin1 and the second parallel open transmission line TL10, port 1 of the second parallel coupling line CLin2 is connected to port 4 of the first parallel coupling line CLin1 and the third parallel open transmission line TL11, and the fourth parallel open transmission line TL12 is connected to port 3 of the second parallel coupling line CLin2 as a load end.

[0042] The above-mentioned output matching network topology structure is a symmetrical terminated coupled line structure. The working principle of the technical solution of the present invention is further explained below.

[0043] To further simplify the analysis, the symmetrical output matching network is subjected to even-odd mode analysis. Figure 4, which is a schematic diagram of the structure of a conventional coupled microstrip line. Since it has four lead-out terminals, 1, 2, 3, and 4, it belongs to a four-port network. The odd and even mode parameters of the coupled microstrip line can be expressed by the following formula:

[0044]

[0045]

[0046] in, and are the odd-mode and even-mode characteristic impedances of the air-coupled microstrip line, respectively, and ε eo and ε ee are the effective dielectric constants of the odd and even modes of the medium, respectively. From the above two equations, we can see that we only need to obtain ε eo and ε ee In ε r The corresponding change value when the change occurs can be obtained by 0o and Z 0e value.

[0047] Parameter Z 0o , Z 0e are the characteristic impedances of the odd and even modes of the coupled microstrip line, respectively, and θ is its electrical length. The four-port impedance matrix of the conventional coupled microstrip line structure can be expressed as:

[0048]

[0049] Where V m and I n (m,n=1,2,3,4) respectively Figure 4 The voltage and current at the four ports of the conventional coupled line, Condition i k＝0 This corresponds to the kth port being open. What is obtained is not a normalized impedance matrix, but a dimensioned impedance matrix, in which each element has a unit of Ω.

[0050]

[0051]

[0052]

[0053]

[0054] After calculating the parameters of the four-port network of coupled microstrip lines, the characteristics of many unit circuits can be obtained on this basis. In addition to using the coupled microstrip directional coupler as a four-port element, it is generally used as a filter circuit unit; at this time, the other two ports are often short-circuited or open-circuited, so that only two ports are connected to other circuits, which actually becomes a two-port network.

[0055] See also Figure 5a , shown is the odd-mode equivalent circuit schematic diagram of the output matching network. Under the odd-mode excitation state, the input impedance expression of the odd-mode equivalent circuit on the symmetric plane is as follows:

[0056] Z ino =Z 11 +Z 12 (8)

[0057] in:

[0058]

[0059]

[0060] Z od ,Z en are the odd-mode and even-mode characteristic impedances of the coupled lines CLin1 and CLin2, respectively, θ is its electrical length, and Z 1 ,θ 1 are the characteristic impedance and electrical length of transmission lines TL9 and TL12.

[0061] See also Figure 5b , shown is the schematic diagram of the even-mode equivalent circuit of the output matching network. Under the even-mode excitation state, the input impedance expression of the even-mode equivalent circuit in the symmetric plane is as follows:

[0062] Z ine =Z 22 +Z 23 (11)

[0063] in:

[0064]

[0065]

[0066] Z 1 ,θ 1 is the characteristic impedance and electrical length of transmission lines TL9 and TL12, Z 2 ,θ 2 are the characteristic impedance and electrical length of transmission lines TL10 and TL11 respectively. Then the input impedance of the odd-even mode equivalent circuit is introduced into the scattering parameter, and the expression of the scattering parameter can be obtained as follows:

[0067]

[0068]

[0069] Where Z in It is represented as the input impedance of the output matching network. Based on the above expression, the external scattering parameters of the terminated coupled line structure can be calculated and analyzed, and the filtering performance parameters within the working frequency band are determined by the above formula. Figure 6 The figure is a schematic diagram of the S-parameter simulation results of the output matching network filtering. From the S-parameter simulation results, it can be seen that the matching network suppresses the second harmonic by at least 23dB, showing good filtering characteristics.

[0070] See also Figure 7 , shown is the output power, efficiency and gain simulation result diagram of the broadband high-efficiency power amplifier based on the terminated coupled line structure of the present invention. The designed power amplifier operates in the 1.2-3.6GHz frequency band, with a saturated output power of 40-42dBm, a gain greater than 10dB, and a drain efficiency between 63% and 76%, showing good performance indicators.

[0071] In a preferred embodiment, a GaN HEMT CGH40010F transistor from Cree is used;

[0072] In a preferred embodiment, a gate bias circuit is provided between the designed input matching network and the transistor, and its bias voltage is set to -2.8V;

[0073] In a preferred embodiment, a drain bias circuit is provided between the transistor and the designed output matching network, and its bias voltage is set to 28V;

[0074] The design method of the broadband high-efficiency power amplifier based on the terminated coupled line structure of the present invention is implemented by the following steps:

[0075] Step S1: firstly perform source pulling and load pulling on the gate and drain of the transistor at the center frequency to obtain the optimal source impedance and the optimal load impedance;

[0076] Step S2: According to the optimal source impedance obtained in step S1, a step impedance matching method is used to achieve conjugate matching from the input port to the optimal source impedance, and an input matching network is designed;

[0077] Step S3: designing a bias circuit module using a quarter-wavelength transmission line;

[0078] Step S4: Design an output filter matching network based on the optimal load impedance obtained in step S1. By cascading the amplifier and the filter matching network, a filter response can be obtained between different input impedance points and a fixed output impedance of 50Ω. In this way, the impedance mismatch caused by the interconnection line between the transistor drain node and the filter matching network input port can be minimized. The designed output filter matching network is shown in FIG. Figure 3 As shown in FIG. 5 , two parallel coupled microstrip lines are cascaded to expand the working bandwidth, and four open short stubs TL9, TL10, TL11, and TL12 are loaded on different port branches of the parallel coupled microstrip lines to form an output filter matching network. Loading open short stubs on the branches can increase the transmission zero of the filter matching network, improve its selectivity, and obtain a better out-of-band suppression level. FIG. 5 shows the odd-even mode equivalent circuit diagram of the output filter matching network, and the input impedance of the odd-even mode equivalent circuit is:

[0079] Z ino =Z 11 +Z 12 (16)

[0080] Z ine =Z 22 +Z 23 (17)

[0081] in:

[0082]

[0083]

[0084]

[0085]

[0086] Z od ,Z en are the odd-mode and even-mode characteristic impedances of the coupled lines CLin1 and CLin2, respectively, θ is its electrical length, and Z 1 ,θ 1 is the characteristic impedance and electrical length of transmission lines TL9 and TL12, Z 2 ,θ 2 are the characteristic impedance and electrical length of transmission lines TL10 and TL11 respectively. Introducing the input impedance of the odd-mode and even-mode equivalent circuit into the scattering parameter, the expression of the scattering parameter can be obtained as follows:

[0087]

[0088]

[0089] Where Z inIt is represented as the input impedance of the output matching network. Based on the above expression, the external scattering parameters of the terminated coupled line structure can be calculated and analyzed, and the filtering performance parameters within the working frequency band are determined by the above formula. Figure 6 The figure is a schematic diagram of the S-parameter simulation results of the output matching network filtering. From the S-parameter simulation results, it can be seen that the matching network suppresses the second harmonic by at least 23dB, showing good filtering characteristics.

[0090] Step S5: construct the designed modules into an integral circuit, simulate and debug the constructed integral circuit, optimize the integral circuit according to the simulation results, and further improve the performance of the designed power amplifier.

[0091] See also Figure 7 , shown is the output power, efficiency and gain simulation result diagram of the broadband high-efficiency power amplifier based on the terminated coupled line structure of the present invention. The designed power amplifier operates in the 1.2-3.6GHz frequency band, with a saturated output power of 40-42dBm, a gain greater than 10dB, and a drain efficiency between 63% and 76%, showing good performance indicators.

[0092] The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present invention, the present invention can also be improved and modified in a number of ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention. It is obvious to those skilled in the art that various modifications to these embodiments can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown in the present application, but will conform to the widest range consistent with the principles and novel features disclosed in the present application.

Claims

1. A broadband high-efficiency power amplifier based on a terminated coupled line structure, characterized in that: At least includes an input matching network, a gate DC feeding network, a transistor, a drain DC feeding network and an output matching network, wherein: The input matching network is connected to the input end of the transistor and is used to match the 50 ohm impedance to the conjugate of the optimal source impedance obtained by the transistor through source pulling, so that the power amplifier obtains the maximum input power; The gate DC feeding network and the drain DC feeding network are connected to the gate and drain of the transistor respectively, and are used to block the RF signal from flowing into the power supply and set the static operating point; The transistor is used to amplify the input signal; The output matching network is connected to the output end of the transistor and is used to match the optimal output impedance obtained by the transistor load pulling to 50 ohms, so that the power amplifier can achieve maximum efficiency transmission. The output matching network not only has the function of impedance matching, but also has the function of suppressing harmonics. It adopts the network topology of the terminated coupled line cascade structure, including a first parallel open transmission line TL9, a second parallel open transmission line TL10, a third parallel open transmission line TL11, a fourth parallel open transmission line TL12, a first parallel coupled line CLin1 and a second parallel coupled line CLin2, wherein the first parallel open transmission line TL9 is connected to the 2-port of the first parallel coupled line CLin1 as an input end, the 3-port of the first parallel coupled line CLin1 is connected to the 2-port of the second parallel coupled line CLin2 and the second parallel open transmission line TL10, the 4-port of the first parallel coupled line CLin1 is connected to the 1-port of the second parallel coupled line CLin2 and the third parallel open transmission line TL11, and the fourth parallel open transmission line TL12 is connected to the 3-port of the second parallel coupled line CLin2 as a load end; The input matching network includes a DC blocking capacitor C1, a first series transmission line TL1, a second series transmission line TL2, a third series transmission line TL3, a fourth series transmission line TL5 and an RC parallel stabilization circuit, wherein one end of the DC blocking capacitor C1 is connected to the input end of the RF source, the other end of the DC blocking capacitor C1 is connected to one end of the first series transmission line TL1, the other end of the first series transmission line TL1 is connected to one end of the second series transmission line TL2, the other end of the second series transmission line TL2 is connected to one end of the RC parallel stabilization circuit, the other end of the RC parallel stabilization circuit is connected to one end of the third series transmission line TL3, the other end of the third series transmission line TL3 is connected to one end of the fourth series transmission line TL5, and the other end of the fourth series transmission line is connected to the input end of the transistor; The gate DC feeding network includes a microstrip transmission line TL4, a stabilizing resistor R2 and a coupling capacitor C3, wherein one end of the microstrip transmission line is connected to a power supply and one end of the capacitor C3, the other end of the capacitor C3 is grounded, the other end of the microstrip transmission line TL4 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to the input end of the transistor, and the bias voltage of the gate DC feeding network is -2.8V; the drain DC feeding network includes a microstrip transmission line TL7 and a capacitor C4, wherein one end of the microstrip transmission line TL7 is connected to a power supply and one end of the capacitor C4, one end of the capacitor C4 is grounded, and the other end of the microstrip transmission line TL7 is connected to the output end of the transistor.

2. The broadband high-efficiency power amplifier based on the terminated coupled line structure according to claim 1, characterized in that: The output matching network is a symmetrical matching network formed by loading open-circuit stubs on different ports of coupling lines and then cascading the coupling lines.

3. The broadband high-efficiency power amplifier based on a terminated coupled line structure according to claim 1, characterized in that: The transistor adopts a GaN HEMT CGH40010F transistor.

4. The method for designing a broadband high-efficiency power amplifier based on a terminated coupled line structure according to any one of claims 1 to 3, characterized in that: This is accomplished by the following steps: Step S1: performing source pulling and load pulling on the gate and drain of the transistor at the center frequency to obtain an optimal source impedance and an optimal load impedance; Step S2: According to the optimal source impedance obtained in step S1, a step impedance matching method is used to achieve conjugate matching from the input port to the optimal source impedance, and an input matching network is designed; Step S3: designing a bias circuit using a quarter-wavelength transmission line; Step S4: designing an output filter matching network according to the optimal load impedance obtained in step S1; wherein two sections of parallel coupled microstrip lines are cascaded to expand the working bandwidth, and four open short stubs TL9, TL10, TL11, and TL12 are loaded on different port branches of the parallel coupled microstrip lines to form an output filter matching network; Step S5: Build the designed modules into an integrated circuit.

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