Circuit module and power chip module

Abstract

The present invention provides a circuit module and a power chip module, which can suppress the increase of the wiring layer of the mounting substrate and can appropriately connect the power supply source and the supply object. The circuit module (80) comprises a power chip module (10), a load chip module (20) and a system substrate (30). The power output terminal group (11) of the power chip module (10) is arranged in a column along at least one side of the power chip module substrate (21), and the power input terminal group (31) of the load chip module (20) comprises a specific terminal group (31S), and the specific terminal group (31S) is arranged in a specific column (SG) along at least one side of the load chip module substrate (21), so that the wiring width (W11) of the wiring pattern (41) connecting the power output terminal group (11) and the system substrate (30) along the arrangement direction of the power output terminal group (11) is greater than the wiring width (W31) of the wiring pattern (41) connecting the specific terminal group (31S) and the system substrate (30) along the arrangement direction of the specific terminal group (31S).

Description

Technical Field

[0001] The present invention relates to a circuit module having a power chip module, a load chip module, a system substrate supporting the power chip module and the load chip module, and the power chip module. Background Art

[0002] Japanese Patent Publication No. 2014-82245 discloses a semiconductor storage device having a controller (201) and a power supply IC (202) (the reference numerals in brackets in the background art are from the reference document). The power supply IC (202) generates a plurality of different power supply voltages and supplies them to the controller (201). Among the terminals of the controller (201), the amount of current flowing in the power supply terminal for input and output of power is larger than that in the signal terminal for input and output of signals. Therefore, in many cases, a plurality of terminals are allocated to the power supply terminal corresponding to one power supply.

[0003] When the terminals are arranged in a rectangular ring shape by a BGA (Ball Grid Array) or the like, a plurality of power supply terminals corresponding to one power supply are arranged side by side from the center toward the outer periphery.

[0004] In addition, on the mounting substrate, the amount of current flowing in the conductive wiring pattern is larger than that in the wiring pattern for transmitting signals. Therefore, the wiring pattern for the power supply is usually formed to be larger than the wiring pattern for the signal (the effective cross-sectional area becomes larger). However, in the case where multiple power terminals corresponding to one power supply are arranged from the center of the power IC (202) to the outer periphery, in order to ensure the insulation of the terminals adjacent to the circumference, it is difficult to expand the wiring pattern in the direction along the surface of the mounting substrate. Therefore, in most cases, the mounting substrate is used as a multi-layer substrate, and the inner layer is used to ensure the effective cross-sectional area of ​​the wiring pattern of the power supply. The more the number of layers of the multi-layer substrate increases, the higher the production cost. Therefore, it is preferable to suppress the increase of the power wiring layer of the mounting substrate to connect load electronic components such as the controller (201) and power supply electronic components such as the power IC (202).

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2014-82245 Summary of the invention

[0008] Problem that the invention aims to solve

[0009] In view of the above background, it is desirable to provide a technology capable of appropriately connecting a power supply source and a supply target while suppressing an increase in the number of wiring layers of a mounting substrate.

[0010] Means used to solve problems

[0011] In view of the above problems, a circuit module of one embodiment has a power chip module, a load chip module and a system substrate, wherein the power chip module has: a rectangular plate-shaped power chip module substrate; at least one power semiconductor chip supported by the upper surface of the power chip module substrate; a plurality of connection terminals arranged in a plurality of rows of rectangular rings along the sides of the power chip module substrate on the lower surface of the power chip module substrate and electrically connected to the power semiconductor chip, and the load chip module has: a rectangular plate-shaped load chip module substrate; at least one load semiconductor chip supported by the upper surface of the load chip module substrate; a plurality of load-side connection terminals arranged in a plurality of rows of rectangular rings along the sides of the load chip module substrate on the lower surface of the load chip module substrate and electrically connected to the load semiconductor chip , the system substrate supports the power chip module and the load chip module, wherein the plurality of connection terminals include a power output terminal group having a plurality of terminals, the plurality of load-side connection terminals include a power input terminal group having a plurality of terminals connected to the power output terminal group, the power output terminal group is arranged in a column along at least one side of the power chip module substrate, the power input terminal group has a specific terminal group, the specific terminal group is arranged in a column along at least one side of the load chip module substrate, i.e., a specific column, and the wiring width of the wiring pattern connecting the power output terminal group to the system substrate along the arrangement direction of the power output terminal group is greater than the wiring width of the wiring pattern connecting the specific terminal group to the system substrate in the specific column along the arrangement direction of the specific terminal group.

[0012] An appropriate number of power input terminal groups are provided on the load chip module according to the current consumption of the load chip module. On the other hand, an appropriate number of power output terminal groups are provided on the power chip module so that the power chip module can output the maximum current within the output range. As a matter of course, a power chip module with a specification that can sufficiently supply current even when the current consumption of the load chip module is the maximum is used. In other words, the maximum value of the current consumption of the load chip module is less than the maximum value of the output current of the power chip module. Therefore, the effective cross-sectional area of ​​the wiring connected to the power input terminal group can be smaller than the effective cross-sectional area of ​​the wiring connected to the power output terminal group. According to this structure, the wiring width of the wiring pattern connected to the power output terminal group is greater than the wiring width of the wiring pattern connected to the power input terminal group. Therefore, the power chip module and the load chip module can be appropriately connected.

[0013] In addition, in view of the above problems, a power chip module of one embodiment comprises: a rectangular plate-shaped power chip module substrate; at least one power semiconductor chip supported by the upper surface of the power chip module substrate; a plurality of connecting terminals arranged in a plurality of rows of rectangular rings along the sides of the power chip module substrate on the lower surface of the power chip module substrate, and electrically connected to the power semiconductor chip, wherein the plurality of connecting terminals include: a first power output terminal group having a plurality of terminals for outputting a first voltage; a second power output terminal group having a plurality of terminals for outputting a second voltage, the first power output terminal group and the second power output terminal group One of the two power output terminal groups is arranged in an outermost column along at least one side of the power chip module substrate, namely, an outermost column; the other of the first power output terminal group and the second power output terminal group is arranged in an inner column than the outermost column along the arrangement direction of the power output terminal groups in the outermost column, namely, an inner column; when viewed from a direction along the power chip module substrate and orthogonal to the arrangement direction, a first area where the first power output terminal group is arranged and a second area where the second power output terminal group is arranged at least partially overlap.

[0014] According to this structure, the power output terminal group arranged in the outermost column and the power supply object can be connected by the surface wiring formed on the mounting surface of the substrate on which the power chip module is mounted. In addition, the power output terminal group arranged in the outermost column is adjacent to the circumference of the connection terminal arranged in a rectangular ring, so it is possible to set the surface wiring with sufficient wiring width and suppress the wiring impedance in the direction along the arrangement direction. When viewed from a direction orthogonal to the arrangement direction, the power output terminal group arranged in the inner column overlaps at least a part of the power output terminal group arranged in the outermost column, so as described above, it is difficult to connect to the power supply object through the surface wiring of the mounting surface. However, by setting the wiring on another wiring layer other than the surface wiring of the mounting surface of the substrate, it is possible to connect to the power supply object appropriately. That is, it is possible to ensure sufficient wiring width in the surface direction of the substrate on which the power chip module is mounted, so that it is possible to ensure sufficient effective cross-sectional area of ​​the wiring, so that it is not necessary to expand the effective cross-sectional area of ​​the wiring in the thickness direction of the substrate. Therefore, it is possible to suppress the increase of the wiring layer (inner wiring layer) of the substrate. As described above, according to this structure, it is possible to appropriately connect the power supply source and the supply target while suppressing the increase in the wiring layers of the mounting substrate.

[0015] Further features and advantages of the power chip module and the circuit module will become apparent from the following description of the embodiments (of the present invention) explained with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the circuit module.

[0017] Figure 2 This is a schematic perspective view showing an example of the terminal arrangement of the power chip module.

[0018] Figure 3 It is a schematic perspective view showing an example of the terminal arrangement of the load chip module.

[0019] Figure 4 It is a schematic cross-sectional view showing the structure of a power chip module and a load chip module.

[0020] Figure 5 It is a schematic cross-sectional view showing the structure of a power chip module and a load chip module.

[0021] Figure 6 This is an explanatory diagram showing the terminal structure of the power chip module and the load chip module.

[0022] Figure 7 This is a diagram schematically showing an example of a wiring pattern of power supply wiring on the first surface of the system substrate.

[0023] Figure 8 This is a diagram schematically showing an example of a wiring pattern of power supply wiring on the second surface of the system substrate.

[0024] Fig. 9 It is a cross-sectional view schematically showing an example of a wiring pattern of a power supply wiring of a system substrate.

[0025] Fig.10 It is a schematic perspective view showing another example of the terminal arrangement of the power chip module.

[0026] Fig.11 It is a cross-sectional view schematically showing another example of the wiring pattern of the power supply wiring of the system substrate.

[0027] Fig.12 It is a cross-sectional view schematically showing an example of a wiring pattern of a power supply wiring using an inner wiring layer.

[0028] Fig.13 It is a cross-sectional view schematically showing an example of a wiring pattern of a power supply wiring of one system.

[0029] Fig.14 It is a cross-sectional view schematically showing another example of the wiring pattern of the power supply wiring of one system.

[0030] Fig.15 This is a diagram schematically showing another example of the wiring pattern of the power supply wiring on the first surface of the system substrate.

[0031] Fig.16 It is a diagram schematically showing a comparative example of the wiring pattern of the power supply wiring on the first surface of the system substrate. DETAILED DESCRIPTION

[0032] Next, an embodiment of a circuit module is described with reference to the accompanying drawings. The circuit module includes a power chip module that is a power supply source, and a load chip module that is a power supply target of the power chip module and the power supply target. Figure 1 As shown, the circuit module 80 includes a power chip module 10, a load chip module 20, and a system substrate 30 as a mounting substrate, and the system substrate 30 supports the power chip module 10 and the load chip module 20. The load chip module 20 is connected to the power chip module 10 and is supplied with power from the power chip module 10. Figure 1 The first surface 30a of the system substrate supports the power chip module 10 and the load chip module 20, and a first power wiring pattern 41 (first wiring pattern) is formed on the first surface 30a of the system substrate. Fig. 9 As shown, a second power supply wiring pattern 42 (second wiring pattern) is formed on the second surface 30b of the system substrate.

[0033] Hereinafter, the direction perpendicular to the system substrate 30 as viewed from the first surface 30a of the system substrate is referred to as the "Z direction", the direction in which the power chip module 10 and the load chip module 20 are arranged along the substrate surface of the system substrate 30 is referred to as the "Y direction", and the direction perpendicular to the "Z direction" and the "Y direction" is referred to as the "X direction". In addition, Figure 2 , Figure 3 From Figure 1 The perspective view viewed in the Z direction in FIG. 1 shows the arrangement of the connection terminals 3 of the power chip module 10 and the load-side connection terminals 23 of the load chip module 20 .

[0034] like Figure 4 As shown, the power chip module 10 comprises: a rectangular plate-shaped power chip module substrate 1; at least one power semiconductor chip 2 supported by the upper surface 1a of the power chip module substrate 1; and a plurality of connection terminals 3 arranged on the lower surface 1b of the power chip module substrate 1 and electrically connected to the power semiconductor chip 2. Figure 2 As shown, the connection terminals 3 are arranged in a plurality of rows of rectangular rings along each side of the power chip module substrate 1 .

[0035] Similarly, the load chip module 20 comprises: a rectangular plate-shaped load chip module substrate 21; at least one load semiconductor chip 22 supported by the upper surface 21a of the load chip module substrate 21; and a plurality of load-side connection terminals 23 disposed on the lower surface 21b of the load chip module substrate 21 and electrically connected to the load semiconductor chip 22. Figure 3 As shown, the load-side connection terminals 23 are also arranged in a rectangular ring shape in multiple rows along each side of the load chip module substrate 21 .

[0036] like Figure 2 As shown, the multiple connection terminals 3 of the power chip module 10 include: a first power output terminal group 11, having multiple terminals for outputting a first voltage; a second power output terminal group 12, having multiple terminals for outputting a second voltage. In addition, the first voltage and the second voltage can be different voltages or the same voltage. The current that the second power output terminal group 12 can output from the power chip module 10 is greater than the current that the first power output terminal group 11 can output from the power chip module 10, so more connection terminals 3 are allocated to the second power output terminal group 12. Here, an example is given of allocating three connection terminals 3 to the first power output terminal group 11 and six connection terminals 3 to the second power output terminal group 12.

[0037] In this example, the first power output terminal group 11 is arranged on the outermost column G1, which is the outermost column along at least one side of the power chip module substrate 1. Hereinafter, the direction in which the first power output terminal group 11 is arranged is referred to as the arrangement direction L1. Herein, the area where the first power output terminal group 11 is arranged is referred to as the first area R1. On the other hand, the second power output terminal group 12 is arranged on an inner column G2 along the arrangement direction L1 of the first power output terminal group 11, and the inner column G2 is a column that is closer to the inner side than the outermost column G1. Herein, the area where the second power output terminal group 12 is arranged is referred to as the second area R2.

[0038] In addition, Figure 2In the figure, the first power output terminal group 11 is illustrated as being arranged in a row along one side of the power chip module substrate 1, but the first power output terminal group 11 can also be arranged along two sides adjacent to each other with a corner. When the first power output terminal group 11 is arranged in a row along one side of the power chip module substrate 1, the arrangement direction L1 is a straight line. Preferably, when the first power output terminal group 11 is arranged along two sides, the direction along one side of the side with more terminals or along one side parallel to the arrangement direction of the side along the second power output terminal group 12 (similar to the first power output terminal group 11, when the second power output terminal group 12 is also arranged along two sides, the arrangement direction along the side with more terminals is used as the arrangement direction L1.

[0039] Figure 2 In the example, when viewed from the direction along the power chip module substrate 1 and orthogonal to the arrangement direction L1 (viewed in the LX direction), the entire first region R1 of the first power output terminal group 11 arranged in the arrangement direction L1 overlaps with the second region R2 of the second power output terminal group 12 arranged in the arrangement direction L1. In addition, the example is given here that the number of terminals of the second power output terminal group 12 is greater than the number of terminals of the first power output terminal group 11, and when viewed from the LX direction, the entire first region R1 overlaps with the second region R2, but conversely, the number of terminals of the first power output terminal group 11 is greater than the number of terminals of the second power output terminal group 12, and when viewed from the LX direction, the entire second region R2 overlaps with the first region R1. That is, in the first power output terminal group 11 and the second power output terminal group 12, the side with more terminals is the multi-terminal group, and the side with fewer terminals is the less terminal group, and when viewed from the LX direction, the entire area of ​​the less terminal group arranged in the arrangement direction L1 overlaps with the area of ​​the multi-terminal group arranged in the arrangement direction L1. In addition, the example here shows that the entire region where the small terminal group is arranged in the arrangement direction L1 overlaps the region where the large terminal group is arranged in the arrangement direction L1 when viewed from the LX direction, but the first region R1 and the second region R2 may at least partially overlap when viewed from the LX direction.

[0040] On the mounting surface (here, the first surface 30a of the system substrate) of the system substrate 30 on which the power chip module 10 is mounted, the power output terminal group (11, 12) and the power wiring pattern (41, 42) connected to the power output terminal group (11, 12) sometimes hinder the laying of the wiring path of the signal input terminal from the center to the outer periphery of the power chip module 10. By overlapping the entire area where the small terminal group is arranged with the area where the large terminal group is arranged, the possibility of hindering the laying of the wiring path of the signal input terminal can be reduced, thereby making it easy to ensure the wiring path. In addition, by overlapping a part of the area where the small terminal group is arranged with the area where the large terminal group is arranged, the possibility of hindering the laying of the wiring path of the signal input terminal can also be reduced to a certain extent, so that the wiring path can be easily ensured compared to the case where there is no overlap at all.

[0041] like Figure 3 As shown, the load-side connection terminal 23 of the load chip module 20 includes a first power input terminal group 31 and a second power input terminal group 32, wherein the first power input terminal group 31 has a plurality of terminals connected to the first power output terminal group 11, and the second power input terminal group 32 has a plurality of terminals connected to the second power output terminal group 12. Here, the area where the first power input terminal group 31 is configured is referred to as the load-side first area R21, and the area where the second power input terminal group 32 is configured is referred to as the load-side second area R22. Here, the column closest to the outermost peripheral column G1 ( Figure 3 The arrangement direction of the power input terminal group (the first power input terminal group 31 or the second power input terminal group 32) arranged along at least one side of the load chip module substrate 21 in the specific column SG is used as the load side arrangement direction L2. Figure 3 In the illustrated embodiment, the three load-side connection terminals 23 arranged in the specific row SG constitute the specific terminal group 31S, and the arrangement direction of the three load-side connection terminals 23 of the specific terminal group 31S is the load-side arrangement direction L2.

[0042] In addition, here, as a particularly preferred mode, a mode in which the specific column SG is set to the outermost column G1 of the load-side connection terminals 23 configured in a rectangular ring shape is exemplified, but the specific column SG may also be set to a column closer to the inner side than the outermost column G1. In addition, here, as a particularly preferred mode, a mode in which the entire specific terminal group 31S configured in the specific column SG is included in the first power input terminal group 31 is exemplified, but the specific terminal group 31S may include both the load-side connection terminals 23 included in the first power input terminal group 31 and the load-side connection terminals 23 included in the second power input terminal group 32. In the present embodiment, the specific column SG is set in the outermost column G1, the entire specific terminal group 31S configured in the specific column SG is included in the first power input terminal group 31, and the second power input terminal group 32 is configured at a position closer to the inner side (the side from the specific column SG toward the inner side) than the specific column SG.

[0043] Figure 3 The example shows a method in which the first power input terminal group 31 includes terminals arranged in a specific column SG, and the second power input terminal group 32 is arranged at a position closer to the inside than the specific column SG. However, the second power input terminal group 32 may also include terminals arranged in a specific column SG, and the first power input terminal group 31 may also be arranged at a position closer to the inside than the specific column SG. That is, one of the first power input terminal group 31 and the second power input terminal group 32 may also be arranged in any one of the multiple columns along the load-side arrangement direction L2, that is, the specific column SG, and the other of the first power input terminal group 31 and the second power input terminal group 32 may be arranged at a position closer to the inside than the specific column SG.

[0044] Similar to the connection terminal 3 of the power chip module 10, the load-side connection terminal 23 also includes a signal input and output terminal. On the mounting surface of the system substrate 30 on which the load chip module 20 is mounted (here, the first surface 30a of the system substrate), the power input terminal group (31, 32) and the power wiring pattern (41, 42) connected to the power input terminal group (31, 32) sometimes hinder the laying of the wiring path from the center of the load chip module 20 to the outer peripheral side. However, if one of the power input terminal groups (31, 32) is arranged in a specific column SG and the other is arranged at a position closer to the inside than the specific column SG, the possibility of at least a portion of the first power input terminal group 31 and the second power input terminal group 32 overlapping in the direction orthogonal to the load-side arrangement direction L2 increases. Therefore, the possibility of hindering the laying of the wiring path of the signal input and output terminals can be reduced.

[0045] However, refer to Figure 4As described above, the power chip module 10 has a power chip module substrate 1, at least one power semiconductor chip 2, and a plurality of connection terminals 3. In addition, the load chip module 20 has a load chip module substrate 21, at least one load semiconductor chip 22, and a plurality of load-side connection terminals 23. Figure 4 In the illustrated embodiment, the power chip module 10 and the load chip module 20 have a plurality of semiconductor chips (2 or 22), forming a hybrid IC called a multi-chip module (MCM). The multi-chip module is a module in which at least one of a plurality of semiconductor elements (semiconductor chips) having a specific function is mounted on a support substrate (1 or 21). In addition, the multi-chip module may also have one semiconductor element (semiconductor chip).

[0046] in addition, Figure 4 The example shows a semiconductor element of BGA (Ball Grid Array) type. Figure 5 As exemplified above, the semiconductor element may be a SOP (Small Outline Package) or a QFP (Quad Flat Package). Alternatively, a plurality of BGA-type semiconductor elements may be provided to form a multi-chip module.

[0047] like Figure 6 As shown, the load chip module 20 configured as a multi-chip module has a processor 22p such as a microcomputer or a DSP (Digital Signal Processor) and peripheral chips such as a memory 22m as a load semiconductor chip 22. In addition, although not shown in the figure, the power chip module 10 may also have a plurality of power semiconductor chips 2 or a power semiconductor chip 2 and a control chip such as a controller.

[0048] In a multi-chip module, the terminal configuration of the processor 22p can be changed on a supporting substrate such as a load chip module substrate 21. That is, the terminal configuration of the processor 22p can be rearranged on the load chip module substrate 21 to configure the load-side connection terminal 23 so as to form a terminal configuration suitable for the case where the load chip module 20 is mounted on the system substrate 30. In the case where the processor 22p is a general-purpose microcomputer or DSP, the terminal configuration is determined by a semiconductor supplier. In the load chip module 20 as a multi-chip module, the terminal configuration of the processor 22p can be rearranged on the load chip module substrate 21, and an appropriate terminal configuration can be set as the load-side connection terminal 23 of the load chip module 20. Figure 6The terminal configuration of the processor 22p and the load chip module 20 is shown by a perspective view of the lower surface (the side with terminals) viewed from the upper surface (the side without terminals) of the processor 22p and the load chip module 20.

[0049] like Figure 6 As shown, the processor 22p has a plurality of chip power supply terminals 31p ( Figure 6 The load chip module 20 has a load chip side power supply terminal (first power input terminal group 31) (also a terminal painted black) electrically connected to the chip power supply terminal 31p on the load chip module substrate 21. The chip power supply terminal 31p of the processor 22p is arranged at a position (near the center) where power can be appropriately supplied to the semiconductor bare chip mounted on the processor 22p. However, the terminal configuration is rearranged on the load chip module substrate 21, and on the load chip module 20, the first power input terminal group 31 is arranged so as to be continuously arranged to the outermost terminal.

[0050] However, by connecting a plurality of semiconductor elements on a support substrate such as the load chip module substrate 21, it is possible to reduce the terminals (connection terminals 3, load-side connection terminals 23) of the multi-chip module that are only connected between these semiconductor elements. By reducing the total number of terminals, the terminals can be arranged more appropriately on the multi-chip module. For example, Figure 6 The illustrated load chip module 20 includes a processor 22p and a memory 22m. In many cases, the terminals connected to the memory 22m on the processor 22p include bus signals such as an address bus or a data bus, so the number of terminals is large. If the processor 22p and the memory 22m are connected on the load chip module substrate 21, the terminals for such bus signals can be reduced from the load-side connection terminals 23 of the load chip module 20. Therefore, as described above, the arrangement of the power input terminals becomes easy to rearrange.

[0051] Although detailed description is omitted, similarly to the power chip module 10, the terminal configuration of the power semiconductor chip 2 is determined by the supplier of the power semiconductor chip 2, and there is a case where the optimal configuration is not formed when it is installed on the system substrate 30. However, by rearranging on the power chip module substrate 1, the terminal configuration of the power output terminals (the first power output terminal group 11 and the second power output terminal group 12) of the power chip module 10 can be optimized.

[0052] When the power chip module 10 and the load chip module 20 are mounted on the system substrate 30 to form a circuit module 80, Figure 7 to Figure 9As shown, the power chip module 10 and the load chip module 20 can be connected through the wiring layer of the surface layer of the system substrate 30 (the wiring layer of the first surface 30a of the system substrate and the wiring layer of the second surface 30b of the system substrate). In other words, since it is not necessary to use the inner wiring layer of the system substrate 30 to supply power, the cost of the system substrate 30 can be reduced.

[0053] Figure 7 FIG. 1 schematically shows an example of the pattern of the pads and power supply wiring on the first surface 30 a of the system substrate. Figure 8 An example of the pattern of the pads and power supply wiring on the second surface 30 b of the system substrate is schematically shown. Figure 7 and Figure 8 In the figure, the large circle formed by the dotted line or black color represents the mounting pad connected to the connection terminal 3 and the load-side connection terminal 23, and the small circle formed by the solid line and the dotted line represents the through hole TH. The reference numeral "L11" represents the mounting pad connected to the first power output terminal group 11, the reference numeral "L12" represents the mounting pad connected to the second power output terminal group 12, the reference numeral "L31" represents the mounting pad connected to the first power input terminal group 31, and the reference numeral "L32" represents the mounting pad connected to the second power input terminal group 32. In addition, an annular insulating area S is formed between the first power wiring pattern 41 and the mounting pad "L32" connected to the second power input terminal group 32.

[0054] like Figure 7 As shown, the pad connected to the specific terminal group 31S in the first power input terminal group 31 is set in the specific pad area R31S. The first power wiring pattern 41 connecting the first power output terminal group 11 and the first power input terminal group 31 has a length "W11" along the arrangement direction L1 at the part connected to the first power output terminal group 11 (the part corresponding to the outer edge of the load-side connection terminal 23 configured in a rectangular ring shape), and has a length "W31" along the load-side arrangement direction L2 at the part connected to the first power input terminal group 31. The first power wiring pattern 41 has a wiring width "W41" between the power chip module 10 and the load chip module 20.

[0055] exist Figure 7 In the example, "W11", "W31", and "W41" are equal in length, but the three lengths may be different from each other. Fig.15As described later, it is preferred that at least "W11 ≥ W31" is satisfied. That is, in the system substrate 30, it is preferred that the wiring width "W31" of the wiring pattern (first power wiring pattern 41) connected to the specific terminal group 31S along the arrangement direction (load side arrangement direction L2) of the specific terminal group 31S is less than the wiring width "W11" of the wiring pattern (first power wiring pattern 41) connected to the first power output terminal group 11 along the arrangement direction L1 of the first power output terminal group 11.

[0056] Likewise, if Figure 8 As shown, the second power wiring pattern 42 connecting the second power output terminal group 12 and the second power input terminal group 32 has a length "W12" along the arrangement direction L1 at the portion connected to the second power output terminal group 12, and has a length "W32" along the load side arrangement direction L2 on the load chip module 20 side (the portion corresponding to the outer edge of the load side connection terminal 23 configured as a rectangular ring). The second power wiring pattern 42 has a wiring width "W42" between the power chip module 10 and the load chip module 20. Figure 8 In the example, "W12", "W32" and "W42" are the same length, but the three may be different from each other. It is preferred that at least "W12 ≥ W32" is satisfied.

[0057] On the load chip module 20, an appropriate number of power input terminal groups are provided according to the current consumption of the load chip module 20. On the other hand, an appropriate number of power output terminal groups are provided on the power chip module 10 so that the power chip module 10 can output the maximum current within the outputtable range. As a matter of course, on the circuit module 80, a power chip module 10 of a specification capable of sufficiently supplying current even when the current consumption of the load chip module 20 becomes maximum is used. In other words, the maximum value of the current consumption of the load chip module 20 is smaller than the maximum value of the output current of the power chip module 10. Therefore, the effective cross-sectional area of ​​the wiring connected to the power input terminal group can be less than the effective cross-sectional area of ​​the wiring connected to the power output terminal group.

[0058] In the present embodiment, the first power wiring pattern 41 is a surface wiring pattern of the first surface 30a of the system substrate, and the second power wiring pattern 42 is a surface wiring pattern of the second surface 30b of the system substrate. Therefore, the effective cross-sectional area of ​​the first power wiring pattern 41 and the effective cross-sectional area of ​​the second power wiring pattern 42 can be specified by the respective wiring widths. As described above, since the effective cross-sectional area of ​​the wiring connected to the power input terminal group can be smaller than the effective cross-sectional area of ​​the wiring connected to the power output terminal group, the wiring width of the power wiring pattern at the portion connected to the power input terminal group can be less than the wiring width of the power wiring pattern at the portion connected to the power output terminal group.

[0059] Specifically, if Figure 7 As shown in FIG. 1 , the wiring width W31 of the first power wiring pattern 41 at the portion connected to the specific terminal group 31S in the first power input terminal group 31 (the outer edge portion of the load-side connection terminal 23 configured as a rectangular ring) may be less than the wiring width W11 of the first power wiring pattern 41 at the portion connected to the first power output terminal group 11. Figure 8 As shown, the wiring width W32 of the second power wiring pattern 42 at the outer edge of the load-side connection terminal 23 configured in a rectangular ring shape may be less than the wiring width W12 of the second power wiring pattern 42 at the portion connected to the first power output terminal group 11 .

[0060] Such a wiring width can also be determined as follows based on the length of the region where the power input terminal group and the power output terminal group are arranged. That is, the load side first region R21 where the first power input terminal group 31 is arranged (the specific pad region R31S connected to the specific terminal group 31S (refer to Figure 7 )) along the load side arrangement direction L2 length W21 (refer to Figure 3 ) is arranged in the first region R1 where the first power output terminal group 11 is arranged. Figure 2 ) or less. In addition, the length W22 (refer to Figure 3 ) is arranged in the first region R1 where the second power output terminal group 12 is arranged. Figure 2 )the following.

[0061] Fig. 9 is along Figure 1 The schematic cross-sectional view of the circuit module 80 in the Y direction also includes the path of the through-hole TH, showing Figure 7 and Figure 8 The first power supply wiring pattern 41 and the second power supply wiring pattern 42 are shown as examples. Figure 1 and Fig. 9 As shown, the power chip module 10 and the load chip module 20 are supported by the same surface of the system substrate 30 (here, the first surface 30a of the system substrate), and when viewed from the Z direction perpendicular to the substrate surface of the system substrate 30, the outermost peripheral column G1 where the power output terminal group (here, the first power output terminal group 11) is arranged is arranged opposite to the specific column SG. Figure 2 , Figure 3As described above, the first power output terminal group 11 is arranged in the outermost column G1, and the second power output terminal group 12 is arranged at a position closer to the inner side than the outermost column G1. In addition, the first power input terminal group 31 is arranged in the specific column SG, and the second power input terminal group 32 is arranged at a position closer to the inner side than the specific column SG.

[0062] Therefore, if Figure 7 to Figure 9 As shown, the first power output terminal group 11 and the first power input terminal group 31 can be connected on one wiring layer of the system substrate 30, and the second power output terminal group 12 and the second power input terminal group 32 can be connected on another wiring layer. As described above, in the case where the specific column SG is included in the outermost peripheral column G1 of the load chip module 20, the first power output terminal group 11 and the first power input terminal group 31 can be connected through the first power wiring pattern 41 on the surface wiring layer (specific surface wiring layer 30y) of the support surface (system substrate first surface 30a) supporting the power chip module 10 and the load chip module 20 on the system substrate 30. In addition, another wiring layer formed with the second power wiring pattern 42 connecting the second power output terminal group 12 and the second power input terminal group 32 can be used as the surface wiring layer of the back side (system substrate second surface 30b) of the support surface. In this case, the power chip module 10 and the load chip module 20 can be appropriately connected by the system substrate 30 having two wiring layers.

[0063] Of course, the wiring layer formed with the second power wiring pattern 42 may be as follows. Fig.12 In the example shown, the first power wiring pattern 41 is formed in the inner wiring layer, rather than the surface wiring layer. In addition, although the illustration is omitted, in the case where the specific column SG is not included in the outermost column G1 of the load chip module 20, the first power wiring pattern 41 connecting the first power output terminal group 11 and the first power input terminal group 31 can be formed in the inner wiring layer. Similarly, in the case where the first power output terminal group 11 is not configured in the outermost column G1, although the illustration is omitted, the first power wiring pattern 41 can be formed in the inner wiring layer. In these cases, for example, if the second power wiring pattern 42 is formed in the surface wiring layer, the power chip module 10 and the load chip module 20 can be appropriately connected through the system substrate 30 having three wiring layers.

[0064] Fig.10 Another configuration example of the power output terminal of the power chip module 10 is shown. Fig.11 Indicates the use Fig.10 Another structural example of the circuit module 80 of the illustrated power chip module 10. Figures 1 to 9In the above embodiment, the first power output terminal group 11 is arranged in the outermost peripheral column G1, and the second power output terminal group 12 is arranged in the inner peripheral column G2 closer to the inner side than the outermost peripheral column G1. Fig.10 In the illustrated example, the second power output terminal group 12 is arranged in the outermost peripheral row G1, and the first power output terminal group 11 is arranged in the inner peripheral row G2 which is closer to the inner side than the outermost peripheral row G1. Figures 1 to 9 The configuration of the first power input terminal group 31 and the second power input terminal group 32 of the load chip module 20 is the same as the above. Fig. 9 Likewise, Fig.11 is a schematic cross-sectional view of the circuit module 80, which shows the connection between the load chip module 20 and the Fig.10 The illustrated power chip module 10 includes a first power wiring pattern 41 and a second power wiring pattern 42 .

[0065] like Fig.11 As shown, the power chip module 10 and the load chip module 20 are supported by the surfaces of the system substrate 30 facing opposite sides. Fig.10 The power chip module 10 and the load chip module 20 are supported by the second surface 30b of the system substrate. When viewed from the Z direction orthogonal to the substrate surface of the system substrate 30, the power chip module 10 and the load chip module 20 are arranged such that the outermost peripheral column G1 and the specific column SG where the power output terminal group (here, the second power output terminal group 12) are arranged are opposite, and the power chip module 10 and the load chip module 20 do not overlap.

[0066] Since the power chip module 10 and the load chip module 20 are supported by different surfaces of the system substrate 30, they may be arranged in an overlapping manner when viewed from the Z direction. However, usually, the power chip module 10 consumes a large current and generates a large amount of heat. In addition, when the built-in processor 22p of the load chip module 20 has a high operating frequency and a high computing load, the heat generation will increase. Therefore, in order to suppress the transfer of radiant heat from the power chip module 10 to the load chip module 20, and taking into account the heat dissipation of the power chip module 10 and the load chip module 20, the power chip module 10 and the load chip module 20 are arranged on the system substrate 30 in a non-overlapping manner when viewed from the Z direction.

[0067] Reference Fig.10 As described above, the first power output terminal group 11 is arranged in the outermost peripheral column G1, and the second power output terminal group 12 is arranged at a position closer to the inner side than the outermost peripheral column G1. Figure 3As described above, the first power input terminal group 31 is arranged in the specific column SG, and the second power input terminal group 32 is arranged at a position closer to the inside than the specific column SG. Fig.11 As shown, the first power output terminal group 11 and the first power input terminal group 31 can be connected on one wiring layer of the system substrate 30, and the second power output terminal group 12 and the second power input terminal group 32 can be connected on another wiring layer.

[0068] In this case, when the specific column SG is included in the outermost column G1 of the load chip module 20, the first power output terminal group 11 and the first power input terminal group 31 can be connected through the first power wiring pattern 41 on the surface wiring layer (specific surface wiring layer 30y) of the system substrate second surface 30b supporting the load chip module 20 on the system substrate 30. In addition, another wiring layer formed with the second power wiring pattern 42 connecting the second power output terminal group 12 and the second power input terminal group 32 can be used as the surface wiring layer of the system substrate first surface 30a supporting the power chip module 10 from the back side of the system substrate second surface 30b. In this case, the power chip module 10 and the load chip module (20) can be appropriately connected by the system substrate 30 having two wiring layers.

[0069] Although not shown in the figure, it is a matter of course that the wiring layer on which the second power wiring pattern 42 is formed may be as follows: Fig.12 The inner wiring layer is not a surface wiring layer as shown in the example. In addition, although the illustration is omitted, in the case where the specific column SG is not included in the outermost column G1 of the load chip module 20, the first power wiring pattern 41 connecting the first power output terminal group 11 and the first power input terminal group 31 can be formed in the inner wiring layer. In this case, for example, if the second power wiring pattern 42 is formed in the surface wiring layer, the power chip module 10 and the load chip module 20 can be properly connected through the system substrate 30 having three wiring layers. Similarly, although the illustration is omitted, in the case where the second power output terminal group 12 is not configured in the outermost column G1 (such as Figure 2 The terminals shown are not Fig.10 The second power wiring pattern 42 can be formed in the inner wiring layer. In this case, for example, if the first power wiring pattern 41 is formed in the surface wiring layer, the power chip module 10 and the load chip module 20 can be properly connected through the system substrate 30 having three wiring layers.

[0070] In addition, here, refer to Fig.10 and Fig.11, the opposite configuration of the first power output terminal group 11 and the second power output terminal group 12 of the power chip module 10 is described, but similarly, in the load chip module 20, the configuration of the first power input terminal group 31 and the second power input terminal group 32 can also be set oppositely. Figures 1 to 12 The above description can be easily changed, so detailed description is omitted.

[0071] Reference Figures 1 to 12 As described above, as a preferred embodiment, the circuit module 80 has the following structure. The system substrate 30 has a first power wiring pattern 41 and a second power wiring pattern 42 as power paths connecting the power chip module 10 and the load chip module 20, wherein the first power wiring pattern 41 is formed on any one of the surface wiring layers of the system substrate 30, namely, a specific surface wiring layer 30y, and the second power wiring pattern 42 is formed on a wiring layer different from the specific surface wiring layer 30y. In addition, the power output terminal group includes: a first power output terminal group 11 connected to the first power wiring pattern 41; and a second power output terminal group 12 connected to the second power wiring pattern 42. The power input terminal group includes: a first power input terminal group 31 including a specific terminal group 31S and connected to the first power wiring pattern 41; and a second power input terminal group 32 connected to the second power wiring pattern 42. The wiring width (W42) of the second power wiring pattern 42 is greater than the wiring width (W41) of the first wiring pattern (41) (refer to Figure 7 and Figure 8 ). In addition, the wiring width W11 of the first power wiring pattern 41 at the portion connected to the first power output terminal group 11 is greater than the wiring width W31 of the first power wiring pattern 41 at the load chip module 20 side (refer to Figure 7 ). In addition, the wiring width W42 of the second power wiring pattern 42 at the portion connected to the second power output terminal group 12 is greater than the wiring width W32 of the second power wiring pattern 42 on the load chip module 20 side.

[0072] In addition, refer to Figure 1 , Fig. 9 , Fig.12 As described above, when the power chip module 10 and the load chip module 20 are supported by the same surface of the system substrate 30, when the columns in which the power output terminal groups (11, 12) are arranged are arranged relative to the specific column SG when viewed from the Z direction, it is preferred that the first power output terminal group 11 is arranged in a column closer to the outer periphery than the second power output terminal group 12, and the first power input terminal group 31 is arranged in a column closer to the outer periphery than the second power input terminal group 32. In addition, referring to Fig.10 , Fig.11As described above, when the power chip module 10 and the load chip module 20 are respectively supported by the surfaces of the system substrate 30 facing opposite sides, when viewed from the Z direction, the column in which the power output terminal groups (11, 12) are arranged is opposite to the specific column SG, and the power chip module 10 and the load chip module 20 are arranged without overlapping, it is preferred that the first power output terminal group 11 is arranged on a column closer to the inner circumference than the second power output terminal group 12, and the first power input terminal group 31 is arranged on a column closer to the outer circumference than the second power input terminal group.

[0073] In reference Figures 1 to 12 In the above description, the power output terminal group includes the first power output terminal group 11 and the second power output terminal group 12, the power input terminal group includes the first power input terminal group 31 and the second power input terminal group 32, and the power supplies of the two systems are connected via the wiring patterns of the two systems (the first power wiring pattern 41 and the second power wiring pattern 42). However, as Fig.13 and Fig.14 As illustrated, the power output terminal group may be, for example, only the first power output terminal group 11, the power input terminal group may be, for example, the first power input terminal group 31, and the power supply of one system may be connected via a wiring pattern of one system (for example, the first power wiring pattern 41).

[0074] That is, it may also be the following mode: the plurality of connection terminals 3 include a power output terminal group (first power output terminal group 11) having a plurality of terminals, the plurality of load-side connection terminals (23) include a power input terminal group (first power input terminal group 31) having a plurality of terminals connected to the power output terminal group, the power output terminal group is arranged in a column along at least one side of the power chip module substrate 1, the power input terminal group has a specific terminal group 31S arranged in a specific column SG which is a column along at least one side of the load chip module substrate 21, and in the specific column SG, the wiring width (W31) of the wiring pattern (first power wiring pattern 41) connecting the specific terminal group 31S to the system substrate 30 along the load-side arrangement direction L2 of the specific terminal group 31S is less than the wiring width (W11) of the wiring pattern (first power wiring pattern 41) connecting the power output terminal group to the system substrate along the arrangement direction L1 of the power output terminal group.

[0075] and Fig. 9 Likewise, Fig.13 The power chip module 10 and the load chip module 20 are supported by the same surface of the system substrate 30, and when viewed from the Z direction, the column where the power output terminal group (the first power output terminal group 11) is arranged is arranged opposite to the specific column SG. Fig.13As shown, when the specific column SG is included in the outermost periphery of the load chip module 20, on the system substrate 30, the power output terminal group (first power output terminal group 11) and the power input terminal group (first power input terminal group 31) can be connected through the power path (first power wiring pattern 41) formed on the surface wiring layer (specific surface wiring layer 30y) of the support surface (system substrate first surface 30a) supporting the power chip module 10 and the load chip module 20. That is, the power chip module 10 and the load chip module 20 can be appropriately connected through the system substrate 30 having at least the specific surface wiring layer 30y (having one wiring layer).

[0076] Although the illustration is omitted, it is natural that the wiring layer formed with the first power wiring pattern 41 can be a surface wiring layer on the back side (the second side 30b of the system substrate) of the supporting surface (the first side 30a of the system substrate), rather than the specific surface wiring layer 30y. In this case, the power chip module 10 and the load chip module 20 can be properly connected by the system substrate 30 having two wiring layers, which are the surface wiring layer (specific surface wiring layer 30y) for mounting the power chip module 10 and the load chip module 20 on the first side 30a of the system substrate and the surface wiring layer for forming the power path (first power wiring pattern 41) on the second side 30b of the system substrate. Similarly, although the illustration and detailed description are omitted, the first power wiring pattern 41 can also be formed in the inner wiring layer. In this case, the power chip module 10 and the load chip module 20 can be properly connected by the system substrate 30 having three wiring layers.

[0077] and Fig.11 Likewise, Fig.14 The following situation is shown: the power chip module 10 and the load chip module 20 are supported by the surfaces of the system substrate 30 facing opposite sides, respectively, and when viewed from the Z direction, the column where the power output terminal group (the first power output terminal group 11) is arranged is opposite to the specific column SG, and the power chip module 10 and the load chip module 20 are arranged without overlapping. Fig.14As shown, when the specific column SG is included in the outermost periphery of the load chip module 20, the power output terminal group (first power output terminal group 11) and the power input terminal group (first power input terminal group 31) can be connected through the power path (first power wiring pattern 41) formed on the surface wiring layer (specific surface wiring layer 30y) of the support surface (system substrate second surface 30b) supporting the load chip module 20 on the system substrate 30. That is, the power chip module 10 and the load chip module 20 can be appropriately connected by the system substrate 30 having two wiring layers, namely, the surface wiring layer for mounting the power chip module 10 on the system substrate first surface 30a and the surface wiring layer (specific surface wiring layer 30y) for mounting the load chip module 20 on the system substrate second surface 30b and forming the power path (first power wiring pattern 41).

[0078] In addition, Fig.14 In the embodiment, the arrangement of the connection terminals of the power chip module 10 is similar to Fig.10 and Fig.11 The first power output terminal group 11 is not arranged in the outermost peripheral row G1, but Figure 2 and Fig. 9 Similarly, the first power output terminal group 11 may be arranged in the outermost column G1. In addition, of course, the wiring layer formed with the first power wiring pattern 41 may also be the surface wiring layer of the back side (the first side 30a of the system substrate) of the support surface (the second side 30b of the system substrate) of the load chip module 20, rather than the specific surface wiring layer 30y. Although not shown in the figure, for example, when the specific column SG is not included in the outermost column G1 of the load chip module 20 and the first power output terminal group 11 is arranged in the outermost column G1 of the power chip module 10, it is preferred that the first power wiring pattern 41 is formed on the surface wiring layer of the first side 30a of the system substrate. In this case, the power chip module 10 and the load chip module 20 can be appropriately connected by the system substrate 30 having two wiring layers.

[0079] In addition, similarly, although illustration and detailed description are omitted, the first power wiring pattern 41 can also be formed on the inner wiring layer. For example, when the specific column SG is not included in the outermost column G1 of the load chip module 20, and the first power output terminal group 11 is not configured on the outermost column G1 of the power chip module 10, it is preferred to form the first power wiring pattern 41 on the inner wiring layer. In this case, the power chip module 10 and the load chip module 20 can be appropriately connected by the system substrate 30 having at least three wiring layers.

[0080] In addition, in the above content, reference Figure 7etc. illustrate that the wiring width W11 is the same as the wiring width W31, wherein the wiring width W11 is the wiring width of the first power wiring pattern 41 (wiring pattern connecting the power output terminal group to the system substrate 30) connecting the first power output terminal group 11 to the system substrate 30 along the arrangement direction L1 of the first power output terminal group 11, and the wiring width W31 is the wiring width of the first power wiring pattern 41 connecting the specific terminal group 31S to the system substrate 30 on a specific column along the arrangement direction L2 of the specific terminal group 31S.

[0081] However, the load chip module 20 may have more input and output signals and more terminals than the power chip module 10. In this case, the terminals of the load chip module 20 are preferably arranged at a higher density than the terminals of the power chip module 10. Therefore, the terminal interval of the load chip module 20 tends to be narrower than the terminal interval (pin pitch) of the power chip module 10. Figure 7 In the example, the terminal interval of the power chip module 10 is the same as the terminal interval of the load chip module 20, and the wiring width "W1" is the same as the wiring width "W31". Fig.15 As shown, when the terminal interval of the load chip module 20 is narrower than the terminal interval of the power chip module 10, the wiring width “W11” is greater than the wiring width “W31”.

[0082] Therefore, the wiring width W11 of the first power wiring pattern 41 (wiring pattern connecting the power output terminal group to the system substrate 30) connecting the first power output terminal group 11 to the system substrate 30 along the arrangement direction L1 of the first power output terminal group 11 can be greater than the wiring width W31 of the first power wiring pattern 41 connecting the specific terminal group 31S to the system substrate 30 on a specific column along the arrangement direction L2 of the specific terminal group 31S.

[0083] As described above, a method for supplying two systems of power from the power chip module 10 to the load chip module 20 using two wiring layers (preferably two surface wiring layers) has been described. In addition, a method for supplying one system of power from the power chip module 10 to the load chip module 20 using one wiring layer (preferably a surface wiring layer) has also been described. Supplying two systems of power is achieved by arranging the first power output terminal group 11 and the second power output terminal group 12 of the power chip module 10 (see Figure 2 , Fig.10 The power supply to a system is realized by arranging the power output terminal group (first power output terminal group 11) of the power chip module 10 (analogously applicable to Figure 2 , Fig.10). Hereinafter, the case of supplying power to two systems will be taken as an example, and the comparative example will be referred to. Fig.16 The excellent structure of the power chip module 10 of this embodiment will be described.

[0084] and Figure 1 and Fig. 9 Likewise, Fig.16 The first power supply wiring pattern 41 is schematically shown when the power chip module 10 and the load chip module 20 are supported by the same surface of the system substrate 30, that is, the first surface 30a of the system substrate. Figure 3 The arrangement of the first power input terminal group 31 of the load chip module 20 is as described above. On the other hand, the number of connection terminals of the first power output terminal group 11 and the second power output terminal group 12 of the power chip module 10, which respectively constitute the power output terminal group, is the same as that of the reference Figure 2 , Fig.10 The above method is the same as above, but the arrangement direction is different. Figure 2 , Fig.10 In the above-mentioned embodiment, the first power output terminal group 11 and the second power output terminal group 12 are arranged along the arrangement direction L1 along the side of the rectangular power chip module substrate 1. Fig.16 In the comparative example shown, the first power output terminal group 11 is arranged in one row in the LX direction orthogonal to the arrangement direction L1. In addition, the second power output terminal group 12 is arranged in two rows in the LX direction.

[0085] That is, the first power output terminal group 11 and the second power output terminal group 12 are arranged side by side from the center to the outer periphery of the power semiconductor chip 2. Therefore, in the comparative example, the length (W1') of the first region R1 where the first power output terminal group 11 is arranged along the arrangement direction L1 is longer than that along the reference direction. Figure 2 The length (W1) of the arrangement direction L1 in the above-mentioned embodiment is short. Figure 2 In the above-mentioned embodiments, three connection terminals 3 are arranged along the arrangement direction L1, but in the comparative example, there is only one connection terminal 3 along the arrangement direction L1. In the comparative example, the length of the first region R1 along the arrangement direction L1 is approximately one-third. Therefore, the wiring width W11 of the first power wiring pattern 41 at the portion connected to the first power output terminal group 11 is larger than Fig.16 The comparative examples shown in the reference Figure 7 The above-mentioned embodiment is shorter, and the effective cross-sectional area of ​​the first power supply wiring pattern 41 is also narrowed.

[0086] In the comparative example, as a method of increasing the effective cross-sectional area of ​​the first power wiring pattern 41, it is considered to use a wiring layer other than the surface wiring layer. In order to use another wiring layer with the same wiring width as the first power wiring pattern 41 on the first surface 30a of the system substrate to ensure the same cross-sectional area as the reference Figure 7 To obtain an effective cross-sectional area equivalent to that of the above-mentioned embodiment, two other wiring layers need to be used. For example, the wiring layer of the second surface 30b of the system substrate and the inner wiring layer not shown need to be used. Fig. 9 and Fig.11 As described above, when the specific column SG of the load chip module 20 is included in the outermost column G1, the system substrate 30 can be formed of a substrate having at least two wiring layers. However, in the comparative example, three wiring layers are required.

[0087] Regarding the second power output terminal group 12, referring to Figure 2 In the above-mentioned embodiment, six connection terminals 3 are arranged along the arrangement direction L1, but in the comparative example, two connection terminals 3 are arranged along the arrangement direction L1, and the length of the second region R2 along the arrangement direction L1 in the comparative example is approximately one third. Therefore, similarly to the first power wiring pattern 41, Fig.16 The comparative examples shown are shorter than the reference Figure 8 In the above embodiment, the effective cross-sectional area of ​​the second power wiring pattern 42 is also narrowed. Therefore, it is also necessary to use another wiring layer for the second power wiring pattern 42, and the cost of the system substrate 30 may increase.

[0088] On the other hand, refer to Figure 1 to Figure 15 As described above, in this embodiment, a sufficient wiring width in the surface direction of the system substrate 30 on which the power chip module 10 is mounted can be ensured, thereby ensuring a sufficient effective cross-sectional area of ​​the wiring. Therefore, there is no need to expand the effective cross-sectional area of ​​the wiring in the thickness direction of the substrate, thereby suppressing the increase of the wiring layer (inner wiring layer) of the system substrate 30.

[0089] (Outline of Implementation Methods)

[0090] The following is a brief description of the outlines of the power chip module (10) and the circuit module (80) described above.

[0091] As one embodiment, a circuit module (80) comprises a power chip module (10), a load chip module (20) and a system substrate (30), wherein the power chip module (10) comprises: a rectangular plate-shaped power chip module substrate (1); at least one power semiconductor chip (2), supported by the upper surface (1a) of the power chip module substrate (1); a plurality of connection terminals (3), arranged in a plurality of rows of rectangular rings along the sides of the power chip module substrate (1) on the lower surface (1b) of the power chip module substrate (1), and connected to the power chip module substrate (1). The load chip module (20) is electrically connected with a semiconductor chip (2), the load chip module (20) comprising: a rectangular plate-shaped load chip module substrate (21); at least one load semiconductor chip (22) supported by the upper surface (21a) of the load chip module substrate (21); a plurality of load-side connection terminals (23) arranged in a plurality of rows of rectangular rings along the sides of the load chip module substrate (21) on the lower surface (21b) of the load chip module substrate (21) and electrically connected to the load semiconductor chip (22); the system substrate (30) supporting the load semiconductor chip (22); and a plurality of load-side connection terminals (23) arranged in a plurality of rows of rectangular rings along the sides of the load chip module substrate (21) on the lower surface (21b) of the load chip module substrate (21). The power chip module (10) and the load chip module (20), wherein the plurality of connection terminals (3) include a power output terminal group (11) having a plurality of terminals, the plurality of load-side connection terminals (23) include a power input terminal group (31) having a plurality of terminals connected to the power output terminal group (11), the power output terminal group (11) being arranged in a row along at least one side of the power chip module substrate (1), the power input terminal group (31) having a specific terminal group (31S), the specific terminal group ( The load chip module substrate (31S) is arranged in a column, i.e., a specific column (SG), along at least one side of the load chip module substrate (21), so that the wiring width (W11) of the wiring pattern (41) connecting the power output terminal group (11) to the system substrate (30) along the arrangement direction (L1) of the power output terminal group (11) is greater than the wiring width (W31) of the wiring pattern (41) connecting the specific terminal group (31S) to the system substrate (30) in the specific column along the arrangement direction (L2) of the specific terminal group (31S).

[0092] In the load chip module (20), an appropriate number of power input terminal groups are provided according to the current consumption of the load chip module (20). On the other hand, in the power chip module (10), an appropriate number of power output terminal groups are provided so that the power chip module (10) can output the maximum current within the output range. As a matter of course, a power chip module (10) of a specification that can supply sufficient current even when the current consumption of the load chip module (20) is maximum is used. In other words, the maximum value of the current consumption of the load chip module (20) is less than the maximum value of the output current of the power chip module (10). Therefore, the effective cross-sectional area of ​​the wiring connected to the power input terminal group can be smaller than the effective cross-sectional area of ​​the wiring connected to the power output terminal group. According to this structure, the wiring width (W11) of the wiring pattern connected to the power output terminal group is greater than the wiring width (W31) of the wiring pattern connected to the power input terminal group. Therefore, the power chip module (10) and the load chip module (80) can be appropriately connected.

[0093] Here, preferably, the system substrate (30) has a first wiring pattern (41) and a second wiring pattern (42) as a power path connecting the power chip module (10) and the load chip module (20), the first wiring pattern (41) being formed on any one surface wiring layer of the system substrate (30), namely a specific surface wiring layer (30y), and the second wiring pattern (42) being formed on a wiring layer different from the specific surface wiring layer (30y), the power output terminal group comprising: a first power output terminal group (11), connected to the first wiring pattern (41); a second power output terminal group (12), connected to the second wiring pattern (42), and the power input terminal group comprising: a first power input terminal group (31), including the specific terminal group (3 1S), and connected to the first wiring pattern (41); a second power input terminal group (32), connected to the second wiring pattern (42), the wiring width (W42) of the second wiring pattern (42) being greater than the wiring width (W41) of the first wiring pattern (41), the wiring width (W11) of the first wiring pattern (41) at a portion connected to the first power output terminal group (11) being greater than the wiring width (W31) of the first wiring pattern (41) at the side of the load chip module (20), and the wiring width (W42) of the second wiring pattern (42) at a portion connected to the second power output terminal group (12) being greater than the wiring width (W32) of the second wiring pattern (42) at the side of the load chip module (20).

[0094] As described above, the maximum value of the current consumption of the load chip module (20) is smaller than the maximum value of the output current of the power chip module (10). Therefore, the effective cross-sectional area of ​​the wiring connected to the power input terminal group can be smaller than the effective cross-sectional area of ​​the wiring connected to the power output terminal group. According to this structure, the length (W21, W22) of the area where the power input terminal group is arranged is respectively less than the length (W1, W2) of the area where the corresponding power output terminal group is arranged. Therefore, the power chip module (10) and the load chip module (80) can be appropriately connected.

[0095] In addition, preferably, the power chip module (10) and the load chip module (20) are configured to be supported by the same surface of the system substrate (30), and when viewed from a direction (Z) orthogonal to the substrate surface of the system substrate (30), the column in which the power output terminal groups (11, 12) are arranged is opposite to the specific column (SG), the first power output terminal group (11) is arranged in a column closer to the outer peripheral side than the second power output terminal group (12), and the first power input terminal group (31) is arranged in a column closer to the outer peripheral side than the second power input terminal group (32).

[0096] According to this structure, the first power output terminal group (11) and the first power input terminal group (31) can be connected on a specific surface wiring layer (30y) of the system substrate (30), and the second power output terminal group (12) and the second power input terminal group (32) can be connected on another wiring layer. The other wiring layer connecting the second power output terminal group (12) and the second power input terminal group (32) can be set, for example, as a surface wiring layer on the back side (30b) of the support surface (30a) formed with the specific surface wiring layer (30y). In this case, the power chip module (10) and the load chip module (20) can be properly connected through the system substrate (30) having two wiring layers. In addition, the other wiring layer connecting the second power output terminal group (12) and the second power input terminal group (32) can be an inner wiring layer instead of the surface wiring layer on the back side (30b). In this case, for example, the power chip module (10) and the load chip module (20) can be properly connected through the system substrate (30) having three wiring layers.

[0097] In addition, preferably, the power chip module (10) and the load chip module (20) are configured to be supported by surfaces of the system substrate (30) facing opposite sides thereof, respectively, and when viewed from a direction (Z) orthogonal to the substrate surface of the system substrate (30), a column in which the power output terminal groups (11, 12) are arranged is opposite to the specific column (SG), and the power chip module (10) and the load chip module (20) do not overlap, the first power output terminal group (11) is arranged in a column closer to the inner peripheral side than the second power output terminal group (12), and the first power input terminal group (31) is arranged in a column closer to the outer peripheral side than the second power input terminal group (32).

[0098] As described above, according to this structure, a specific surface wiring layer (30y) of the system substrate (30) can be used to connect the first power output terminal group (11) and the first power input terminal group (31), and another wiring layer can be used to connect the second power output terminal group (12) and the second power input terminal group (32). The other wiring layer connecting the second power output terminal group (12) and the second power input terminal group (32) can be set, for example, as a surface wiring layer on the back side (30a) of the surface (30b) formed with the specific surface wiring layer (30y). In this case, the power chip module (10) and the load chip module (20) can be appropriately connected by the system substrate (30) having two wiring layers. In addition, the other wiring layer connecting the second power output terminal group (12) and the second power input terminal group (32) can be an inner wiring layer instead of the surface wiring layer on the back side (30a) of the surface (30b) formed with the specific surface wiring layer (30y). In this case, for example, the power chip module (10) and the load chip module (20) can be appropriately connected through the system substrate (30) having three wiring layers.

[0099] As one embodiment, a power chip module (10) comprises: a rectangular plate-shaped power chip module substrate (1); at least one power semiconductor chip (2), supported by the upper surface (1a) of the power chip module substrate (1); a plurality of connection terminals (3), arranged in a plurality of rows of rectangular rings along the sides of the power chip module substrate (1) on the lower surface (1b) of the power chip module substrate (1), and electrically connected to the power semiconductor chip (2), wherein the plurality of connection terminals (3) include: a first power output terminal group (11), having a plurality of terminals for outputting a first voltage; a second power output terminal group (12), having a plurality of terminals for outputting a second voltage, the first power output terminal group (11) and the second power output terminal group (12) One of the power output terminal groups is arranged in an outermost column (G1) along at least one side of the power chip module substrate (1), and the other of the first power output terminal group (11) and the second power output terminal group (12) is arranged in an inner column (G2) that is closer to the inner side than the outermost column (G1) along an arrangement direction (L1) of the power output terminal groups in the outermost column (SG), and when viewed from a direction (LX) along the power chip module substrate (1) and orthogonal to the arrangement direction (L1), a first region (R1) where the first power output terminal group (11) is arranged and a second region (R2) where the second power output terminal group (12) is arranged at least partially overlap.

[0100] According to this structure, the power output terminal group arranged in the outermost column (G1) and the power supply object can be connected by the surface wiring formed on the mounting surface of the substrate on which the power chip module (10) is mounted. In addition, the power output terminal group arranged in the outermost column (G1) is adjacent to the connection terminal (3) arranged in a rectangular ring shape in the circumferential direction, so that the surface wiring having a sufficient wiring width and suppressing the wiring impedance can be set in the direction along the arrangement direction (L1). When viewed from the direction (LX) orthogonal to the arrangement direction (L1), the power output terminal group arranged in the inner column (G2) overlaps with the power output terminal group arranged in the outermost column (G1) at least in part, so it is difficult to connect to the power supply object through the surface wiring on the mounting surface as described above. However, it is possible to appropriately connect to the power supply object through the wiring set on another wiring layer other than the surface wiring on the mounting surface of the substrate. That is, a sufficient wiring width can be ensured in the surface direction of the substrate on which the power chip module (10) is mounted, thereby ensuring a sufficient effective cross-sectional area of ​​the wiring, so that there is no need to expand the effective cross-sectional area of ​​the wiring in the thickness direction of the substrate. Therefore, the increase of the wiring layer (inner wiring layer) of the substrate can be suppressed. In this way, according to this structure, the increase of the wiring layer of the mounting substrate can be suppressed, and the supply source and the supply object of the power supply can be properly connected.

[0101] Here, the one with more terminals in the first power output terminal group (11) and the second power output terminal group (12) is regarded as a multi-terminal group, and the one with fewer terminals is regarded as a small terminal group. When observed from a direction along the power chip module substrate (1) and orthogonal to the arrangement direction (L1), the entire area where the small terminal group is arranged along the arrangement direction (L1) overlaps with the area where the multi-terminal group is arranged along the arrangement direction (L1).

[0102] The connection terminals (3) arranged in multiple rows in a rectangular ring shape also include signal input and output terminals, but on the mounting surface of the substrate on which the power chip module (10) is mounted, the wiring connected to the power output terminal group and the power output terminal group sometimes hinders the laying of the wiring path of the signal input terminal from the center of the power chip module (10) to the outer peripheral side. According to this structure, since the entire area where the small terminal group is arranged overlaps with the arrangement area of ​​the large terminal group, the possibility of hindering the laying of the wiring path of the signal input terminal can be reduced, so that the wiring path can be easily ensured.

[0103] Preferably, in a circuit module (80) having the above-mentioned power chip module (10) and a load chip module (20) connected to the power chip module (10), the load chip module (20) comprises: a rectangular plate-shaped load chip module substrate (21); at least one load semiconductor chip (22) supported by the upper surface (21a) of the load chip module substrate (21); a plurality of load-side connecting terminals (23) arranged in a plurality of rows of rectangular rings along each side of the load chip module substrate (21) on the lower surface (21b) of the load chip module substrate (21) and electrically connected to the load semiconductor chip (22), the plurality of load-side connecting terminals (23) comprising a first power input terminal group (31) and a second power input terminal group (32) as power input terminal groups, the first power input terminal group (31) being connected to the first power output terminal group (11) and having a plurality of terminals, the second power input terminal group (32) being connected to the second power output terminal group (12) and having a plurality of terminals, an area where the first power input terminal group (31) is arranged is a first area (R21) on the load side, and an area where the second power input terminal group (32) is arranged is a second area (R22) on the load side, in a row closest to the outermost circumference, an arrangement direction of the power input terminal group arranged along at least one side of the load chip module substrate (21) is taken as a load side arrangement direction (L2), the first power input terminal group (31) is arranged so that a length (W21) of the first area on the load side in the direction of the load side arrangement direction (L2) is less than a length (W1) of the first area (R1) in the direction of the arrangement direction (L1), and the second power input terminal group (32) is arranged so that a length (W22) of the second area on the load side in the direction of the load side arrangement direction (L2) is less than a length (W2) of the second area (R2) in the direction of the arrangement direction (L1).

[0104] An appropriate number of power input terminal groups are provided on the load chip module (20) according to the current consumption of the load chip module (20). On the other hand, an appropriate number of power output terminal groups are provided on the power chip module (10) so that the power chip module (10) can output the maximum current within the output range. As a matter of course, a power chip module (10) of a specification that can supply sufficient current even when the current consumption of the load chip module (20) is maximum is used. In other words, the maximum value of the current consumption of the load chip module (20) is less than the maximum value of the output current of the power chip module (10). Therefore, the effective cross-sectional area of ​​the wiring connected to the power input terminal group can be smaller than the effective cross-sectional area of ​​the wiring connected to the power output terminal group. According to this structure, the length (W21, W22) of the area where the power input terminal group is configured is respectively less than the length (W1, W2) of the area where the corresponding power output terminal group is configured. Therefore, the power chip module (10) and the load chip module (80) can be appropriately connected.

[0105] Here, preferably, one of the first power input terminal group (31) and the second power input terminal group (32) is arranged in any one column among a plurality of columns along the load side arrangement direction (L2), namely, a specific column (SG), and the other of the first power input terminal group (31) and the second power input terminal group (32) is arranged at a position closer to the inside than the specific column (SG).

[0106] Similar to the connection terminals (3) of the power chip module (10), the load-side connection terminals (23) arranged in a plurality of rows and in a rectangular ring shape also include signal input and output terminals. On the mounting surface of the substrate on which the load chip module (20) is mounted, the power input terminal group and the wiring connected to the power input terminal group sometimes hinder the laying of the wiring path from the center of the load chip module (20) to the outer peripheral side. However, according to the present structure, the first power input terminal group (31) and the second power input terminal group (32) are arranged in a manner that at least a portion overlaps in a direction orthogonal to the load-side arrangement direction (L2), thereby reducing the possibility of hindering the laying of the wiring path of the signal input and output terminals.

[0107] In addition, preferably, when one of the first power input terminal group (31) and the second power input terminal group (32) is arranged in the specific column (SG) and the other power input terminal group is arranged on the inner side of the specific column (SG), the circuit module further comprises a system substrate (30), the system substrate (30) supports the power chip module (10) and the load chip module (20), and the power chip module (10) and the load chip module (20) are arranged to be supported by the same surface of the system substrate (30). The system substrate (30) is supported by a plurality of power supply terminals, and when viewed from a direction (Z) perpendicular to the substrate surface of the system substrate (30), the outermost column (G1) where the power output terminal group is arranged is opposite to the specific column (SG), the first power output terminal group (11) is arranged in the outermost column (G1), the second power output terminal group (12) is arranged at a position closer to the inside than the outermost column (G1), the first power input terminal group (31) is arranged in the specific column (SG), and the second power input terminal group (32) is arranged at a position closer to the inside than the specific column (SG).

[0108] According to this structure, the first power output terminal group (11) and the first power input terminal group (31) can be connected on one wiring layer of the system substrate (30), and the second power output terminal group (12) and the second power input terminal group (32) can be connected on another wiring layer. In the case where the specific column (SG) is included in the outermost column (G1) of the load chip module (20), the first power output terminal group (11) and the first power input terminal group (31) can be connected on the surface wiring layer of the support surface (30a) supporting the power chip module (10) and the load chip module (20) on the system substrate (30). In addition, the other wiring layer connecting the second power output terminal group (12) and the second power input terminal group (32) can be set as a surface wiring layer on the back side (30b) of the support surface (30a). In this case, the power chip module (10) and the load chip module (20) can be appropriately connected by the system substrate (30) having two wiring layers. Furthermore, when the specific column (SG) is not included in the outermost column (G1) of the load chip module (20), the first power output terminal group (11) and the first power input terminal group (31) are connected in the inner wiring layer. In this case, for example, the power chip module (10) and the load chip module (20) can be appropriately connected through a system substrate (30) having three wiring layers.

[0109] In addition, preferably, when one of the first power input terminal group (31) and the second power input terminal group (32) is arranged in the specific column (SG) and the other power input terminal group is arranged at a position closer to the inside than the specific column (SG), the circuit module further comprises a system substrate (30) supporting the power chip module (10) and the load chip module (20), and the power chip module (10) and the load chip module (20) are arranged to be supported by surfaces of the system substrate (30) facing opposite sides thereof, and to be connected to the system substrate (30) from the sides thereof. ), the outermost column (G1) where the power output terminal group is arranged is opposite to the specific column (SG), and the power chip module (10) and the load chip module (20) do not overlap, the second power output terminal group (12) is arranged in the outermost column (G1), the first power output terminal group (11) is arranged at a position closer to the inside than the outermost column (G1), the first power input terminal group (31) is arranged in the specific column (SG), and the second power input terminal group (32) is arranged at a position closer to the inside than the specific column (SG).

[0110] As described above, according to this structure, the first power output terminal group (11) and the first power input terminal group (31) can be connected on one wiring layer of the system substrate (30), and the second power output terminal group (12) and the second power input terminal group (32) can be connected on another wiring layer. In the case where the specific column (SG) is included in the outermost column (G1) of the load chip module (20), the first power output terminal group (11) and the first power input terminal group (31) can be connected on the surface wiring layer of the surface (30b) supporting the load chip module (20) on the system substrate (30). In addition, the other wiring layer connecting the second power output terminal group (12) and the second power input terminal group (32) can be set as a surface wiring layer that supports the surface (30a) of the power chip module (10) with the back side of the surface (30b). In this case, the power chip module (10) and the load chip module (20) can be appropriately connected by the system substrate (30) having two wiring layers. Furthermore, when the specific column (SG) is not included in the outermost column (G1) of the load chip module (20), the first power output terminal group (11) and the first power input terminal group (31) are connected in the inner wiring layer. In this case, for example, the power chip module (10) and the load chip module (20) can be appropriately connected through a system substrate (30) having three wiring layers.

[0111] Description of reference numerals:

[0112] 1: Power chip module substrate

[0113] 1a: Top surface of the power chip module substrate

[0114] 1b: Bottom surface of the power chip module substrate

[0115] 2: Semiconductor chips for power supply

[0116] 3: Connecting terminals

[0117] 10: Power chip module

[0118] 11: First power output terminal group

[0119] 12: Second power output terminal group

[0120] 20: Load chip module

[0121] 21: Load chip module substrate

[0122] 21a: Upper surface of the load chip module substrate

[0123] 21b: Bottom surface of the load chip module substrate

[0124] 22: Load semiconductor chip

[0125] 23: Load side connection terminal

[0126] 30: System substrate

[0127] 30y: Specific surface wiring layer

[0128] 31: First power input terminal group

[0129] 32: Second power input terminal group

[0130] 41: First power supply wiring pattern (first wiring pattern)

[0131] 42: Second power supply wiring pattern (second wiring pattern)

[0132] 80: Circuit module

[0133] G1: Outermost row

[0134] G2: Inner row

[0135] L1: Arrangement direction

[0136] L2: Load side arrangement direction

[0137] R1: First Area

[0138] R2: Second Area

[0139] R21: Load side first area

[0140] R22: Load side second area

[0141] SG: Specific columns

[0142] W11: Wiring width

[0143] W12: Wiring width

[0144] W31: Wiring width

[0145] W32: Width of wiring

Claims

1. A circuit module comprising a power chip module, a load chip module and a system substrate, The power chip module comprises: a rectangular plate-shaped power chip module substrate; at least one power semiconductor chip supported by the upper surface of the power chip module substrate; a plurality of connection terminals arranged in a plurality of rows of rectangular rings along the sides of the power chip module substrate on the lower surface of the power chip module substrate and electrically connected to the power semiconductor chip. The load chip module comprises: a rectangular plate-shaped load chip module substrate; at least one load semiconductor chip supported by the upper surface of the load chip module substrate; a plurality of load-side connection terminals arranged in a plurality of rows of rectangular rings along the sides of the load chip module substrate on the lower surface of the load chip module substrate and electrically connected to the load semiconductor chip. The system substrate supports the power chip module and the load chip module, wherein: The plurality of connection terminals include a power output terminal group having a plurality of terminals, The plurality of load-side connection terminals include a power input terminal group having a plurality of terminals connected to the power output terminal group, The power output terminal group includes a terminal group arranged in a row at the outermost periphery along at least one side of the power chip module substrate. The power input terminal group includes a specific terminal group, and the specific terminal group is arranged in a column along at least one side of the load chip module substrate, namely, a specific column. The wiring width of the wiring pattern connecting the power output terminal group to the system substrate along the arrangement direction of the power output terminal group is greater than the wiring width of the wiring pattern connecting the specific terminal group to the system substrate in the specific column along the arrangement direction of the specific terminal group.

2. The circuit module according to claim 1, wherein: The system substrate has a first wiring pattern and a second wiring pattern as a power path connecting the power chip module and the load chip module, the first wiring pattern is formed on any surface wiring layer of the system substrate, that is, a specific surface wiring layer, and the second wiring pattern is formed on a wiring layer different from the specific surface wiring layer. The power output terminal group includes: a first power output terminal group connected to the first wiring pattern; a second power output terminal group connected to the second wiring pattern, The power input terminal group includes: a first power input terminal group including the specific terminal group and connected to the first wiring pattern; a second power input terminal group connected to the second wiring pattern, The wiring width of the second wiring pattern is greater than the wiring width of the first wiring pattern, The wiring width of the first wiring pattern at a portion connected to the first power output terminal group is greater than the wiring width of the first wiring pattern at the load chip module side. A wiring width of the second wiring pattern at a portion connected to the second power output terminal group is greater than or equal to a wiring width of the second wiring pattern at the load chip module side.

3. The circuit module according to claim 2, wherein: The power chip module and the load chip module are configured to be supported by the same surface of the system substrate, and the column where the power output terminal group is configured is opposite to the specific column when viewed from a direction perpendicular to the substrate surface of the system substrate. The first power output terminal group is arranged in a row on the outer peripheral side than the second power output terminal group. The first power input terminal group is arranged in a row on the outer peripheral side than the second power input terminal group.

4. The circuit module according to claim 2, wherein: The power chip module and the load chip module are respectively supported by surfaces of the system substrate facing opposite sides, and when viewed from a direction perpendicular to the substrate surface of the system substrate, a column where the power output terminal group is arranged is opposite to the specific column, and the power chip module and the load chip module do not overlap. The first power output terminal group is arranged in a row closer to the inner peripheral side than the second power output terminal group. The first power input terminal group is arranged in a row on the outer peripheral side than the second power input terminal group.

5. A power chip module, comprising: a rectangular plate-shaped power chip module substrate; at least one power semiconductor chip supported by the upper surface of the power chip module substrate; a plurality of connection terminals arranged in a plurality of rows of rectangular rings along the sides of the power chip module substrate on the lower surface of the power chip module substrate and electrically connected to the power semiconductor chip, wherein: The plurality of connection terminals include: a first power output terminal group having a plurality of terminals outputting a first voltage; a second power output terminal group having a plurality of terminals outputting a second voltage, One of the first power output terminal group and the second power output terminal group is arranged in an outermost column along at least one side of the power chip module substrate, that is, an outermost column. The other of the first power output terminal group and the second power output terminal group is arranged in an inner column, i.e., an inner column, along the arrangement direction of the power output terminal groups in the outermost column. When viewed from a direction along the power chip module substrate and perpendicular to the arrangement direction, a first region where the first power output terminal group is arranged and a second region where the second power output terminal group is arranged at least partially overlap.

6. The power chip module according to claim 5, wherein: The first power output terminal group and the second power output terminal group, whichever has more terminals, are used as a large terminal group, and the other which has fewer terminals is used as a small terminal group. When viewed from a direction along the power chip module substrate and perpendicular to the arrangement direction, the entire region where the few terminal groups are arranged along the arrangement direction overlaps the region where the many terminal groups are arranged along the arrangement direction.

7. A circuit module comprising the power chip module according to claim 5 or 6 and a load chip module connected to the power chip module, wherein: The load chip module comprises: a rectangular plate-shaped load chip module substrate; at least one load semiconductor chip supported by the upper surface of the load chip module substrate; a plurality of load-side connection terminals arranged in a plurality of rows of rectangular rings along the sides of the load chip module substrate on the lower surface of the load chip module substrate and electrically connected to the load semiconductor chip. The plurality of load-side connection terminals include a first power input terminal group and a second power input terminal group as power input terminal groups, the first power input terminal group is connected to the first power output terminal group and has a plurality of terminals, the second power input terminal group is connected to the second power output terminal group and has a plurality of terminals, The area where the first power input terminal group is arranged is the first load-side area, and the area where the second power input terminal group is arranged is the second load-side area. In the row closest to the outermost periphery, the arrangement direction of the power input terminal group arranged along at least one side of the load chip module substrate is set as the load side arrangement direction, The first power input terminal group is configured so that the length of the first area on the load side along the load side arrangement direction is less than the length of the first area along the arrangement direction, and the second power input terminal group is configured so that the length of the second area on the load side along the load side arrangement direction is less than the length of the second area along the arrangement direction.

8. The circuit module according to claim 7, wherein: One of the first power input terminal group and the second power input terminal group is arranged in any one column, that is, a specific column, among a plurality of columns along the load side arrangement direction. The other of the first power input terminal group and the second power input terminal group is arranged at an inner side than the specific column.

9. The circuit module according to claim 8, wherein: The circuit module also has a system substrate, and the system substrate supports the power chip module and the load chip module. The power chip module and the load chip module are configured to be supported by the same surface of the system substrate, and the outermost peripheral column where the power output terminal group is configured is opposite to the specific column when viewed from a direction perpendicular to the substrate surface of the system substrate. The first power output terminal group is arranged in the outermost peripheral row, The second power output terminal group is arranged at a position further inside than the outermost peripheral row. The first power input terminal group is arranged in the specific column, The second power input terminal group is arranged at an inner side than the specific column.

10. The circuit module according to claim 8, wherein: The circuit module also has a system substrate, and the system substrate supports the power chip module and the load chip module. The power chip module and the load chip module are respectively supported by surfaces of the system substrate facing opposite sides, and when viewed from a direction perpendicular to the substrate surface of the system substrate, the outermost peripheral column where the power output terminal group is arranged is opposite to the specific column, and the power chip module and the load chip module do not overlap. The second power output terminal group is arranged in the outermost peripheral row, The first power output terminal group is arranged at a position further inside than the outermost peripheral row. The first power input terminal group is arranged in the specific column, The second power input terminal group is arranged at an inner side than the specific column.

Images