A protected dual-output circuit and its PCB board

Abstract

The present invention discloses a protected dual-output circuit and its PCB board, including an input processing unit, a power management unit, a secondary rectification unit, a first ripple suppression unit, a second ripple suppression unit, and a feedback processing unit. An external power supply sequentially passes through the input processing unit, the power management unit, the secondary rectification unit, the first ripple suppression unit, the second ripple suppression unit. The first output pin LED1+ and the second output pin LED1- of the first ripple suppression unit, and the third output pin LED2+ and the fourth output pin LED2- of the second ripple suppression unit are respectively electrically connected to an external lamp. The feedback processing unit is arranged between the power management unit and the ripple suppression unit. By sampling and detecting the working voltages of the two outputs through the feedback processing unit, the output current of the power management unit is controlled. When a fault occurs in any one of the outputs, the power management unit automatically reduces the current to ensure that the other output can work normally.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and particularly to a dual-output circuit with protection and its PCB board. Background Art

[0002] To meet customer requirements, some lamps need to be provided with dual outputs. However, when the two outputs work simultaneously, if an open circuit or short circuit occurs in any one of the outputs, the total current output by the power supply will all flow into the other path, causing the current flowing through the LED lamp beads in the other path to exceed their rated current, thereby causing the LED lamp beads to malfunction. Therefore, if a failure occurs in any one path, the entire lamp cannot be used normally.

[0003] It can be seen that the existing technology still needs to be improved. Summary of the Invention

[0004] In view of the deficiencies of the above-mentioned prior art, the purpose of the present invention is to provide a dual-output circuit with protection, which automatically reduces the current of the power supply when a failure occurs in any one output, thereby ensuring the normal operation of the other path.

[0005] To achieve the above purpose, the present invention adopts the following technical solutions:

[0006] A dual-output circuit with protection includes an input processing unit, a power management unit, a secondary rectification unit, a first ripple suppression unit, a second ripple suppression unit, and a feedback processing unit. The external power supply sequentially passes through the input processing unit, the power management unit, the secondary rectification unit, the first ripple suppression unit, and the second ripple suppression unit. The first output pin LED1+ and the second output pin LED1- of the first ripple suppression unit and the third output pin LED2+ and the fourth output pin LED2- of the second ripple suppression unit are respectively electrically connected to an external lamp. The feedback processing unit is arranged between the power management unit and the ripple suppression unit. The feedback processing unit is respectively connected to the second output pin LED1- and the fourth output pin LED2-, and the feedback processing unit is also connected to the power management unit.

[0007] In the protected dual - output circuit described above, the feedback processing unit includes a second control chip U2, a first feedback part, a second feedback part, and a transmitting part; the power management unit includes a first control chip U1 and a receiving part; pin 2 of the second control chip U2 is connected to the second output pin LED1 - through the first feedback part, pin 4 of the second control chip U2 is connected to the fourth output pin LED2 - through the second feedback part, and the transmitting part is connected to pin 6 and pin 8 of the second control chip U2; the receiving part is connected to pin 4 of the first control chip U1, and the receiving part is connected to the transmitting part.

[0008] In the protected dual - output circuit described above, the first feedback part includes a thirty - fourth resistor R34 and an eighteenth capacitor C18; the second feedback part includes a thirty - fifth resistor R35 and a nineteenth capacitor C19; one ends of the thirty - fourth resistor R34 and the eighteenth capacitor C18 are respectively connected to pin 2 of the second control chip U2, the other end of the thirty - fourth resistor R34 is connected to the second output pin LED1 -, and the other end of the eighteenth capacitor C18 is connected to the output ground; one ends of the thirty - fifth resistor R35 and the nineteenth capacitor C19 are respectively connected to pin 4 of the second control chip U2, the other end of the thirty - fifth resistor R35 is connected to the fourth output pin LED2 -, and the other end of the nineteenth capacitor C19 is connected to the output ground.

[0009] In the described protected dual - output circuit, the transmitting part includes the thirty - sixth resistor R36, the thirty - seventh resistor R37, the tenth field - effect transistor Q12, the optocoupler transmitting end U2A, a linear voltage - regulating unit, and the fortieth resistor R40; the receiving part includes the ninth capacitor C9, the seventeenth resistor R17, the second triode Q2, the eighteenth resistor R18, and the optocoupler receiving end U2B; one end of the thirty - sixth resistor R36 is connected to pin 6 of the second control chip U2, the other end of the thirty - sixth resistor R36 is respectively connected to one end of the thirty - seventh resistor R37 and the gate of the tenth field - effect transistor Q12, the other end of the thirty - seventh resistor R37 is connected to the source of the tenth field - effect transistor Q12 and is grounded at the output, the drain of the tenth field - effect transistor Q12 is connected to pin 2 of the optocoupler transmitting end U2A, one end of the fortieth resistor R40 is connected to pin 1 of the optocoupler transmitting end U2A, the other end of the fortieth resistor R40 is respectively connected to the linear voltage - regulating unit and pin 8 of the second control chip U2, and the linear voltage - regulating unit is also connected to the output end HV+ of the secondary rectifying unit; pin 4 of the first control chip U1 is respectively connected to one end of the ninth capacitor C9, one end of the seventeenth resistor R17, and the collector of the second triode Q2, the ninth capacitor C9, the emitter of the second triode Q2, and pin 3 of the optocoupler receiving end U2B are grounded at the input, pin 4 of the optocoupler receiving end U2B is respectively connected to one end of the eighteenth resistor R18 and the base of the second triode Q2, and the other ends of the eighteenth resistor R18 and the seventeenth resistor R17 are connected to the external +18V power supply; the optocoupler transmitting end U2A is connected to the optocoupler receiving end U2B.

[0010] In the described protected dual - output circuit, an anti - interference unit is connected between the input ground and the output ground.

[0011] In the described protected dual - output circuit, the power management unit further includes the first field - effect transistor Q3 and the primary coil of the transformer T1. Pin 7 of the first control chip U1 is connected to the gate of the first field - effect transistor Q3, pin 6 of the first control chip U1 and the source of the first field - effect transistor Q3 are grounded at the input, the drain of the first field - effect transistor Q3 is connected to pin 3 of the primary coil of the transformer T1, and pin 1 of the primary coil of the transformer T1 is connected to the output end of the input processing unit.

[0012] In the described protected dual - output circuit, the power management unit further includes the feedback coil of the transformer T1. Pin 4 of the feedback coil of the transformer T1 is grounded at the input, and pin 5 of the feedback coil of the transformer T1 is respectively connected to the output end of the input processing unit, pin 5 of the first control chip U1, and pin 8 of the first control chip U1.

[0013] In the described protected dual-output circuit, the secondary rectification unit includes the secondary coil of transformer T1, the thirteenth capacitor C13, and the sixth diode D6. The pin 6 of the secondary coil of transformer T1 is connected to the positive electrode of the sixth diode D6. One end of the thirteenth capacitor C13 and the pin 8 of the secondary coil of transformer T1 are connected to the output ground, and the other end of the thirteenth capacitor C13 is connected to the negative electrode of the sixth diode D6.

[0014] In the described double - output circuit with protection, the first ripple suppression unit includes a second field - effect transistor Q4, a third field - effect transistor Q5, a fourth field - effect transistor Q6, a fifth field - effect transistor Q7, a twenty - fifth resistor R25, a twenty - sixth resistor R26, a twenty - seventh resistor R27, a twenty - eighth resistor R28, a twenty - ninth resistor R29, a seventh diode D7, an eighth diode D8, a ninth diode D9, and a fifteenth capacitor C15; the second ripple suppression unit includes a sixth field - effect transistor Q8, a seventh field - effect transistor Q9, an eighth field - effect transistor Q10, a ninth field - effect transistor Q11, a thirtieth resistor R30, a thirty - first resistor R31, a thirty - second resistor R32, a thirty - third resistor R33, a thirty - fourth resistor R34, a tenth diode D10, an eleventh diode D11, a twelfth diode D12, and a sixteenth capacitor C16; the drains of the second field - effect transistor Q4, the third field - effect transistor Q5, the fourth field - effect transistor Q6, and the fifth field - effect transistor Q7 are respectively connected to the negative electrode of the sixth diode D6, the positive electrode of the eighth diode D8, and one end of the twenty - seventh resistor R27. The negative electrode of the eighth diode D8 is connected to one end of the twenty - eighth resistor R28. The other end of the twenty - eighth resistor R28 is connected to the negative electrode of the ninth diode D9. The positive electrode of the ninth diode D9 is connected to the other end of the twenty - seventh resistor R27. The sources of the second field - effect transistor Q4, the third field - effect transistor Q5, the fourth field - effect transistor Q6, and the fifth field - effect transistor Q7 are respectively connected to the first output pin LED1 -, the positive electrode of the seventh diode D7, and one end of the twenty - fifth resistor R25. The negative electrode of the seventh diode D7 and the other end of the twenty - fifth resistor R25 are respectively connected to one end of the twenty - sixth resistor R26. The twenty - sixth resistor R26 is respectively connected to the positive electrode of the ninth diode D9, one end of the fifteenth capacitor C15, the gate of the second field - effect transistor Q4, the gate of the third field - effect transistor Q5, the gate of the fourth field - effect transistor Q6, and the gate of the fifth field - effect transistor Q7. The other end of the fifteenth capacitor C15 and one end of the twenty - ninth resistor R29 are connected to the output ground. The other end of the twenty - ninth resistor R29 is connected to the second output pin LED1 -;The drains of the sixth field-effect transistor Q8, the seventh field-effect transistor Q9, the eighth field-effect transistor Q10, and the ninth field-effect transistor Q11 are respectively connected to the negative electrode of the sixth diode D6, the positive electrode of the eleventh diode D11, and one end of the thirty-second resistor R32. The negative electrode of the eleventh diode D11 is connected to one end of the thirty-third resistor R33. The other end of the thirty-third resistor R33 is connected to the negative electrode of the twelfth diode D12. The positive electrode of the twelfth diode D12 is connected to the other end of the thirty-second resistor R32. The sources of the sixth field-effect transistor Q8, the seventh field-effect transistor Q9, the eighth field-effect transistor Q10, and the ninth field-effect transistor Q11 are respectively connected to the third output pin LED2-, the positive electrode of the twelfth diode D10, and one end of the thirtieth resistor R30. The negative electrode of the twelfth diode D10 and the other end of the thirtieth resistor R30 are respectively connected to one end of the thirty-first resistor R31. The thirty-first resistor R31 is respectively connected to the positive electrode of the twelfth diode D12, one end of the sixteenth capacitor C16, the gate of the sixth field-effect transistor Q8, the gate of the seventh field-effect transistor Q9, the gate of the eighth field-effect transistor Q10, and the gate of the ninth field-effect transistor Q11. The other end of the sixteenth capacitor C16 and one end of the thirty-fourth resistor R34 are connected to the output ground. The other end of the thirty-fourth resistor R34 is connected to the fourth output pin LED2-.

[0015] The present application also provides a PCB board printed with the protected dual-output circuit as described above.

[0016] Beneficial effects:

[0017] The present invention provides a protected dual-output circuit. The feedback processing unit samples and detects the working voltages of the two outputs, compares the sampled voltages with the normal working voltages, generates a PWM signal, and thus controls the output current of the power management unit. When a fault occurs in any one of the outputs, the power management unit automatically reduces the current to ensure that the other output can work normally. Description of the Drawings

[0018] Figure 1 It is a circuit structure diagram of the protected dual-output circuit provided by the present invention.

[0019] Figure 2 It is a circuit structure diagram of the input processing unit in the protected dual-output circuit provided by the present invention.

[0020] Figure 3 It is a circuit structure diagram of the power management unit in the protected dual-output circuit provided by the present invention.

[0021] Figure 4 This is the circuit structure diagram of the secondary rectification unit in the protected dual-output circuit provided by the present invention.

[0022] Figure 5 This is the circuit structure diagram of the first ripple suppression unit and the second ripple suppression unit in the protected dual-output circuit provided by the present invention.

[0023] Figure 6 This is the circuit structure diagram of the feedback processing unit in the protected dual-output circuit provided by the present invention. Detailed implementation manners

[0024] The present invention provides a protected dual-output circuit and its PCB board. To make the objectives, technical solutions and effects of the present invention clearer and more definite, the following further describes the present invention in detail with reference to the accompanying drawings and by way of examples. It should be understood that the specific examples described herein are only used to explain the present invention and are not used to limit the present invention.

[0025] In the description of the present invention, it should be understood that the terms "first", "second", and "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features.

[0026] Please refer to Figures 1 to 6 , the present invention provides a protected dual-output circuit, including an input processing unit, a power management unit, a secondary rectification unit, a first ripple suppression unit, a second ripple suppression unit, and a feedback processing unit. The external power supply sequentially passes through the input processing unit, the power management unit, the secondary rectification unit, the first ripple suppression unit, and the second ripple suppression unit. The first output pin LED1+ and the second output pin LED1- of the first ripple suppression unit and the third output pin LED2+ and the fourth output pin LED2- of the second ripple suppression unit are respectively electrically connected to an external lamp. The feedback processing unit is disposed between the power management unit and the ripple suppression unit. The feedback processing unit is respectively connected to the second output pin LED1- and the fourth output pin LED2-, and the feedback processing unit is also connected to the power management unit.

[0027] The working principle of this application is as follows: The feedback processing unit samples the working voltages of the second output pin LED1- and the fourth output pin LED2- respectively, that is, samples the working voltages of the lamps connected to the first ripple suppression unit and the lamps connected to the second ripple suppression unit (hereinafter referred to as: LED1 and LED2). If either LED1 or LED2 has a short circuit, the power management unit enters a protection state to prevent the overall circuit and the lamps from burning out. If either LED1 or LED2 has an open circuit, since the open circuit voltage is higher than the voltage in the normal loaded state, when the feedback processing unit samples and detects that the working voltage of either the second output pin LED1- or the fourth output pin LED2- is higher than the voltage in the normal loaded state, it will send a 50% PWM signal to the power management unit, reducing the output current of the power management unit by half to ensure that the normal path can work properly. If both LED1 and LED2 are in a normal state, when the feedback processing unit samples and detects that the working voltages of the second output pin LED1- and the fourth output pin LED2- are equal to the voltage in the normal loaded state, it will send a 0% PWM signal to the power management unit, enabling the power management unit to normally output 100% current to ensure that both LED1 and LED2 can work properly. That is, the feedback processing unit samples and detects the working voltages of the two outputs, compares the sampled voltages with the normal working voltages, generates a PWM signal, and thus controls the output current of the power management unit. When a fault occurs in any one of the outputs, the power management unit automatically reduces the current to ensure that the other path can work properly.

[0028] In one embodiment, the input processing unit includes a protection section, a common-mode noise cancellation section, a rectification section, and a filtering section.

[0029] Such as Figure 1 、 Figure 5 、 Figure 6As shown, further, the feedback processing unit includes a second control chip U2, a first feedback part, a second feedback part, and a transmitting part; the power management unit includes a first control chip U1 and a receiving part; pin 2 of the second control chip U2 is connected to the second output pin LED1- through the first feedback part, pin 4 of the second control chip U2 is connected to the fourth output pin LED2- through the second feedback part, and the transmitting part is connected to pins 6 and 8 of the second control chip U2; the receiving part is connected to pin 4 of the first control chip U1, and the receiving part is connected to the transmitting part; the working voltages of the second output pin LED1- and the fourth output pin LED2- are sampled and detected through the first feedback part and the second feedback part, and a PWM signal is sent to the receiving part through the transmitting part to realize the communication between the feedback processing unit and the power management unit; in an embodiment, the model of the first control chip U1 can be RT7331, and the model of the second control chip U2 can be KG003.

[0030] As Figure 1 , Figure 5 , Figure 6 As shown, further, the first feedback part includes a thirty-fourth resistor R34 and an eighteenth capacitor C18; the second feedback part includes a thirty-fifth resistor R35 and a nineteenth capacitor C19; one ends of the thirty-fourth resistor R34 and the eighteenth capacitor C18 are respectively connected to pin 2 of the second control chip U2, the other end of the thirty-fourth resistor R34 is connected to the second output pin LED1-, and the other end of the eighteenth capacitor C18 is connected to the output ground; one ends of the thirty-fifth resistor R35 and the nineteenth capacitor C19 are respectively connected to pin 4 of the second control chip U2, the other end of the thirty-fifth resistor R35 is connected to the fourth output pin LED2-, and the other end of the nineteenth capacitor C19 is connected to the output ground.

[0031] As Figure 1 , Figure 3 , Figure 6As shown, further, the transmitting part includes a thirty-sixth resistor R36, a thirty-seventh resistor R37, a tenth field-effect transistor Q12, an optocoupler transmitting end U2A, a linear voltage stabilizing unit, and a fortieth resistor R40; the receiving part includes a ninth capacitor C9, a seventeenth resistor R17, a second triode Q2, an eighteenth resistor R18, and an optocoupler receiving end U2B; one end of the thirty-sixth resistor R36 is connected to pin 6 of the second control chip U2, the other end of the thirty-sixth resistor R36 is respectively connected to one end of the thirty-seventh resistor R37 and the gate of the tenth field-effect transistor Q12, the other end of the thirty-seventh resistor R37 is connected to the source of the tenth field-effect transistor Q12 to the output ground, the drain of the tenth field-effect transistor Q12 is connected to pin 2 of the optocoupler transmitting end U2A, one end of the fortieth resistor R40 is connected to pin 1 of the optocoupler transmitting end U2A, the other end of the fortieth resistor R40 is respectively connected to the linear voltage stabilizing unit and pin 8 of the second control chip U2, and the linear voltage stabilizing unit is also connected to the output end HV+ of the secondary rectifying unit; pin 4 of the first control chip U1 is respectively connected to one end of the ninth capacitor C9, one end of the seventeenth resistor R17, and the collector of the second triode Q2, the ninth capacitor C9, the emitter of the second triode Q2, and pin 3 of the optocoupler receiving end U2B are connected to the input ground, pin 4 of the optocoupler receiving end U2B is respectively connected to one end of the eighteenth resistor R18 and the base of the second triode Q2, and the other ends of the eighteenth resistor R18 and the seventeenth resistor R17 are connected to the external +18V power supply; the optocoupler transmitting end U2A is connected to the optocoupler receiving end U2B; a PWM signal is transmitted through the optocoupler transmitting end U2A and the optocoupler receiving end U2B; the voltage of the output end HV+ of the secondary rectifying unit is regulated by the linear voltage stabilizing unit and then supplies power to the second control chip U2.

[0032] In one embodiment, the linear voltage regulator unit includes a thirty-eighth resistor R38, a thirty-ninth resistor R39, a second zener diode ZD2, a thirteenth transistor Q13, and a thirteenth diode D13. One end of the fortieth resistor R40 is connected to pin 1 of the optocoupler emitter U2A, the other end of the fortieth resistor R40 is connected to the cathode of the thirteenth diode D13 and pin 8 of the second control chip U2, the anode of the thirteenth diode D13 is connected to the emitter of the thirteenth transistor Q13, the base of the thirteenth transistor Q13 is connected to one end of the thirty-ninth resistor R39 and the cathode of the second zener diode ZD2, the collector of the thirteenth transistor Q13 is connected to the other end of the thirty-ninth resistor R39 and one end of the thirty-eighth resistor R38, the anode of the second zener diode ZD2 is connected to the output ground, and the other end of the thirty-eighth resistor R38 is connected to the output terminal HV+ of the secondary rectification unit.

[0033] As Figure 1 shown, further, an anti-interference unit is connected between the input ground and the output ground; the common-mode noise on both sides of the transformer T1 is reduced through the anti-interference unit; in one embodiment, the anti-interference unit includes an eleventh capacitor C11.

[0034] As Figure 1 、 Figure 2 、 Figure 3 shown, further, the power management unit further includes a first field-effect transistor Q3 and the primary coil of the transformer T1. Pin 7 of the first control chip U1 is connected to the gate of the first field-effect transistor Q3, pin 6 of the first control chip U1 and the source of the first field-effect transistor Q3 are connected to the input ground, the drain of the first field-effect transistor Q3 is connected to pin 3 of the primary coil of the transformer T1, and pin 1 of the primary coil of the transformer T1 is connected to the output terminal of the input processing unit.

[0035] In one embodiment, the power management unit further includes an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, and a third diode D3. One end of the eleventh resistor R11 is connected to pin 7 of the first control chip U1. The other end of the eleventh resistor R11 is respectively connected to the cathode of the third diode D3 and one end of the twelfth resistor R12. The gate of the first field effect transistor Q3 is respectively connected to one end of the fifteenth resistor R15, the anode of the third diode D3, and the other end of the twelfth resistor R12. One end of the sixteenth resistor R16 is connected to pin 6 of the first control chip U1. The other end of the sixteenth resistor R16 is respectively connected to the other end of the fifteenth resistor R15, one end of the fourteenth resistor R14, one end of the thirteenth resistor R13, and the source of the first field effect transistor Q3. The other ends of the fourteenth resistor R14 and the thirteenth resistor R13 are connected to the input ground.

[0036] As Figure 1 and Figure 3 shown, further, the power management unit further includes a feedback coil of the transformer T1. Pin 4 of the feedback coil of the transformer T1 is connected to the input ground. Pin 5 of the feedback coil of the transformer T1 is respectively connected to the output end of the input processing unit, pin 5 of the first control chip U1, and pin 8 of the first control chip U1.

[0037] In one embodiment, the power management unit further includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a sixth capacitor C6, a seventh capacitor C7, a first diode D1, a second diode D2, a first zener diode ZD1, and a first triode Q1. The fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 are sequentially connected in series between the output terminal of the input processing unit and pin 8 of the first control chip U1. One end of the ninth resistor R9 and one end of the eighth resistor R8 are respectively connected to pin 5 of the first control chip U1. The other end of the ninth resistor R9 is connected to the input ground. The other end of the eighth resistor R8 is respectively connected to pin 5 of the feedback coil of the transformer T1 and the anode of the second diode D2. The cathode of the second diode D2 is respectively connected to the anode of the seventh capacitor C7, one end of the seventh resistor R7, and the collector of the first triode Q1. The other end of the seventh resistor R7 is respectively connected to the base of the first triode Q1 and the cathode of the first zener diode ZD1. The emitter of the first triode Q1 is connected to the anode of the first diode D1. The cathode of the first diode D1 is respectively connected to the anode of the sixth capacitor C6 and pin 8 of the first control chip U1. The cathode of the seventh capacitor C7, the cathode of the first zener diode ZD1, and the cathode of the sixth capacitor C6 are connected to the input ground.

[0038] In one embodiment, the power management unit further includes a tenth resistor R10 and an eighth capacitor C8. One end of the tenth resistor R10 is connected to pin 1 of the first control chip U1. One end of the eighth capacitor C8 is connected to pin 3 of the first control chip U1. Pin 2 of the first control chip U1, the other end of the tenth resistor R10, and the other end of the eighth capacitor C8 are connected to the input ground.

[0039] As Figure 1 and Figure 4 shown, further, the secondary rectification unit includes the secondary coil of the transformer T1, a thirteenth capacitor C13, and a sixth diode D6. Pin 6 of the secondary coil of the transformer T1 is connected to the anode of the sixth diode D6. One end of the thirteenth capacitor C13 and pin 8 of the secondary coil of the transformer T1 are connected to the output ground. The other end of the thirteenth capacitor C13 is connected to the cathode of the sixth diode D6. The voltage of the secondary coil of the transformer T1 is stored and released through the thirteenth capacitor C13.

[0040] As Figure 1 、 、 Figure 4 Figure 5As shown, further, the first ripple suppression unit includes a second field effect transistor Q4, a third field effect transistor Q5, a fourth field effect transistor Q6, a fifth field effect transistor Q7, a twenty-fifth resistor R25, a twenty-sixth resistor R26, a twenty-seventh resistor R27, a twenty-eighth resistor R28, a twenty-ninth resistor R29, a seventh diode D7, an eighth diode D8, a ninth diode D9, and a fifteenth capacitor C15; the second ripple suppression unit includes a sixth field effect transistor Q8, a seventh field effect transistor Q9, an eighth field effect transistor Q10, a ninth field effect transistor Q11, a thirtieth resistor R30, a thirty-first resistor R31, a thirty-second resistor R32, a thirty-third resistor R33, a thirty-fourth resistor R34, a tenth diode D10, an eleventh diode D11, a twelfth diode D12, and a sixteenth capacitor C16; the drains of the second field effect transistor Q4, the third field effect transistor Q5, the fourth field effect transistor Q6, and the fifth field effect transistor Q7 are respectively connected to the negative electrode of the sixth diode D6, the positive electrode of the eighth diode D8, and one end of the twenty-seventh resistor R27. The negative electrode of the eighth diode D8 is connected to one end of the twenty-eighth resistor R28. The other end of the twenty-eighth resistor R28 is connected to the negative electrode of the ninth diode D9. The positive electrode of the ninth diode D9 is connected to the other end of the twenty-seventh resistor R27. The sources of the second field effect transistor Q4, the third field effect transistor Q5, the fourth field effect transistor Q6, and the fifth field effect transistor Q7 are respectively connected to the first output pin LED1-, the positive electrode of the seventh diode D7, and one end of the twenty-fifth resistor R25. The negative electrode of the seventh diode D7 and the other end of the twenty-fifth resistor R25 are respectively connected to one end of the twenty-sixth resistor R26. The twenty-sixth resistor R26 is respectively connected to the positive electrode of the ninth diode D9, one end of the fifteenth capacitor C15, the gate of the second field effect transistor Q4, the gate of the third field effect transistor Q5, the gate of the fourth field effect transistor Q6, and the gate of the fifth field effect transistor Q7. The other end of the fifteenth capacitor C15 and one end of the twenty-ninth resistor R29 are connected to the output ground. The other end of the twenty-ninth resistor R29 is connected to the second output pin LED1-;The drains of the sixth field effect transistor Q8, the seventh field effect transistor Q9, the eighth field effect transistor Q10, and the ninth field effect transistor Q11 are respectively connected to the negative electrode of the sixth diode D6, the positive electrode of the eleventh diode D11, and one end of the thirty-second resistor R32. The negative electrode of the eleventh diode D11 is connected to one end of the thirty-third resistor R33. The other end of the thirty-third resistor R33 is connected to the negative electrode of the twelfth diode D12. The positive electrode of the twelfth diode D12 is connected to the other end of the thirty-second resistor R32. The sources of the sixth field effect transistor Q8, the seventh field effect transistor Q9, the eighth field effect transistor Q10, and the ninth field effect transistor Q11 are respectively connected to the third output pin LED2-, the positive electrode of the twelfth diode D10, and one end of the thirtieth resistor R30. The negative electrode of the twelfth diode D10 and the other end of the thirtieth resistor R30 are respectively connected to one end of the thirty-first resistor R31. The thirty-first resistor R31 is respectively connected to the positive electrode of the twelfth diode D12, one end of the sixteenth capacitor C16, the gate of the sixth field effect transistor Q8, the gate of the seventh field effect transistor Q9, the gate of the eighth field effect transistor Q10, and the gate of the ninth field effect transistor Q11. The other end of the sixteenth capacitor C16 and one end of the thirty-fourth resistor R34 are connected to the output ground. The other end of the thirty-fourth resistor R34 is connected to the fourth output pin LED2-. When in use, the secondary rectification unit stores energy through the thirteenth capacitor C10. When the rectification voltage of the thirteenth capacitor C10 reaches the turn-on voltage of the second field effect transistor Q4, the third field effect transistor Q5, the fourth field effect transistor Q6, the fifth field effect transistor Q7, the sixth field effect transistor Q8, the seventh field effect transistor Q9, the eighth field effect transistor Q10, and the ninth field effect transistor Q11, the drain currents of the second field effect transistor Q4, the third field effect transistor Q5, the fourth field effect transistor Q6, the fifth field effect transistor Q7, the sixth field effect transistor Q8, the seventh field effect transistor Q9, the eighth field effect transistor Q10, and the ninth field effect transistor Q11 increase. Since the total current output to LED1 and LED2 remains constant, in order to maintain energy conservation, the second field effect transistor Q4, the third field effect transistor Q5, the fourth field effect transistor Q6, the fifth field effect transistor Q7, the sixth field effect transistor Q8, the seventh field effect transistor Q9, the eighth field effect transistor Q10, and the ninth field effect transistor Q11 will absorb part of the ripple current flowing in from the secondary rectification unit, thereby playing a role in suppressing the ripple.

[0041] The present application also provides a switching power supply PCB board printed with the dual-output circuit with protection as described above.

[0042] In summary, the feedback processing unit samples and detects the working voltages of the two outputs, compares the sampled voltages with the normal working voltages, generates a PWM signal, thereby controlling the output current of the power management unit. When a fault occurs in any one of the outputs, the power management unit automatically reduces the current to ensure that the other output can work normally.

[0043] It can be understood that for those of ordinary skill in the art, equivalent substitutions or changes can be made according to the technical solutions and inventive concepts of the present invention, and all such changes or substitutions should fall within the protection scope of the appended claims of the present invention.

Claims

1. A protected dual-output circuit, characterized in that It includes an input processing unit, a power management unit, a secondary rectification unit, a first ripple suppression unit, a second ripple suppression unit, and a feedback processing unit. The external power supply sequentially passes through the input processing unit, the power management unit, the secondary rectification unit, the first ripple suppression unit, and the second ripple suppression unit. The first output pin LED1+ and the second output pin LED1- of the first ripple suppression unit, and the third output pin LED2+ and the fourth output pin LED2- of the second ripple suppression unit are respectively electrically connected to an external lamp. The feedback processing unit is arranged between the power management unit and the ripple suppression unit. The feedback processing unit is respectively connected to the second output pin LED1- and the fourth output pin LED2-, and the feedback processing unit is also connected to the power management unit; The feedback processing unit includes a second control chip U2, a first feedback part, a second feedback part, and a transmitting part; the power management unit includes a first control chip U1 and a receiving part; the pin 2 of the second control chip U2 is connected to the second output pin LED1- through the first feedback part, the pin 4 of the second control chip U2 is connected to the fourth output pin LED2- through the second feedback part, and the transmitting part is connected to the pin 6 and the pin 8 of the second control chip U2; the receiving part is connected to the pin 4 of the first control chip U1, and the receiving part is connected to the transmitting part; The model of the first control chip U1 is RT7331, and the model of the second control chip U2 is KG003; If the feedback processing unit samples and detects that the working voltage of any one of the second output pin LED1- and the fourth output pin LED2- is higher than the voltage in the normal loaded state, it will send a 50% PWM signal to the power management unit, so that the output current of the power management unit is reduced by half, ensuring that one path in the normal state can work properly.

2. The protected dual-output circuit according to claim 1, wherein The first feedback part includes a thirty-fourth resistor R34 and an eighteenth capacitor C18; the second feedback part includes a thirty-fifth resistor R35 and a nineteenth capacitor C19; one ends of the thirty-fourth resistor R34 and the eighteenth capacitor C18 are respectively connected to the pin 2 of the second control chip U2, the other end of the thirty-fourth resistor R34 is connected to the second output pin LED1-, and the other end of the eighteenth capacitor C18 is connected to the output ground; one ends of the thirty-fifth resistor R35 and the nineteenth capacitor C19 are respectively connected to the pin 4 of the second control chip U2, the other end of the thirty-fifth resistor R35 is connected to the fourth output pin LED2-, and the other end of the nineteenth capacitor C19 is connected to the output ground.

3. The protected dual-output circuit according to claim 2, wherein The transmitting part includes the thirty-sixth resistor R36, the thirty-seventh resistor R37, the tenth field-effect transistor Q12, the optocoupler transmitting end U2A, the linear voltage regulation unit, and the fortieth resistor R40; the receiving part includes the ninth capacitor C9, the seventeenth resistor R17, the second triode Q2, the eighteenth resistor R18, and the optocoupler receiving end U2B; one end of the thirty-sixth resistor R36 is connected to pin 6 of the second control chip U2, the other end of the thirty-sixth resistor R36 is respectively connected to one end of the thirty-seventh resistor R37 and the gate of the tenth field-effect transistor Q12, the other end of the thirty-seventh resistor R37 is connected to the source of the tenth field-effect transistor Q12 to the output ground, the drain of the tenth field-effect transistor Q12 is connected to pin 2 of the optocoupler transmitting end U2A, one end of the fortieth resistor R40 is connected to pin 1 of the optocoupler transmitting end U2A, the other end of the fortieth resistor R40 is respectively connected to the linear voltage regulation unit and pin 8 of the second control chip U2, and the linear voltage regulation unit is also connected to the output end HV+ of the secondary rectification unit; pin 4 of the first control chip U1 is respectively connected to one end of the ninth capacitor C9, one end of the seventeenth resistor R17, and the collector of the second triode Q2, the ninth capacitor C9, the emitter of the second triode Q2, and pin 3 of the optocoupler receiving end U2B are connected to the input ground, pin 4 of the optocoupler receiving end U2B is respectively connected to one end of the eighteenth resistor R18 and the base of the second triode Q2, and the other ends of the eighteenth resistor R18 and the seventeenth resistor R17 are connected to the external +18V power supply; the optocoupler transmitting end U2A is connected to the optocoupler receiving end U2B.

4. The protected dual-output circuit according to claim 3, characterized in that, An anti-interference unit is connected between the input ground and the output ground.

5. The protected dual-output circuit according to claim 4, wherein The power management unit further includes the first field-effect transistor Q3 and the primary coil of the transformer T1. Pin 7 of the first control chip U1 is connected to the gate of the first field-effect transistor Q3, pin 6 of the first control chip U1 and the source of the first field-effect transistor Q3 are connected to the input ground, the drain of the first field-effect transistor Q3 is connected to pin 3 of the primary coil of the transformer T1, and pin 1 of the primary coil of the transformer T1 is connected to the output end of the input processing unit.

6. The protected dual-output circuit according to claim 5, wherein The power management unit further includes the feedback coil of the transformer T1. Pin 4 of the feedback coil of the transformer T1 is connected to the input ground, and pin 5 of the feedback coil of the transformer T1 is respectively connected to the output end of the input processing unit, pin 5 of the first control chip U1, and pin 8 of the first control chip U1.

7. The protected dual-output circuit according to claim 5, characterized in that, The secondary rectification unit includes the secondary coil of the transformer T1, the thirteenth capacitor C13, and the sixth diode D6. Pin 6 of the secondary coil of the transformer T1 is connected to the positive electrode of the sixth diode D6, one end of the thirteenth capacitor C13 and pin 8 of the secondary coil of the transformer T1 are connected to the output ground, and the other end of the thirteenth capacitor C13 is connected to the negative electrode of the sixth diode D6.

8. The protected dual-output circuit according to claim 7, characterized in that, The first ripple suppression unit includes a second field effect transistor Q4, a third field effect transistor Q5, a fourth field effect transistor Q6, a fifth field effect transistor Q7, a twenty-fifth resistor R25, a twenty-sixth resistor R26, a twenty-seventh resistor R27, a twenty-eighth resistor R28, a twenty-ninth resistor R29, a seventh diode D7, an eighth diode D8, a ninth diode D9, and a fifteenth capacitor C15; the second ripple suppression unit includes a sixth field effect transistor Q8, a seventh field effect transistor Q9, an eighth field effect transistor Q10, a ninth field effect transistor Q11, a thirtieth resistor R30, a thirty-first resistor R31, a thirty-second resistor R32, a thirty-third resistor R33, a thirty-fourth resistor R34, a tenth diode D10, an eleventh diode D11, a twelfth diode D12, and a sixteenth capacitor C16; the drains of the second field effect transistor Q4, the third field effect transistor Q5, the fourth field effect transistor Q6, and the fifth field effect transistor Q7 are respectively connected to the negative electrode of the sixth diode D6, the positive electrode of the eighth diode D8, and one end of the twenty-seventh resistor R27. The negative electrode of the eighth diode D8 is connected to one end of the twenty-eighth resistor R28. The other end of the twenty-eighth resistor R28 is connected to the negative electrode of the ninth diode D9. The positive electrode of the ninth diode D9 is connected to the other end of the twenty-seventh resistor R27. The sources of the second field effect transistor Q4, the third field effect transistor Q5, the fourth field effect transistor Q6, and the fifth field effect transistor Q7 are respectively connected to the first output pin LED1-, the positive electrode of the seventh diode D7, and one end of the twenty-fifth resistor R25. The negative electrode of the seventh diode D7 and the other end of the twenty-fifth resistor R25 are respectively connected to one end of the twenty-sixth resistor R26. The twenty-sixth resistor R26 is respectively connected to the positive electrode of the ninth diode D9, one end of the fifteenth capacitor C15, the gate of the second field effect transistor Q4, the gate of the third field effect transistor Q5, the gate of the fourth field effect transistor Q6, and the gate of the fifth field effect transistor Q7. The other end of the fifteenth capacitor C15 and one end of the twenty-ninth resistor R29 are connected to the output ground. The other end of the twenty-ninth resistor R29 is connected to the second output pin LED1-;The drains of the sixth field effect transistor Q8, the seventh field effect transistor Q9, the eighth field effect transistor Q10, and the ninth field effect transistor Q11 are respectively connected to the negative electrode of the sixth diode D6, the positive electrode of the eleventh diode D11, and one end of the thirty-second resistor R32. The negative electrode of the eleventh diode D11 is connected to one end of the thirty-third resistor R33. The other end of the thirty-third resistor R33 is connected to the negative electrode of the twelfth diode D12. The positive electrode of the twelfth diode D12 is connected to the other end of the thirty-second resistor R32. The sources of the sixth field effect transistor Q8, the seventh field effect transistor Q9, the eighth field effect transistor Q10, and the ninth field effect transistor Q11 are respectively connected to the third output pin LED2-, the positive electrode of the twelfth diode D10, and one end of the thirtieth resistor R30. The negative electrode of the twelfth diode D10 and the other end of the thirtieth resistor R30 are respectively connected to one end of the thirty-first resistor R31. The thirty-first resistor R31 is respectively connected to the positive electrode of the twelfth diode D12, one end of the sixteenth capacitor C16, the gates of the sixth field effect transistor Q8, the seventh field effect transistor Q9, the eighth field effect transistor Q10, and the ninth field effect transistor Q11. The other end of the sixteenth capacitor C16 and one end of the thirty-fourth resistor R34 are connected to the output ground. The other end of the thirty-fourth resistor R34 is connected to the fourth output pin LED2-.

9. A PCB board, characterized in that, The printed circuit board (PCB) is printed with the protected dual-output circuit as described in any one of claims 1-8.

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