Signal processing device and touch display device thereof

Abstract

The present invention provides a signal processing device, comprising a first signal processing circuit and a second signal processing circuit. The first signal processing circuit receives a first signal. The first signal processing circuit has a power supply terminal connected to a first voltage and a reference ground terminal. The second signal processing circuit receives a second signal. The second signal processing circuit has a power supply terminal electrically coupled to the reference ground terminal of the first signal processing circuit or equivalent to the reference ground terminal of the first signal processing circuit. The second signal processing circuit has a reference ground terminal connected to a second voltage.

Description

Technical Field

[0001] The present invention relates to a signal processing device and a touch display device thereof, and more particularly, to a signal processing device for reducing power consumption. Background Art

[0002] In a conventional touch display device, a data driving circuit is arranged to generate a plurality of data voltages for driving display pixels of a touch display panel, wherein a portion of the data voltages is positive polarity and another portion of the data voltages is negative polarity, and a plurality of touch analog front-end (AFE) circuits are arranged and configured to process touch sensing signals from touch sensors on the touch display panel. The power consumption of each touch AFE circuit depends on the same voltage range, which is usually half of the supply voltage range of the data driving circuit and still generates a large power consumption. Summary of the invention

[0003] The present invention provides a signal processing device capable of saving more power and a touch display device thereof.

[0004] According to an embodiment of the present invention, a signal processing device includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit receives a first signal. The first signal processing circuit has a power supply terminal connected to a first voltage and a reference ground terminal. The second signal processing circuit receives a second signal. The second signal processing circuit has a power supply terminal electrically coupled to the reference ground terminal of the first signal processing circuit or equivalent to the reference ground terminal of the first signal processing circuit. The second signal processing circuit has a reference ground terminal connected to a second voltage.

[0005] According to another embodiment of the present invention, a touch display device includes a display panel and a touch display driving device. The display panel is integrated with a touch sensor array, wherein the touch sensor array includes a plurality of touch electrodes. The touch display driving device includes a first touch analog front-end circuit and a second touch analog front-end circuit. The first touch analog front-end circuit is coupled to a first touch electrode of the touch sensor array for receiving a first signal from the first touch electrode, wherein the first signal processing circuit has a power supply terminal connected to a first voltage and a reference ground terminal. The second touch analog front-end circuit is coupled to a second touch electrode of the touch sensor array for receiving a second signal from the second touch electrode, wherein the second signal processing circuit has a power supply terminal electrically coupled to a reference ground terminal of the first signal processing circuit or equivalent to the reference ground terminal of the first signal processing circuit, and the second signal processing circuit has a reference ground terminal connected to a second voltage.

[0006] In summary, the power supply terminals of the first signal processing circuit and the second signal processing circuit are coupled in series. The operating current of the first signal processing circuit can be reused by the second signal processing circuit. In this way, the power consumption of the signal processing device can be reduced.

[0007] In order to better understand the above features and advantages of the present invention, embodiments accompanied by drawings are described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0009] Figure 1 is a schematic diagram of a signal processing device according to an embodiment of the present disclosure.

[0010] Figure 2 is a schematic diagram of a signal processing device according to another embodiment of the present disclosure.

[0011] Figure 3 is a circuit diagram of a signal processing device according to an embodiment of the present disclosure.

[0012] Figure 4A is a circuit diagram of another signal processing device according to an embodiment of the present disclosure.

[0013] Figure 4B is a circuit diagram of another signal processing device according to an embodiment of the present disclosure.

[0014] Figure 4C According to the present disclosure Figure 4A Another circuit diagram of the first signal processing circuit 410 of an embodiment of the present invention.

[0015] Figure 4D According to the present disclosure Figure 4B Another circuit diagram of the first signal processing circuit 430 of an embodiment of the present invention.

[0016] Figure 5 is a schematic diagram of another signal processing device according to an embodiment of the present disclosure.

[0017] Figure 6 is a schematic diagram of another signal processing device according to another embodiment of the present disclosure.

[0018] FIG. 7A to FIG. 7C Schematic diagram of multiple touch display driving devices according to different embodiments of the present disclosure.

[0019] Description of Figure Numbers

[0020] 100, 200, 300, 401, 402, 500, 600: signal processing equipment;

[0021] 110, 210, 310, 410, 430, 510, 610: a first signal processing circuit;

[0022] 120, 220, 320, 420, 440, 520, 620: second signal processing circuit;

[0023] 211, 311, 411, 431: first current conveyor;

[0024] 212, 312, 412, 432: first accumulator;

[0025] 221, 321, 421, 441: second current transmitter;

[0026] 222, 322, 422, 442: second accumulator;

[0027] 413, 433: Current mirror circuit;

[0028] 531: a first sampling and holding circuit;

[0029] 532: a first analog-to-digital converter;

[0030] 541: a second sampling and holding circuit;

[0031] 542: a second analog-to-digital converter;

[0032] 630: a third signal processing circuit;

[0033] 701, 702, 703: touch display driving device;

[0034] 711, 721: driving channel;

[0035] 712, 722: touch analog front end circuit;

[0036] 3111, 3211: voltage follower;

[0037] 3112, 3212: output buffer;

[0038] 4131, 4132, 4331, 4332: voltage clamping circuit;

[0039] CCS1: first current signal;

[0040] CCS2: second current signal;

[0041] CF11, CF12, CF21, CF22, C S1 , CS2 : capacitor;

[0042] GNDA, TVSS: second voltage;

[0043] HTVDD, HVDDA: third voltage;

[0044] HTVDD_ADC: fifth voltage;

[0045] IS1: first signal;

[0046] IS2: Second signal;

[0047] IS3: Third signal;

[0048] MN1, MN2, MN3, MN4, MN41, MN42, MN43, MN44, MP1, MP2, MP3, MP4, MP41, MP42, MP43, MP44: transistor;

[0049] OC: operating current;

[0050] OP1, OP2, OP3, OP4: operational amplifiers;

[0051] OS1: first output signal;

[0052] OS2: second output signal;

[0053] PE1, PE2: power supply end;

[0054] PR1, PR2, PR3, PR4, PR5: power rails;

[0055] RGE1, RGE2: reference ground terminals;

[0056] T[n], T[n+1]: touch electrodes;

[0057] TVDD, VDDA: first voltage;

[0058] TVDD_ADC: fourth voltage;

[0059] TVSS_ADC: sixth voltage;

[0060] VB1: first bias voltage;

[0061] VB2: second bias voltage;

[0062] VB3: third bias voltage;

[0063] VB4: fourth bias voltage;

[0064] VO1, VON1, VOP1: first accumulation result signal;

[0065] VO2, VON2, VOP2: second accumulation result signal;

[0066] V REF 、V REFN 、V REFP : reference signal;

[0067] V TX : driving signal;

[0068] ΔC S1 , ΔC S2 : Capacitance change. DETAILED DESCRIPTION

[0069] The term "coupling (or connection)" throughout the specification (including claims) of the present application is widely used, and covers direct and indirect connections or coupling members. For example, if the present disclosure describes that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or by a coupling member. In addition, the terms such as "first" and "second" mentioned throughout the specification (including claims) of the present application are only used to name the name of the element or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of elements, and are not intended to limit the order of the elements. In addition, the elements / components / steps with the same figure numbers represent the same or similar parts in the drawings and embodiments. The elements / components / symbols with the same figure numbers in different embodiments can refer to the relevant description.

[0070] Figure 1 Schematic diagram of a signal processing device according to an embodiment of the present disclosure. The signal processing device 100 includes a first signal processing circuit 110 and a second signal processing circuit 120. The first signal processing circuit 110 receives a first signal IS1. The first signal processing circuit 110 has a power supply terminal PE1 connected to a first voltage TVDD, and the first signal processing circuit 110 has a reference ground terminal RGE1. On the other hand, the second signal processing circuit 120 receives a second signal IS2. The second signal processing circuit 120 has a power supply terminal PE2, and the power supply terminal PE2 is coupled to the reference ground terminal RGE1 of the first signal processing circuit 110. The second signal processing circuit 120 also has a reference ground terminal RGE2 coupled to a second voltage TVSS.

[0071] In this embodiment, the voltage level of the first voltage TVDD is higher than the voltage level of the second voltage TVSS. The voltage level at the power supply terminal PE1 is lower than the voltage level of the first voltage TVDD, and the voltage level at the power supply terminal PE1 is higher than the voltage level of the second voltage TVSS.

[0072] In one embodiment, the reference ground terminal RGE1 of the first signal processing circuit 110 may be coupled to the power supply terminal PE2 of the second signal processing circuit 120. In another embodiment, the reference ground terminal RGE1 of the first signal processing circuit 110 may be equal to the power supply terminal PE2 of the second signal processing circuit 120. That is, the reference ground terminal RGE1 of the first signal processing circuit 110 and the power supply terminal PE2 of the second signal processing circuit 120 are the same terminal. Figure 1 , the reference ground terminal RGE1 of the first signal processing circuit 110 and the power supply terminal PE2 of the second signal processing circuit 120 are commonly coupled to the third voltage HTVDD, wherein the voltage level of the third voltage HTVDD is between the voltage levels of the first voltage TVDD and the second voltage TVSS. In some embodiments, the voltage level of the third voltage HTVDD may be equal to half of the sum of the voltages of the first voltage TVDD and the second voltage TVSS.

[0073] In this embodiment, the first signal IS1 received by the first signal processing circuit 110 is an analog signal. The first signal processing circuit 110 is an analog front end (AFE) circuit and is configured to process the first signal IS1 to generate a first output signal OS1. The first signal processing circuit 110 is operated based on the first voltage TVDD and the third voltage HTVDD, and an operating current OC can be generated and flows from the power supply terminal PE1 of the first signal processing circuit 110 to the reference ground terminal RGE1 of the first signal processing circuit 110.

[0074] On the other hand, the second signal IS2 received by the second signal processing circuit 120 is also an analog signal. The second signal processing circuit 120 is another analog front end (AFE) circuit, and is configured to process the second signal IS2 to generate a second output signal OS2. Since the power supply terminal PE2 of the second signal processing circuit 120 is coupled to (or is equivalent to) the reference ground terminal RGE1 of the first signal processing circuit 110. The operating current in the second signal processing circuit 120 is equivalent to the operating current OC, and flows from the power supply terminal PE2 of the second signal processing circuit 120 to the reference ground terminal RGE2 of the second signal processing circuit 120.

[0075] That is, in the presented embodiment, the operating current OC is shared by the first signal processing circuit 110 and the second signal processing circuit, and the total power consumption P=(TVDD-TVSS)×0.5×OC, and half of the power can be saved. In one embodiment, the first signal processing circuit and the second signal processing circuit are analog front end (AFE) circuits for processing touch sensing signals from a touch sensor array of a touch display panel.

[0076] Figure 22 is a schematic diagram of a signal processing device according to another embodiment of the present disclosure. In this embodiment, the signal processing device 200 includes a first signal processing circuit 210 and a second signal processing circuit 220. The first signal processing circuit 210 includes a first current transmitter 211 and a first accumulator 212. The first current transmitter 211 receives a first signal IS1, and the first current transmitter 211 is coupled to the first accumulator 212. In this embodiment, the first signal IS1 may be an analog touch sensing signal received from a touch sensor array of a touch display panel. The first current transmitter 211 also receives a drive signal V TX , and the first current conveyor 211 generates a first current signal CCS1 according to the first signal IS1. The driving signal V TX The first accumulator 212 receives the first voltage TVDD and the third voltage HTVDD as operating voltages from the first power supply terminal PE1 and the first reference ground terminal RGE1 respectively. The first accumulator 212 receives the first current signal CCS1 and performs an operation according to the first current signal CCS1 and the reference signal V REF A first accumulation result signal VO1 is generated, wherein the first accumulation result signal VO1 may be a differential output signal.

[0077] On the other hand, the second signal processing circuit 220 includes a second current transmitter 221 and a second accumulator 222. The second current transmitter 221 receives the second signal IS2, and the second current transmitter 221 is coupled to the second accumulator 222. In this embodiment, the second signal IS2 may be an analog touch sensing signal received from a touch sensor array of a touch display panel. The second current transmitter 221 also receives a driving signal V TX , and the second current transmitter 221 generates a second current signal CCS2 according to the second signal IS2. The second accumulator 222 receives the third voltage HTVDD and the second voltage TVSS as operating voltages from the second power terminal PE2 and the second reference ground terminal RGE2, respectively. The second accumulator 222 receives the second current signal CCS2 and generates a second current signal CCS2 according to the second current signal CCS2 and the reference signal V REF A second accumulation result signal VO2 is generated, wherein the second accumulation result signal VO2 may be a differential output signal. The first accumulator 212 and the second accumulator 222 are current accumulators.

[0078] It should be noted here that, since the first reference ground terminal RGE1 and the second power supply terminal PE2 are coupled in series, the operating current OC of the first signal processing circuit 210 can also flow into the second signal processing circuit 220, and thus charge reuse is achieved. The operating currents of the first signal processing circuit 210 and the second signal processing circuit 220 are operating currents equivalent to the operating current OC. By using the same operating current OC, the power consumption of the signal processing device 200 can be saved.

[0079] In addition, in the presented embodiment, the first current transmitter 211 and the second current transmitter 221 both receive the voltage HVDDA and the voltage GNDA as operating voltages, and the voltage level of the voltage HVDDA is higher than the voltage level of the voltage GNDA. In one embodiment, the voltage HVDDA and the first voltage TVDD may be the same or different, and the voltage GNDA and the second voltage TVSS may be the same or different.

[0080] Figure 3 3 is a circuit diagram of a signal processing device according to an embodiment of the present disclosure. The signal processing device 300 includes a first signal processing circuit 310 and a second signal processing circuit 320. The first signal processing circuit 310 includes a first current transmitter 311 and a first accumulator 312. The second signal processing circuit 320 includes a second current transmitter 321 and a second accumulator 322. The first current transmitter 311 and the first current transmitter 321 both receive a first voltage VDDA and a second voltage GNDA as operating voltages. The first accumulator 312 receives the first voltage VDDA and a third voltage HVDDA as operating voltages, and the second accumulator 322 receives the third voltage HVDDA and the second voltage GNDA as operating voltages. Here, the second voltage GNDA may be 0 volts, and the third voltage HVDDA may be half of the first voltage VDDA.

[0081] In this embodiment, the first current conveyor 311 includes a voltage follower 3111 and an output buffer 3112. The voltage follower 3111 has a negative input terminal for receiving the first signal IS1 and a negative input terminal for receiving the driving signal V TX The voltage follower 3111 generates a first current signal CCS1 according to the first signal IS1. In addition, the voltage follower 3111 includes an operational amplifier OP1, and the operational amplifier OP1 has an output stage circuit including a transistor MP1 and a transistor MN1. The positive input terminal of the operational amplifier OP1 receives the first signal IS1, and the negative terminal of the operational amplifier OP1 receives the driving signal V TXThe operational amplifier OP1 receives a first voltage VDDA and a second voltage GNDA as operating voltages, and is configured to generate a first current signal CCS1 according to a first signal IS1. In addition, the transistor MP1 and the transistor MN1 are coupled in series between the first voltage VDDA and the second voltage GNDA. The control terminals of the transistor MP1 and the transistor MN1 receive a first bias voltage VB1 and a second bias voltage VB2, respectively. In addition, the connection terminal of the transistor MP1 and the transistor MN1 is coupled to the negative terminal of the operational amplifier OP1 to provide a feedback path.

[0082] The output buffer 3112 includes a transistor MP2 and a transistor MN2. The transistor MP2 and the transistor MN2 are coupled in series between the first voltage VDDA and the second voltage GNDA. The control terminals of the transistor MP2 and the transistor MN2 receive the first bias voltage VB1 and the second bias voltage VB2, respectively, and the connection terminal of the transistor MP2 and the transistor MN2 is coupled to the first accumulator 312. The output buffer 3112 transmits the first current signal CCS1 to the first accumulator 312.

[0083] The second current conveyor 321 includes a voltage follower 3211 and an output buffer 3212. The voltage follower 3211 has a negative input terminal for receiving the second signal IS2 and a negative input terminal for receiving the driving signal V TX The voltage follower 3211 generates a second current signal CCS2 according to the second signal IS2. In addition, the voltage follower 3211 includes an operational amplifier OP3, and the operational amplifier OP3 has an output stage circuit including a transistor MP3 and a transistor MN3. The positive input terminal of the operational amplifier OP3 receives the second signal IS2, and the negative terminal of the operational amplifier OP3 receives the driving signal V TX The operational amplifier OP3 receives the first voltage VDDA and the second voltage GNDA as operating voltages, and is configured to generate a second current signal CCS2 according to the second signal IS2. In addition, the transistor MP3 and the transistor MN3 are coupled in series between the first voltage VDDA and the second voltage GNDA. The control terminals of the transistor MP3 and the transistor MN3 receive the third bias voltage VB3 and the fourth bias voltage VB4, respectively. In addition, the connection terminal of the transistor MP3 and the transistor MN3 is coupled to the negative terminal of the operational amplifier OP3 to provide a feedback path.

[0084] The output buffer 3212 includes a transistor MP4 and a transistor MN4. The transistor MP4 and the transistor MN4 are coupled in series between the first voltage VDDA and the second voltage GNDA. The control terminals of the transistor MP4 and the transistor MN4 receive the third bias voltage VB3 and the fourth bias voltage VB4, respectively, and the connection terminal of the transistor MP4 and the transistor MN4 is coupled to the second accumulator 322. The output buffer 3212 transmits the second current signal CCS2 to the second accumulator 322.

[0085] The first accumulator 312 includes an operational amplifier OP2 and capacitors CF11 and CF12. The operational amplifier OP2 receives the first voltage VDDA and the third voltage HVDDA as operating voltages. The capacitor CF11 is coupled between the negative input terminal of the operational amplifier OP2 and the output terminal of the operational amplifier OP2, and the capacitor CF12 is coupled between the positive input terminal of the operational amplifier OP2 and the output terminal of the operational amplifier OP2. The negative input terminal of the operational amplifier OP2 receives the reference signal V REFP , and the positive input terminal of the operational amplifier OP2 is coupled to the output buffer 3112 for receiving the first current signal CCS1. The first accumulator 312 generates a first current signal CCS1 according to the reference signal V REFP The first accumulation result signal VOP1 and the first accumulation result signal VON1 are generated by summing up the first current signal CCS1 , wherein the first accumulation result signal VOP1 and the first accumulation result signal VON1 are differential signals.

[0086] The second accumulator 322 includes an operational amplifier OP4 and capacitors CF21 and CF22. The operational amplifier OP4 receives the third voltage HVDDA and the second voltage GNDA as operating voltages. The capacitor CF21 is coupled between the negative input terminal of the operational amplifier OP4 and the output terminal of the operational amplifier OP4, and the capacitor CF22 is coupled between the positive input terminal of the operational amplifier OP4 and the output terminal of the operational amplifier OP4. The negative input terminal of the operational amplifier OP4 receives the reference signal V REFN , and the positive input terminal of the operational amplifier OP4 is coupled to the output buffer 3212 for receiving the second current signal CCS2. The second accumulator 322 generates a second current signal CCS2 according to the reference signal V REFN The second accumulation result signal VOP2 and the second accumulation result signal VON2 are generated by the second current signal CCS2, wherein the second accumulation result signal VOP2 and the second accumulation result signal VON2 are differential signals.

[0087] Figure 4A4 is a circuit diagram of another signal processing device according to an embodiment of the present disclosure. The signal processing device 401 includes a first signal processing circuit 410 and a second signal processing circuit 420. The first signal processing circuit 410 and the second signal processing circuit 420 may be coupled to corresponding touch electrodes, such as adjacent touch electrodes T[n] and touch electrodes T[n+1]. The touch electrodes T[n] and touch electrodes T[n+1] may be arranged in a touch sensor array integrated in a display panel. The first signal IS1 may be generated according to the capacitor C of the touch electrode T[n]. S1 Capacitance change ΔC S1 The second signal IS2 can be generated according to the capacitor C of the touch electrode T[n+1]. S2 Capacitance change ΔC S2 And produced.

[0088] The first signal processing circuit 410 includes a first current transmitter 411, a current mirror circuit 413 and a first accumulator 412. Figure 3 In the embodiment of the present invention, the first current transmitter 411 formed by the operational amplifier OP1 and the transistors MP2 and MN2 receives the third voltage HVDDA and the second voltage GNDA as the operating voltage. In addition, the first terminal of the transistor MP2 receives the third voltage HVDDA; the second terminal of the transistor MP2 is coupled to one terminal of the current mirror circuit 413; the first terminal of the transistor MN2 is coupled to the other terminal of the current mirror circuit 413; and the second terminal of the transistor MN2 receives the second voltage GNDA. The current mirror circuit 413 receives the first voltage VDDA and the second voltage GNDA as the operating voltage. The current mirror circuit 413 includes transistors MP41 to MN42. The first terminals of the transistors MP41 and MP42 receive the first voltage VDDA; the control terminal and the second terminal of the transistor MP41 are commonly coupled to the first terminal of the transistor MN2 and the control terminal of the transistor MP42; the control terminal and the first terminal of the transistor MN41 are commonly coupled to the second terminal of the transistor MP2 and the control terminal of the transistor MN42; the second terminals of the transistors MN41 and MN42 receive the second voltage GNDA; and the second terminal of the transistor MP42 is coupled to the first terminal of the transistor MN42.

[0089] In this embodiment, the operating voltage range (VDDA to GNDA) of the current mirror circuit 413 is different from the operating voltage range (HVDDA to GNDA) of the first current conveyor 411. The first current conveyor 411 provides the first current signal CCS1, and the current mirror circuit 413 is used to mirror the first current signal CCS1 to be operated in a different operating voltage range. In other words, since the current mirror circuit 413 performs a current delivery function, the first current conveyor 411 can operate at a lower operating voltage (which means that the third voltage HVDDA can be lower than the first voltage VDDA) and power consumption can be reduced.

[0090] On the other hand, the second signal processing circuit 420 does not include a current mirror circuit, and the second current transmitter 421 and the second accumulator 422 receive the third voltage HVDDA and the second voltage GNDA as operating voltages. Therefore, the operating current OC of the first accumulator 412 can flow into the second accumulator 422, and therefore, the charge is reused and the power consumption of the signal processing device 401 can also be reduced.

[0091] Figure 4B 4 is a circuit diagram of another signal processing device according to an embodiment of the present disclosure. In this embodiment, the signal processing device 402 includes a first signal processing circuit 430 and a second signal processing circuit 440. The first signal processing circuit 430 includes a first current conveyor 431, a first accumulator 432, and a current mirror circuit 433. The second signal processing circuit 440 includes a second current conveyor 441 and a second accumulator 442. In this embodiment, the first current conveyor 431 receives the third voltage HVDDA and the second voltage GNDA as operating voltages, and the first accumulator 432 receives the first voltage VDDA and the third voltage HVDDA as operating voltages.

[0092] Different from Figure 4AIn the embodiment of the present invention, the current mirror circuit 433 includes two current mirror stages that convey current and also convert the operating voltage range. The current mirror circuit 433 includes transistors MP41 to MN44, wherein transistors MP41 to MN42 form a first-stage current mirror, the first-stage current mirror is used to convey current and convert the range of the operating voltage from the voltage range HVDDA to GNDA to the voltage range VDDA to GNDA, and transistors MP43 to MN44 form a second-stage current mirror, the second-stage current mirror is used to convey current and convert the range of the operating voltage from the voltage range VDDA to GNDA to the voltage range VDDA to HVDDA. In this embodiment, transistors MP41 to MN42 receive the first voltage VDDA and the second voltage GNDA as operating voltages, and transistors MP43 to MN44 receive the first voltage VDDA and the third voltage HVDDA as operating voltages. On the other hand, the second signal processing circuit 440 does not include a current mirror circuit, and the second current conveyor 441 and the second accumulator 442 receive the third voltage HVDDA and the second voltage GNDA as operating voltages. Therefore, the operating current OC of the first accumulator 432 may flow into the second accumulator 442 , and thus, charges are reused and the power consumption of the signal processing apparatus 402 may also be reduced.

[0093] Figure 4C According to the present disclosure Figure 4A Another circuit diagram of the first signal processing circuit 410 of an embodiment of the present invention. Figure 4C In the embodiment of the present invention, the current mirror circuit 413 includes a voltage clamp circuit 4131 and a voltage clamp circuit 4132. The voltage clamp circuit 4131 is disposed between the transistor MP41 and the transistor MN2, and the voltage clamp circuit 4132 is disposed between the transistor MP43 and the transistor MN42. By using the clamp circuit 4131 and the clamp circuit 4132, it is possible to avoid applying a high voltage to the transistor MN2 and the transistor MN42. That is, the transistor MN2 and the transistor MN42 can be implemented by low withstand voltage transistors, and the cost of the circuit can be reduced.

[0094] Figure 4D According to the present disclosure Figure 4B Another circuit diagram of the first signal processing circuit 430 of an embodiment of the present invention. Figure 4DIn the embodiment of the present invention, the current mirror circuit 433 includes a voltage clamp circuit 4331 and a voltage clamp circuit 4332. The voltage clamp circuit 4331 is disposed between the transistor MP41 and the transistor MN2, and the voltage clamp circuit 4332 is disposed between the transistor MP43 and the transistor MN42. By using the clamp circuit 4331 and the clamp circuit 4332, it is possible to avoid applying a high voltage to the transistor MN2 and the transistor MN42. That is, the transistor MN2 and the transistor MN42 can be implemented by low withstand voltage transistors, and the cost of the circuit can be reduced.

[0095] Figure 5 Schematic diagram of another signal processing device according to an embodiment of the present disclosure. The signal processing device 500 includes a first signal processing circuit 510 and a second signal processing circuit 520, and further includes a first sample and hold (S / H) circuit 531, a first analog to digital converter (ADC), a second S / H circuit 541 and a second ADC 542. The first signal processing circuit 510 receives a first voltage TVDD and a third voltage HTVDD as operating voltages, and the second signal processing circuit 520 receives a third voltage HTVDD and a second voltage TVSS as operating voltages. In addition, the first S / H circuit 531 and the first ADC 532 are coupled in series, and the first S / H circuit 531 receives an accumulation result from the first signal processing circuit 510. In addition, the power supply terminals of the first S / H circuit 531 and the first ADC 532 are coupled to each other, and the power supply terminals of the first S / H circuit 531 and the first ADC 532 receive a fourth voltage TVDD_ADC. The reference ground terminals of the first S / H circuit 531 and the first ADC 532 are also coupled to each other and receive the fifth voltage HTVDD_ADC. In this embodiment, the voltage level of the fifth voltage HTVDD_ADC is lower than the voltage level of the fourth voltage TVDD_ADC.

[0096] On the other hand, the second S / H circuit 541 and the second ADC 542 are coupled in series, and the second S / H circuit 541 receives the accumulated result from the second signal processing circuit 520. In addition, the power supply terminals of the second S / H circuit 541 and the second ADC 542 are coupled to each other, and the power supply terminals of the second S / H circuit 541 and the second ADC 542 receive the fifth voltage HTVDD_ADC. The reference ground terminals of the second S / H circuit 541 and the second ADC 542 are also coupled to each other, and the reference ground terminals of the second S / H circuit 541 and the second ADC 542 receive the sixth voltage TVSS_ADC. In this embodiment, the voltage level of the fifth voltage HTVDD_ADC is greater than the voltage level of the sixth voltage TVSS_ADC.

[0097] It can be seen that the first S / H circuit 531 and the second S / H circuit 541 can share the same operating current, and the first ADC 532 and the second ADC 542 can share another same operating current, and the power consumption can be further reduced.

[0098] Figure 6 6 is a schematic diagram of another signal processing device according to another embodiment of the present disclosure. The signal processing device 600 includes a first signal processing circuit 610, a second signal processing circuit 620, and a third signal processing circuit 630. The first signal processing circuit 610, the third signal processing circuit 630, and the second signal processing circuit 620 are sequentially cascade-connected between a first voltage TVDD and a second voltage TVSS, and the first signal processing circuit 610, the third signal processing circuit 630, and the second signal processing circuit 620 are respectively used to receive a first signal IS1, a third signal IS3, and a second signal IS2. An operating current OC can flow from the first voltage TVDD to the second voltage TVSS through the first signal processing circuit 610, the third signal processing circuit 630, and the second signal processing circuit 620. By sharing the same operating current OC, the power consumption of the signal processing device 600 can be reduced.

[0099] FIG. 7A to FIG. 7C Schematic diagram of multiple touch display driving devices according to different embodiments of the present disclosure. The touch display driving device is an integrated circuit (IC) installed in a touch display device, which is used to drive the touch display panel of the touch display device, such as a mobile phone, a tablet computer with a touch function, a TV with a touch function, etc. Figures 1 to 4D The circuit structure of any one of the signal processing devices described in FIG. 7A to FIG. 7C The touch display driving device 701, the touch display driving device 702 or the touch display driving device 703. Fig. 7A In the embodiment, the touch display driving device 701 includes a touch analog front end (AFE) circuit 712 and a touch analog front end circuit 722 and a data driving circuit, and the data driving circuit includes a plurality of driving channels 711 and a plurality of driving channels 721. The touch sensor array may include a plurality of touch electrodes. For example, a plurality of display common electrodes may be connected to form a touch sensor. The display panel and the touch sensor array in this embodiment may be applied using any touch display panel known to those skilled in the art, and there is no further limitation herein.

[0100] The plurality of driving channels 711 are used to output a data voltage of a positive polarity (which operates in a voltage range of VDDA to HVDDA), and the plurality of driving channels 721 are used to output a data voltage of a negative polarity (which operates in a voltage range of HVDDA to GNDA). The power supply terminal PE1 of the touch AFE circuit 712 is coupled to the power supply rail PR1 for receiving a first voltage TVDD equivalent to the voltage VDDA, and the reference ground terminal RGE1 of the touch AFE circuit 712 is coupled to the power supply rail PR3 for receiving a third voltage HTVDD equivalent to the voltage HVDDA (as a common voltage). The power supply terminal PE2 of the touch AFE circuit 722 is coupled to the power supply rail PR3 for receiving the third voltage HTVDD, and the reference ground terminal RGE2 of the touch AFE circuit 722 is coupled to the power supply rail PR2 for receiving a second voltage TVSS equivalent to the voltage GNDA. The voltage level of the first voltage TVDD is greater than the voltage level of the third voltage HTVDD, and the voltage level of the third voltage HTVDD is greater than the voltage level of the second voltage TVSS.

[0101] The power supply terminal of the driving channel 711 is coupled to the power rail PR1 for receiving the voltage VDDA, and the reference ground terminal of the driving channel 711 is coupled to the power rail PR3 for receiving the voltage HVDDA. The driving channel 711 receives the voltage VDDA and the voltage HVDDA as operating voltages. In addition, the power supply terminal of the driving channel 721 is coupled to the power rail PR3 for receiving the voltage HVDDA, and the reference ground terminal of the driving channel 721 is coupled to the power rail PR2 for receiving the voltage GNDA. The driving channel 721 receives the voltage HVDDA and the voltage GNDA as operating voltages. Here, the driving channel 711 and the driving channel 721 are both hardware circuits and can be implemented by analog or mixed mode circuit structures.

[0102] In this embodiment, the driving channels 711 and 721 and the touch AFE circuits 712 and 722 may use the same operating voltage, and their power consumption may also be reduced.

[0103] exist Figure 7BIn the touch display driving device 702, the reference ground terminal of the driving channel 711 and the power supply terminal of the driving channel 721 can be commonly coupled to a power rail PR4 different from the power rail PR3. The power supply terminal PE1 of the touch AFE circuit 712 is coupled to the power rail PR1 for receiving a first voltage TVDD equivalent to the voltage VDDA. The power supply terminal PE2 of the touch AFE circuit 722 is coupled to the power rail PR3 for receiving a third voltage HTVDD, which is different from the voltage HVDDA (common voltage) coupled to the driving channel 711 and the driving channel 712. The reference ground terminal RGE2 of the touch AFE circuit 722 is coupled to the power rail PR2 for receiving a second voltage TVSS equivalent to the voltage GNDA. The driving channel 711 and the driving channel 721 and the touch AFE circuit 712 and the touch AFE circuit 722 can use the same maximum operating voltage and minimum operating voltage (but use different common voltages), and their power consumption can also be reduced.

[0104] exist Figure 7C In the touch display driving device 703, the power supply terminal of the driving channel 711 can be coupled to the power rail PR5 different from the power rail PR1. The voltage VDDA can be applied to the rail PR5, and the voltage VDDA can be different from the first voltage TVDD. The driving channel 711 and the driving channel 721 and the touch AFE circuit 712 and the touch AFE circuit 722 can use the same minimum operating voltage, and their power consumption can also be reduced.

[0105] In summary, the present disclosure provides a signal processing device having a plurality of signal processing circuits coupled in series between two operating voltages. The operating current can flow from the first signal processing circuit to the last signal processing circuit, and the signal processing circuits share the operating current. That is, the power consumption of the signal processing device can be reduced.

[0106] It will be apparent to those skilled in the art that various modifications and changes may be made to the structure of the disclosed embodiments without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is intended that the present disclosure covers modifications and changes of the present disclosure within the scope of the appended claims and their equivalents.

Claims

1. A signal processing device, comprising: A first signal processing circuit, configured to receive a first signal, wherein the first signal processing circuit has a power supply terminal connected to a first voltage and a reference ground terminal; as well as a second signal processing circuit for receiving a second signal, wherein the second signal processing circuit has a power supply terminal electrically coupled to the reference ground terminal of the first signal processing circuit or equivalent to the reference ground terminal of the first signal processing circuit, and the second signal processing circuit has a reference ground terminal connected to a second voltage, wherein the reference ground terminal of the first signal processing circuit and the power supply terminal of the second signal processing circuit are connected to a third voltage, wherein the first voltage is greater than the third voltage, and the third voltage is greater than the second voltage, The first signal processing circuit comprises: a first current transmitter receiving the first voltage and the second voltage as operating voltages, the first current transmitter generating a first current signal according to the first signal; and a first accumulator, coupled to the first current conveyor circuit, receiving the first voltage and the third voltage as operating voltages, receiving the first current signal, and generating a first accumulation result signal according to the first current signal and a first reference signal; And wherein the second signal processing circuit comprises: a second current transmitter receiving the third voltage and the second voltage as operating voltages, the second current transmitter generating a second current signal according to the second signal; and The second accumulator, coupled to the second current conveyor circuit, receives the third voltage and the second voltage as operating voltages, receives the second current signal, and generates a second accumulation result signal by accumulating the second current signal according to a second reference signal.

2. A signal processing device according to claim 1, wherein the first operating current of the first signal processing circuit flows from the power supply terminal of the first signal processing circuit to the reference ground terminal of the first signal processing circuit, and the second operating current of the second signal processing circuit flows from the power supply terminal of the second signal processing circuit to the reference ground terminal of the second signal processing circuit, wherein the first operating current is equivalent to the second operating current. 3 . The signal processing device according to claim 1 , wherein the third voltage is equal to half of a voltage sum of the first voltage and the second voltage.

4. The signal processing device according to claim 1, wherein the first signal processing circuit and the second signal processing circuit are both analog front-end circuits for processing touch sensing signals, and the first signal and the second signal are analog touch sensing signals received from a touch sensor array of a touch display panel.

5. The signal processing device according to claim 1, wherein the first current conveyor comprises: A first voltage follower having a negative input terminal for receiving the first signal, a positive input terminal for receiving a driving signal, and an output terminal coupled to the negative input terminal, and generating the first current signal; as well as a first output buffer coupled to the first voltage follower and transmitting the first current signal to the first accumulator; And wherein the second current conveyor comprises: a second voltage follower having a negative input terminal for receiving the second signal, a positive input terminal for receiving the driving signal, and an output terminal coupled to the negative input terminal, and generating the second current signal; as well as The second output buffer is coupled to the second voltage follower and transmits the second current signal to the second accumulator.

6. The signal processing device according to claim 1, wherein the first accumulator comprises: a first operational amplifier having a negative input terminal for receiving the first reference signal and a positive input terminal for receiving the first current signal; A first capacitor coupled between the negative input terminal of the first operational amplifier and a first output terminal of the first operational amplifier; as well as a second capacitor coupled between the positive input terminal of the first operational amplifier and a second output terminal of the first operational amplifier, and wherein the second accumulator comprises: a second operational amplifier having a negative input terminal for receiving the second reference signal and a positive input terminal for receiving the second current signal; A third capacitor coupled between the negative input terminal of the second operational amplifier and the first output terminal of the second operational amplifier; and A fourth capacitor is coupled between the positive input terminal of the second operational amplifier and the second output terminal of the second operational amplifier.

7. The signal processing device according to claim 1, further comprising: a first sampling and holding circuit, coupled to the first signal processing circuit and configured to receive a first accumulation result generated by the first signal processing circuit; a first analog-to-digital converter coupled to the first sample and hold circuit; a second sampling and holding circuit, coupled to the second signal processing circuit and configured to receive a second accumulation result generated by the second signal processing circuit; as well as a second analog-to-digital converter coupled to the second sample and hold circuit; The first sampling and holding circuit and the power supply terminal of the first analog-to-digital converter are coupled to each other, the first sampling and holding circuit and the reference ground terminal of the first analog-to-digital converter are coupled to each other, the second sampling and holding circuit and the power supply terminal of the second analog-to-digital converter are coupled to each other, and the second sampling and holding circuit and the reference ground terminal of the second analog-to-digital converter are coupled to each other, and the first sampling and holding circuit and the reference ground terminal of the first analog-to-digital converter serve as the power supply terminal of the second sampling and holding circuit and the second analog-to-digital converter.

8. The signal processing device according to claim 1, further comprising: The third signal processing circuit is used to receive a third signal, wherein the third signal processing circuit has a third power supply terminal connected to the reference ground terminal of the first signal processing circuit and has a reference ground terminal connected to the power supply terminal of the second signal processing circuit.

9. The signal processing device according to claim 8, wherein the power supply terminal of the third signal processing circuit receives a third voltage, and the reference ground terminal of the third signal processing circuit receives a fourth voltage, wherein the first voltage>the third voltage>the fourth voltage>the second voltage.

10. A touch display device, comprising: A display panel integrated with a touch sensor array, wherein the touch sensor array includes a plurality of touch electrodes; as well as A touch display driving device, comprising: A first touch analog front-end circuit coupled to a first touch electrode of the touch sensor array for receiving a first signal from the first touch electrode, wherein the first signal processing circuit has a power supply terminal connected to a first voltage and a reference ground terminal; and a second touch analog front-end circuit, coupled to the second touch electrode of the touch sensor array for receiving a second signal from the second touch electrode, wherein the second signal processing circuit has a power supply terminal electrically coupled to the reference ground terminal of the first signal processing circuit or equivalent to the reference ground terminal of the first signal processing circuit, and the second signal processing circuit has a reference ground terminal connected to a second voltage, wherein the reference ground terminal of the first touch analog front-end circuit and the power supply terminal of the second touch analog front-end circuit are connected to a third voltage, wherein the first voltage is greater than the third voltage, and the third voltage is greater than the second voltage, The first touch analog front-end circuit comprises: a first current transmitter receiving the first voltage and the second voltage as operating voltages, the first current transmitter generating a first current signal according to the first signal; and a first accumulator, coupled to the first current conveyor circuit, receiving the first voltage and the third voltage as operating voltages, receiving the first current signal, and generating a first accumulation result signal according to the first current signal and a first reference signal; And wherein the second touch analog front-end circuit comprises: a second current transmitter receiving the third voltage and the second voltage as operating voltages, the second current transmitter generating a second current signal according to the second signal; and The second accumulator, coupled to the second current conveyor circuit, receives the third voltage and the second voltage as operating voltages, receives the second current signal, and generates a second accumulation result signal by accumulating the second current signal according to a second reference signal.

11. A touch display device according to claim 10, wherein the first operating current of the first touch analog front-end circuit flows from the power supply terminal of the first touch analog front-end circuit to the reference ground terminal of the first touch analog front-end circuit, and the second operating current of the second touch analog front-end circuit flows from the power supply terminal of the second touch analog front-end circuit to the reference ground terminal of the second touch analog front-end circuit, wherein the first operating current is equivalent to the second operating current. 12 . The touch display device according to claim 10 , wherein the third voltage is equal to a half of a voltage difference between the first voltage and the second voltage.

13. The touch display device according to claim 10, wherein the touch display driving device further comprises a data driving circuit, the data driving circuit comprising a plurality of first driving channels for outputting a data voltage of a positive polarity and a plurality of second driving channels for outputting a data voltage of a negative polarity, and wherein the plurality of first driving channels are coupled to a first power rail, the plurality of second driving channels are coupled to a second power rail, and the plurality of first driving channels and the plurality of second driving channels are coupled to a third power rail providing a common voltage.

14. The touch display device according to claim 13, wherein the power supply terminal of the first touch analog front-end circuit is coupled to the first power supply rail, the reference ground terminal of the second touch analog front-end circuit is coupled to the second power supply rail, and the reference ground terminal of the first touch analog front-end circuit and the power supply terminal of the second touch analog front-end circuit are coupled to the third power supply rail. 15 . The touch display device according to claim 13 , wherein the power supply terminal of the first touch analog front-end circuit is coupled to the first power supply rail, and the reference ground terminal of the second touch analog front-end circuit is coupled to the second power supply rail. 16 . The touch display device according to claim 13 , wherein the reference ground terminal of the second touch analog front-end circuit is coupled to the second power rail.

17. A signal processing device comprising: A first signal processing circuit, configured to receive a first signal, wherein the first signal processing circuit has a power supply terminal connected to a first voltage and a reference ground terminal; as well as a second signal processing circuit for receiving a second signal, wherein the second signal processing circuit has a power supply terminal electrically coupled to the reference ground terminal of the first signal processing circuit or equivalent to the reference ground terminal of the first signal processing circuit, and the second signal processing circuit has a reference ground terminal connected to a second voltage, wherein the reference ground terminal of the first signal processing circuit and the power supply terminal of the second signal processing circuit are connected to a third voltage, wherein the first voltage is greater than the third voltage, and the third voltage is greater than the second voltage, The first signal processing circuit comprises: a first current transmitter, receiving the third voltage and the second voltage as operating voltages, and generating a third current signal according to the first signal; a current mirror circuit, coupled between the first current conveyor and the first accumulator, receiving the first voltage and the second voltage as operating voltages and mirroring the third current signal to generate a first current signal; and The first accumulator is coupled to the current mirror circuit, receives the first voltage and the third voltage as operating voltages, receives the first current signal, and generates a first accumulation result signal by accumulating the first current signal according to a first reference signal; And wherein the second signal processing circuit comprises: a second current transmitter receiving the third voltage and the second voltage as operating voltages, the second current transmitter generating a second current signal according to the second signal; and The second accumulator, coupled to the second current conveyor circuit, receives the third voltage and the second voltage as operating voltages, receives the second current signal, and generates a second accumulation result signal by accumulating the second current signal according to a second reference signal.

18. A touch display device, comprising: A display panel integrated with a touch sensor array, wherein the touch sensor array includes a plurality of touch electrodes; as well as A touch display driving device, comprising: A first touch analog front-end circuit coupled to a first touch electrode of the touch sensor array for receiving a first signal from the first touch electrode, wherein the first signal processing circuit has a power supply terminal connected to a first voltage and a reference ground terminal; and a second touch analog front-end circuit, coupled to the second touch electrode of the touch sensor array for receiving a second signal from the second touch electrode, wherein the second signal processing circuit has a power supply terminal electrically coupled to the reference ground terminal of the first signal processing circuit or equivalent to the reference ground terminal of the first signal processing circuit, and the second signal processing circuit has a reference ground terminal connected to a second voltage, wherein the reference ground terminal of the first touch analog front-end circuit and the power supply terminal of the second touch analog front-end circuit are connected to a third voltage, wherein the first voltage is greater than the third voltage, and the third voltage is greater than the second voltage, The first touch analog front-end circuit comprises: a first current transmitter, receiving the third voltage and the second voltage as operating voltages, and generating a third current signal according to the first signal; a current mirror circuit, coupled between the first current transmitter and the first accumulator, receiving the first voltage and the second voltage as operating voltages and mirroring the third current signal to generate a first current signal; and The first accumulator is coupled to the current mirror circuit, receives the first voltage and the third voltage as operating voltages, receives the first current signal, and generates a first accumulation result signal by accumulating the first current signal according to a first reference signal; And wherein the second touch analog front-end circuit comprises: a second current transmitter receiving the third voltage and the second voltage as operating voltages, the second current transmitter generating a second current signal according to the second signal; and The second accumulator, coupled to the second current conveyor circuit, receives the third voltage and the second voltage as operating voltages, receives the second current signal, and generates a second accumulation result signal by accumulating the second current signal according to a second reference signal.

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