Semiconductor packaging device and manufacturing method thereof

Abstract

The present disclosure provides a semiconductor packaging device and a method for manufacturing the same. The semiconductor packaging device first forms one or two electronic components on a first circuit layer by using a material with a self-alignment property (e.g., a bump or a solder ball), and forms a connecting line (e.g., a metal column) on the first circuit layer to be connected to the upper circuit component, thereby completing the positioning of the one or two electronic components and reducing the displacement caused by mold flow impact during the sealing process. Then, the circuit component is connected to the one or two electronic groups and the connecting line using a material with a self-alignment property. Furthermore, the semiconductor packaging device can reduce the displacement (shift) that may be caused to the electronic components by the mold flow impact during the sealing process, increase the data transmission speed between the electronic components, and reduce the cost.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor packaging devices, and in particular to an antenna semiconductor packaging device and a manufacturing method thereof. Background Art

[0002] The current semiconductor packaging forms mainly include 2.5D packaging, 3D packaging and fan-out packaging. In 2.5D packaging and 3D packaging, the bare chip (Die) and the substrate in the packaged product are mainly connected by through silicon vias (TSV) and interposers. However, the through silicon via process of the interposer is long and expensive. Although fan-out packaging does not require an interposer with through silicon vias, it can be connected through metal pillars. However, there is a redistribution layer (RDL) between the bare chip and the bridge die, which will warp during thermal cycling. In addition, if the electronic components or circuit components (for example, bare chips) are arranged above and below in the fan-out package, the electronic components arranged in the lower layer may be displaced by the mold flow impact during the sealing process, which may cause the subsequent redistribution layer to be unable to accurately align the unique electronic components (for example, bare chips) produced due to the mold flow impact. Summary of the invention

[0003] The present disclosure provides a semiconductor packaging device and a method for manufacturing the same.

[0004] In a first aspect, the present disclosure provides a semiconductor packaging device, the semiconductor packaging device comprising:

[0005] A first circuit layer having a first surface and a second surface opposite to the first surface, wherein the second surface is provided with a conductive element;

[0006] A first electrical component is disposed on the first surface, the passive surface is close to and parallel to the first surface, and the active surface is provided with an electrical connector;

[0007] A circuit component is disposed on the first electrical component, the active surface of the circuit component is close to the active surface of the first electrical component, and the circuit component is electrically connected to the first electrical component;

[0008] A connecting line, the circuit component is connected to the first circuit layer through the connecting line, and the length of the connecting line is greater than the height of the first electrical component;

[0009] A first dielectric material is disposed between the circuit component and the first electrical component and the connecting circuit and is close to the circuit component;

[0010] The second dielectric material is disposed between the circuit component and the first electrical component and the connecting circuit and is close to the first electrical component. The first dielectric material is different from the second dielectric material.

[0011] In some optional implementations, the semiconductor packaging device further includes:

[0012] A second electrical component, wherein the second electrical component and the first electrical component are arranged side by side on the first surface, the passive surface is close to and parallel to the first surface, and the active surface is provided with an electrical connector;

[0013] The circuit assembly is arranged on the first electrical assembly and the second electrical assembly, the active surface of the second electrical assembly is close to the active surface of the circuit assembly, the circuit assembly is electrically connected to the second electrical assembly, and the length of the connection circuit is greater than the height of the second electrical assembly;

[0014] A third dielectric material is disposed between the circuit component and the second electrical component and is close to the circuit component;

[0015] The fourth dielectric material is disposed between the circuit component and the second electrical component and is close to the second electrical component. The third dielectric material is different from the fourth dielectric material.

[0016] In some optional embodiments, the connecting line is arranged between the first electrical component and the second electrical component.

[0017] In some optional embodiments, the first electrical component has a third surface and a fourth surface opposite to the third surface, the second electrical component has a fifth surface and a sixth surface opposite to the fifth surface, the third surface is close to the second electrical component and the fourth surface is far away from the second electrical component, the fifth surface is close to the first electrical component and the sixth surface is far away from the first electrical component, the connecting line is arranged between the line component and the first electrical component and is close to the fourth surface and away from the third surface, or the connecting line is arranged between the line component and the second electrical component and is close to the sixth surface and away from the fifth surface.

[0018] In some optional embodiments, the connecting line is a metal column.

[0019] In some optional implementations, the circuit component is a chip, a bare chip, or a chip scale package.

[0020] In some optional embodiments, the first electrical component and the second electrical component include active electrical components and / or passive electrical components, and the first electrical component and the second electrical component are chips, bare dies, or chip scale packages.

[0021] In some optional embodiments, the first dielectric material is the same as the third dielectric material, and / or the second dielectric material is the same as the fourth dielectric material.

[0022] In some optional embodiments, the circuit component is electrically connected to the first electrical component, including:

[0023] The active surface of the circuit component is provided with a second circuit layer, and the circuit component is electrically connected to the electrical connector provided on the active surface of the first electrical component through the second circuit layer; alternatively, the active surface of the circuit component is provided with a conductive element, and the circuit component is electrically connected to the electrical connector provided on the active surface of the first electrical component through the conductive element provided on the active surface of the circuit component.

[0024] In some optional embodiments, the circuit component is electrically connected to the second electrical component, including:

[0025] The active surface of the circuit component is provided with a second circuit layer, and the circuit component is electrically connected to the electrical connector provided on the active surface of the second electrical component through the second circuit layer; alternatively, the active surface of the circuit component is provided with a conductive element, and the circuit component is electrically connected to the electrical connector provided on the active surface of the second electrical component through the conductive element provided on the active surface of the circuit component.

[0026] In some optional embodiments, the circuit component is electrically connected to the first electrical component, including:

[0027] The electrical connector disposed on the active surface of the first electrical component is a third circuit layer, and the circuit component is electrically connected to the third circuit layer disposed on the active surface of the first electrical component.

[0028] In some optional embodiments, the circuit component is electrically connected to the second electrical component, including:

[0029] The electrical connector disposed on the active surface of the second electrical component is a fourth circuit layer, and the circuit component is electrically connected to the fourth circuit layer disposed on the active surface of the second electrical component.

[0030] In some optional embodiments, the circuit assembly is electrically connected to the first electrical assembly, and the circuit assembly is electrically connected to the second electrical assembly, including:

[0031] The active surface of the circuit component is provided with a conductive element, the electrical connectors provided on the active surfaces of the first electrical component and the second electrical component are conductive elements, and the conductive elements provided on the active surface of the circuit component are electrically connected to the conductive elements provided on the active surfaces of the first electrical component and the second electrical component respectively.

[0032] In some optional implementations, the semiconductor packaging device further includes:

[0033] A first adhesive layer, disposed between the first electrical component and the first circuit layer;

[0034] The second adhesive layer is disposed between the second electrical component and the first circuit layer. In a first aspect, the present disclosure provides a method for manufacturing a semiconductor packaging device, the method comprising:

[0035] A first package is provided, the first package comprising a first carrier, a first circuit layer, a connecting circuit and a first electrical component, wherein the first circuit layer has a first surface and a second surface opposite to the first surface, the second surface is bonded to the first carrier, the first electrical component is arranged on the first surface, the passive surface of the first electrical component is close to and parallel to the first surface, the active surface of the first electrical component is provided with an electrical connector, the length of the connecting circuit is greater than the height of the first electrical component, the connecting circuit is electrically connected to the first circuit layer, a second dielectric material is provided on the active surface of the first electrical component and the end surface of the connecting circuit away from the first circuit layer to protect the active surface of the first electrical component and the end surface of the connecting circuit away from the first circuit layer, and the electrical connector and the connecting circuit of the first electrical component are exposed from the surface of the first package opposite to the first carrier;

[0036] Placing a circuit component on the first package body, wherein an active surface of the circuit component is close to the first electrical component and the connecting circuit;

[0037] electrically connecting the circuit assembly to the first electrical assembly and the connecting circuit respectively;

[0038] Forming a first dielectric material between the circuit component and the first electrical component and the connecting circuit to protect the active surface of the circuit component;

[0039] Injecting packaging material onto the circuit component to form a semiconductor packaging device;

[0040] removing the first carrier to expose the first circuit layer;

[0041] A conductive element is formed on the second surface.

[0042] In some optional implementations, the first package further includes:

[0043] a second electrical component, wherein the second electrical component and the first electrical component are arranged side by side on the first surface, the passive surface is close to and parallel to the first surface, the active surface of the second electrical component is provided with an electrical connector, the active surface of the second electrical component is further provided with a fourth dielectric material to protect the active surface of the second electrical component, and the electrical connector of the second electrical component is exposed from a surface of the first package body opposite to the first carrier; and

[0044] The step of electrically connecting the circuit component to the first electrical component and the connecting circuit respectively comprises:

[0045] electrically connecting the circuit component to the first electrical component, the connecting circuit, and the second electrical component respectively; and

[0046] The step of forming a first dielectric material between the circuit component and the first electrical component and the connecting circuit to protect the active surface of the circuit component includes:

[0047] A first dielectric material is formed between the circuit component and the first electrical component and the connecting circuit, and a third dielectric material is formed between the circuit component and the second electrical component to protect the active surface of the circuit component.

[0048] In some optional implementations, providing a first package includes:

[0049] forming a fifth circuit layer on the second carrier;

[0050] forming the connecting line on the fifth circuit layer, wherein the connecting line is electrically connected to the fifth circuit layer;

[0051] The first electrical component and the second electrical component are bonded and cured on the fifth circuit layer by using the second dielectric material and the fourth dielectric material respectively, and the active surface of the first electrical component and the active surface of the second electrical component are close to the fifth circuit layer;

[0052] injecting a packaging material to form a second packaging body;

[0053] grinding a surface of the second package body opposite to the second carrier to expose the connecting circuit;

[0054] removing the second carrier;

[0055] Removing the fifth circuit layer in the second package body, and grinding the seventh surface to expose the electrical connector of the first electrical component, the connecting circuit and the electrical connector of the second electrical component, wherein the seventh surface is a surface of the second package body close to the active surface of the first electrical component;

[0056] forming the first circuit layer on the first carrier;

[0057] The second package body is turned over and bonded to the first circuit layer, and the connecting circuit is electrically connected to the first circuit layer to form the first package body.

[0058] In some optional implementations, providing a first package includes:

[0059] forming the first circuit layer on the first carrier;

[0060] forming the connecting line on the first circuit layer so that the connecting line is electrically connected to the first circuit layer;

[0061] Adhere and solidify the passive surface of the first electrical component and the passive surface of the second component on the first surface of the first circuit layer using a first adhesive layer and a second adhesive layer respectively;

[0062] Injecting packaging material to form the first packaging body, wherein the second dielectric material is the packaging material injected onto the first electrical component and the connecting line, and the fourth dielectric material is the packaging material injected onto the second electrical component;

[0063] The surface of the first package body opposite to the first carrier is ground to expose the electrical connector of the first electrical component, the connecting line and the electrical connector of the second electrical component.

[0064] In some optional implementations, electrically connecting the circuit component to the first electrical component, the connecting circuit, and the second electrical component respectively includes:

[0065] The circuit component is electrically connected to the first electrical component, the connecting circuit and the second electrical component respectively through a material having a self-alignment property.

[0066] In some optional embodiments, the forming of the first dielectric material between the circuit component and the first electrical component and the connecting circuit, and the forming of the third dielectric material between the circuit component and the second electrical component to protect the active surface of the circuit component includes:

[0067] The bottom filling glue is injected into the space between the circuit component and the first electrical component, the connecting circuit and the second electrical component by dispensing glue to form the first dielectric material and the third dielectric material to protect the active surface of the circuit component.

[0068] The semiconductor packaging device and the manufacturing method thereof provided by the present disclosure, by using a material with self-alignment properties (e.g., a bump or a solder ball), firstly forms one or two electronic components (e.g., a first electrical component or a first electrical component and a second electrical component) on a first circuit layer (e.g., a redistribution layer), and forms a connecting line (e.g., a metal column) on the first circuit layer to be connected to the upper circuit component, thereby completing the positioning of the above one or two electronic components and reducing the displacement caused by mold flow impact during the sealing process. Then, the circuit component is connected to the above one or two electronic groups and the connecting line using a material with self-alignment properties. Furthermore, the semiconductor packaging device can achieve technical effects including but not limited to the following:

[0069] (1) By utilizing materials with self-alignment properties, the displacement of electronic components caused by mold flow impact during the sealing process is reduced, the internal connection problem between multiple electronic components is solved, and the yield is improved. It has been proven in practice that when a fan-out package in the prior art includes multiple electronic components, the assembly displacement of the multiple electronic components is greater than 15 microns, while the assembly displacement of the multiple electronic components in the semiconductor packaging device of the present disclosure can be less than 5 microns.

[0070] (2) In the prior art packaging method where a bridge chip connects a logic chip and a memory chip, the logic chip needs to be connected to the bridge chip through a redistribution layer and then to the memory chip. In the present disclosure, however, the communication between two electronic components (for example, the two electronic components can be a logic chip and a memory chip, respectively) only needs to be done through a line component as a bridge chip, without having to go through other redistribution layers, thereby shortening the transmission path and increasing the data transmission speed between the two electronic components. Practice has proven that the read and write speed between the two electronic components in the semiconductor packaging device of the present disclosure can exceed the read and write speed between the two electronic components in the 2.5D semiconductor packaging device of the prior art by 10%.

[0071] (3) The semiconductor package provided by the present disclosure does not use a through silicon via process, which greatly reduces the cost. Practice has proven that the cost can be reduced by more than 10% compared to the use of through silicon vias in 2.5D and 3D packages. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] Other features, objects and advantages of the present disclosure will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0073] Figure 1A is a cross-sectional view of one embodiment of a semiconductor package device according to the present disclosure;

[0074] Figure 1Bis a cross-sectional view of yet another embodiment of a semiconductor package device according to the present disclosure;

[0075] Figure 1C is a cross-sectional view of yet another embodiment of a semiconductor package device according to the present disclosure;

[0076] Figure 1D is a cross-sectional view of yet another embodiment of a semiconductor package device according to the present disclosure;

[0077] Figure 1E is a cross-sectional view of yet another embodiment of a semiconductor package device according to the present disclosure;

[0078] Figure 1F is a cross-sectional view of yet another embodiment of a semiconductor package device according to the present disclosure;

[0079] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E are cross-sectional views of semiconductor package devices 2a, 2b, 2c, 2d, 2e at various stages of manufacture according to some embodiments of the present disclosure;

[0080] Figure 2B' According to the present disclosure Figure 2B A cross-sectional view of one embodiment of a semiconductor package device 2b' manufactured at the stage shown;

[0081] Figure 3A-3H is a cross-sectional view of an embodiment of a first package according to the present disclosure at various stages of manufacture;

[0082] Figure 4A-4D 1 is a cross-sectional view of yet another embodiment of the first package according to the present disclosure at various manufacturing stages.

[0083] Explanation of symbols:

[0084] 10 first circuit layer 17 third dielectric material

[0085] 10a First surface 18 Fourth dielectric material

[0086] 10b Second surface 19 First adhesive layer

[0087] 11 first electrical component 20 second adhesive layer

[0088] 11a third surface 21 first package body

[0089] 11b fourth surface 22 first carrier

[0090] 12 circuit assembly 23 second carrier

[0091] 13 Connection line 24 Fifth line layer

[0092] 14 first dielectric material 25 first adhesive layer

[0093] 15 second dielectric material 26 second package

[0094] 16 Second electrical component 26a Seventh surface

[0095] 16a Fifth surface 27 Second adhesive layer

[0096] 16b Sixth surface DETAILED DESCRIPTION

[0097] The specific implementation of the present invention is described below in conjunction with the accompanying drawings and embodiments. Through the contents recorded in this specification, those skilled in the art can easily understand the technical problems solved by the present invention and the technical effects produced. It is understood that the specific embodiments described herein are only used to explain the relevant inventions, rather than to limit the inventions. In addition, for ease of description, only the parts related to the relevant inventions are shown in the accompanying drawings.

[0098] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented, so they have no substantial technical significance. Any modification of the structure, change in the proportion relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0099] In addition, the embodiments and features in the embodiments of the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0100] refer to Figure 1A , Figure 1A The cross-sectional view of one embodiment of a semiconductor package device 1 a according to the present disclosure is shown. The semiconductor package device 1 may include: a first circuit layer 100 , a first electrical component 11 , a circuit component 12 , a connecting circuit 13 , a first dielectric material 14 , and a second dielectric material 15 .

[0101] The first circuit layer 10 has a first surface 10a and a second surface 10b opposite to the first surface, and the second surface 10b is provided with a conductive element. The conductive element provided on the second surface 10b can be used to electrically connect the semiconductor package device 1a to the outside, such as to electrically connect to a printed circuit board (PCB).

[0102] For example, the conductive element disposed on the second surface 10b may be a controlled collapse chip connection (C4) bump, a solder bump, a ball grid array (BGA) or a land grid array (LGA), a metal pillar, or a combination of two or more thereof.

[0103] The first electrical component 11 is disposed on the first surface 10a, and the passive surface of the first electrical component 11 is close to and parallel to the first surface 10a, that is, the active surface of the first electrical component 11 is away from the first surface 10a. The active surface of the first electrical component 11 is provided with an electrical connector for electrically connecting to the outside. The first electrical component 11 may include active electrical components and / or passive electrical components, and the first electrical component 11 may also be a chip (for example, a logic function chip, a memory chip, a communication chip, a microprocessor chip, a graphics chip, or a micro-electromechanical system (MEMS) chip cut from a wafer), a bare die or a chip scale package, an insert, or a combination thereof. In some embodiments, the MEMS chip may include, for example, micro-sized electromechanical components (for example, optical devices, switches, mirrors, filters, transducers, accelerometers, microphones, capacitive sensors, sensors or actuators, etc.).

[0104] The circuit component 12 is disposed on the first electrical component 11. The active surface of the circuit component 12 is close to the active surface of the first electrical component 11, and the circuit component 12 is electrically connected to the first electrical component 11.

[0105] The circuit component 12 is connected to the first circuit layer 10 via a connecting line 13 , and the length of the connecting line 13 is greater than the height of the first electrical component 11 .

[0106] In some embodiments, the connection line 13 may be a metal pillar, and the connection line 13 may be a conductive material such as a metal or a metal alloy, or may include a conductive material such as a metal or a metal alloy. Here, the metal may be, for example, gold (Au), silver (Ag), aluminum (Al), copper (Cu) or an alloy thereof.

[0107] It should be noted that there is at least one connecting line 13 , and usually there are at least three connecting lines 13 , which are respectively used to realize the functions of power supply, grounding and signal transmission.

[0108] The first dielectric material 14 is disposed between the circuit component 12 and the first electrical component 11 and the connecting circuit 13 and is close to the circuit component 12. In some embodiments, the first dielectric material 14 can be, for example, PP (PrePreg, prepreg material or semi-cured resin, semi-cured sheet), ABF resin, BT (Bismaleimide Triazine, bismaleimide triazine) resin, glass cloth-based epoxy resin (FR4, FR5), PI resin, liquid crystal polymer resin (LCP) or epoxy resin.

[0109] The second dielectric material 15 is disposed between the circuit component 12 and the first electrical component 11 and the connecting circuit 13 and is close to the first electrical component 11, and the first dielectric material 14 is different from the second dielectric material 15. That is, the first dielectric material 14 and the second dielectric material 15 are disposed between the circuit component 12 and the first electrical component 11 and the connecting circuit 13, wherein the first dielectric material 14 is close to the circuit component 12, and the second dielectric material 15 is close to the first electrical component 11. The second dielectric material 15 can be, for example, polypropylene, ABF resin, BT resin, FR4, FR5, PI resin, liquid crystal polymer resin or epoxy resin.

[0110] Continue to refer Figure 1B , Figure 1B The semiconductor package device 1b shown in FIG. Figure 1A The semiconductor package device 1 a shown in FIG. 1 is different in that the semiconductor package device 1 b further includes a second electrical component 16 , a third dielectric material 17 and a fourth dielectric material 18 .

[0111] The second electrical component 16 and the first electrical component 11 are arranged side by side on the first surface 10a, and the passive surface of the second electrical component 16 is close to and parallel to the first surface 10a, that is, the active surface of the second electrical component 16 is far away from the first surface 10a. The active surface of the second electrical component 16 is provided with an electrical connector for electrical connection with the outside. The circuit component 12 is arranged on the first electrical component 11 and the second electrical component 16. The active surface of the second electrical component 16 is close to the active surface of the circuit component 12, the circuit component 12 is electrically connected to the second electrical component 16, and the length of the connecting line 13 is greater than the height of the second electrical component 16. The second electrical component 16 may include an active electrical component and / or a passive electrical component, and the second electrical component 16 may also be a chip (for example, a logic function chip, a memory chip, a communication chip, a microprocessor chip, a graphics chip or a micro-electromechanical system MEMS chip cut from a wafer), a bare die or a chip scale package, an insert or a combination thereof. In some embodiments, a MEMS chip may include, for example, micro-sized electromechanical components (eg, optical devices, switches, mirrors, filters, transducers, accelerometers, microphones, capacitive sensors, sensors or actuators, etc.).

[0112] The third dielectric material 17 is disposed between the circuit component 12 and the second electrical component 16 and is close to the circuit component 12. The third dielectric material 17 can be, for example, polypropylene, ABF resin, BT resin, FR4, FR5, PI resin, liquid crystal polymer resin or epoxy resin.

[0113] The fourth dielectric material 18 is disposed between the circuit component 12 and the second electrical component 16 and is close to the second electrical component 16, and the third dielectric material 17 is different from the fourth dielectric material 18. The fourth dielectric material 18 can be, for example, polypropylene, ABF resin, BT resin, FR4, FR5, PI resin, liquid crystal polymer resin or epoxy resin. That is, the third dielectric material 17 and the fourth dielectric material 18 are disposed between the circuit component 12 and the second electrical component 16, wherein the third dielectric material 17 is close to the circuit component 12, and the fourth dielectric material 18 is close to the second electrical component 16.

[0114] In some embodiments, the connection line 13 may be disposed between the first electrical component 11 and the second electrical component 16. For example, Figure 1A The semiconductor package device 1a shown or Figure 1B The semiconductor package device 1b is shown.

[0115] Continue to refer Figure 1C and Figure 1D , Figure 1C The semiconductor package device 1c shown in FIG. Figure 1B The semiconductor packaging device 1b shown in the figure is different in that: the first electrical component 11 has a third surface 11a and a fourth surface 11b opposite to the third surface 11a, the second electrical component 16 has a fifth surface 16a and a sixth surface 16b opposite to the fifth surface 16a, the third surface 11a is close to the second electrical component 16 and the fourth surface 11b is far away from the second electrical component 16, the fifth surface 16a is close to the first electrical component 11 and the sixth surface 16b is far away from the first electrical component 11, and the connecting line 13 is arranged between the line component 12 and the first electrical component 11 and is close to the fourth surface 11b and away from the third surface 11a (as shown in FIG. Figure 1C or the connecting line 13 is disposed between the line component 12 and the second electrical component 16 and is close to the sixth surface 16b and away from the fifth surface 16a (as shown in Figure 1D shown).

[0116] Continue to refer Figure 1E , Figure 1E The semiconductor package device 1e shown in FIG. Figure 1B The semiconductor package device 1 b shown in FIG. 1 is different in that the first dielectric material 14 may be the same as the third dielectric material 17 , and / or the second dielectric material 15 may be the same as the fourth dielectric material 18 .

[0117] In some embodiments, the active surface of the circuit component 12 can be provided with a second circuit layer, and the circuit component 12 can be electrically connected to the electrical connector provided on the active surface of the first electrical component 11 through the second circuit layer provided on its active surface, and the circuit component 12 can be electrically connected to the electrical connector provided on the active surface of the second electrical component 16 through the second circuit layer provided on its active surface.

[0118] In some embodiments, the active surface of the circuit component 12 may be provided with a conductive element, and the circuit component 12 may be electrically connected to the electrical connector provided on the active surface of the first electrical component 11 through the conductive element provided on the active surface of the circuit component 12, and the circuit component 12 may be electrically connected to the electrical connector provided on the active surface of the second electrical component 16 through the conductive element provided on its active surface.

[0119] For example, the conductive element disposed on the active surface of the circuit component 12 may be a controlled collapse chip connection (C4) bump, a solder bump, a ball grid array (BGA) or a land grid array (LGA), a metal pillar, or a combination of two or more thereof.

[0120] In some embodiments, the electrical connector disposed on the active surface of the first electrical component 11 may be a third circuit layer, and the circuit component 12 may be electrically connected to the third circuit layer disposed on the active surface of the first electrical component 11 .

[0121] In some embodiments, the electrical connector disposed on the active surface of the second electrical component 16 may be a fourth circuit layer, and the circuit component 12 may be electrically connected to the fourth circuit layer disposed on the active surface of the second electrical component 16 .

[0122] Continue to refer Figure 1F , Figure 1F The semiconductor package device 1f shown in FIG. Figure 1BThe semiconductor packaging device 1b shown in the figure is different in that: the active surface of the circuit component 12 is provided with a conductive element, the electrical connectors provided on the active surfaces of the first electrical component 11 and the second electrical component 16 can be conductive elements, and the conductive elements provided on the active surface of the circuit component 12 are respectively electrically connected to the conductive elements provided on the active surfaces of the first electrical component 11 and the second electrical component 16. For example, the conductive elements provided on the active surfaces of the circuit component 12, the first electrical component 11 and the second electrical component 16 can be controlled collapse chip connection (Controlled Collapse Chip Connection, C4) bumps, solder bumps, ball grid arrays (BGA) or land grid arrays (LGA), metal pillars (Pillar) or a combination of two or more thereof. In some embodiments, the semiconductor packaging device 1f can also include: a first adhesive layer 19 and a second adhesive layer 20. The first adhesive layer 19 is provided between the first electrical component 11 and the first circuit layer 10. The second adhesive layer 20 is provided between the second electrical component 16 and the first circuit layer 10.

[0123] As an example, the first adhesive layer 19 and the second adhesive layer 20 can be non-conductive paste (NCP) or non-conductive film (NCF). The first adhesive layer 19 is used to fix the first electrical component 11 and the first circuit layer 10, and the second adhesive layer 20 is used to fix the second electrical component 16 and the first circuit layer 10, so that the semiconductor packaging device is more secure.

[0124] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E 2F, 2G and 2H are cross-sectional views of semiconductor package devices 2a, 2b, 2c, 2d, 2e, 2f, 2g and 2h manufactured at various stages according to some embodiments of the present invention. The figures have been simplified for better understanding of various aspects of the present invention.

[0125] The first step is to provide a first package.

[0126] like Figure 2A As shown, a first package body 21 is provided. Here, the first package body 21 includes a first carrier 22, a first wiring layer 10, a connecting wire 13 and a first electrical component 11.

[0127] The first circuit layer 10 has a first surface 10a and a second surface 10b opposite to the first surface 10a. The first circuit layer 10 can be bonded to the first carrier 22 through the second adhesive layer 27. The first carrier 22 can be a panel type or a wafer type. The first carrier 22 can include glass or other materials. The second adhesive layer 27 can be, for example, a temporary glue layer.

[0128] The first electrical component 11 is disposed on the first surface 10a. The passive surface of the first electrical component 11 is close to and parallel to the first surface 10a. The active surface of the first electrical component 11 is provided with an electrical connector.

[0129] The length of the connection line 13 is greater than the height of the first electrical component 11. The connection line 13 is electrically connected to the first circuit layer 10.

[0130] A second dielectric material 15 is disposed on the active surface of the first electrical component 11 and the end surface of the connecting line 13 away from the first circuit layer 10 to protect the active surface of the first electrical component 11 and the end surface of the connecting line 13 away from the first circuit layer 10 .

[0131] The electrical connectors and the connection lines 13 of the first electrical component 11 are exposed on a surface of the first package body 21 opposite to the first carrier 22 .

[0132] The second step is to place the circuit component on the first packaging body.

[0133] like Figure 2B As shown, the circuit component 12 is placed on the first packaging body 21 , wherein the active surface of the circuit component 3 is close to the first electrical component 11 and the connecting line 13 .

[0134] The third step is to electrically connect the circuit assembly to the first electrical assembly and the connecting circuit respectively.

[0135] like Figure 2B As shown, the line component 12 is electrically connected to the first electrical component 11 and the connecting line 13 respectively.

[0136] Here, a material with an automatic alignment property can be used to electrically connect the circuit component 12 to the first electrical component 11 and the connection circuit 13. As an example, the circuit component 12 can be flip-chip welded, hot-pressed welded, or reflow welded to the electrical connector of the first electrical component 11 and the circuit component 13. Among them, electrically connecting the circuit component 12 to the first electrical component 11 can be electrically connecting the circuit component 12 to the electrical connector provided on the active surface of the first electrical component 11.

[0137] The electrical connectors disposed on the active surfaces of the first electrical component and the second electrical component may be redistribution layers or various conductive elements.

[0138] The fourth step is to form a first dielectric material between the circuit component and the first electrical component and the connecting circuit to protect the active surface of the circuit component.

[0139] like Figure 2B As shown, after placing the circuit component 12 on the first package body 21, a first dielectric material 14 can be formed between the circuit component 12 and the first electrical component 11 and the connecting line 13 to protect the active surface of the circuit component 12. For example, the bottom filling glue can be filled into the space below the circuit component 12 and between the first electrical component 11 and the connecting line 13 by dispensing technology to form the first dielectric material 14 for protecting the active surface of the circuit component 12. In some embodiments, the bottom filling glue can be a packaging material with smaller particles and better fluidity, which is used to fill small spaces.

[0140] In the fifth step, a packaging material is injected onto the circuit component to form a semiconductor packaging device.

[0141] like Figure 2C As shown, a packaging material is injected onto the circuit component 12 to form a semiconductor package device 2e.

[0142] Step 6: remove the first carrier to expose the first circuit layer.

[0143] like Figure 2D As shown, the first carrier 22 is removed to expose the first wiring layer 10. For example, the first carrier may be removed by a thermal process or other suitable process.

[0144] In the seventh step, a conductive element is formed on the second surface.

[0145] like Figure 2E As shown, a conductive element is formed on the second surface 10b of the first wiring layer 10.

[0146] Here, the conductive element may be a solder ball, a bump, a conductive glue or a conductive film. Figure 2E It is understood that the process and technology used may be different according to the type of conductive element, and will not be described in detail here.

[0147] In some optional embodiments, the first package provided in the first step may further include a second electrical component. The second electrical component and the first electrical component are arranged side by side on the first surface. The passive surface of the second electrical component is close to and parallel to the first surface. The active surface of the second electrical component is provided with an electrical connector, and the active surface of the second electrical component is also provided with a fourth dielectric material to protect the active surface of the second electrical component. The electrical connector of the second electrical component exposes the surface of the first package body opposite to the first carrier.

[0148] Based on the above optional implementation, in the third step, the circuit assembly is electrically connected to the first electrical assembly and the connecting line respectively, which can be performed as follows: the circuit assembly is electrically connected to the first electrical assembly, the connecting line and the second electrical assembly respectively. Figure 2B' As shown, the second electrical component 16 and the first electrical component 11 are arranged side by side on the first surface 10a. The passive surface of the second electrical component 16 is close to and parallel to the first surface 1a. The active surface of the second electrical component 16 is provided with an electrical connector, and the active surface of the second electrical component 16 is also provided with a fourth dielectric material 18 to protect the active surface of the second electrical component 16. The electrical connector of the second electrical component 16 exposes the surface of the first package body 21 opposite to the first carrier 22. The circuit component 12 is electrically connected to the first electrical component 11, the connecting line 13 and the second electrical component 16 respectively. In some embodiments, the circuit component can be electrically connected to the first electrical component, the connecting line and the second electrical component respectively by a material having an automatic alignment property. For example, the circuit component 12 can be flip-chip soldered, hot-pressed or reflow soldered to the electrical connector of the first electrical component 11, the electrical connector of the second electrical component 16 and the circuit component 13.

[0149] Based on the above optional implementation, in the fourth step, forming the first dielectric material between the circuit component and the first electrical component and the connecting circuit to protect the active surface of the circuit component can be performed as follows: forming the first dielectric material between the circuit component and the first electrical component and the connecting circuit, and forming the third dielectric material between the circuit component and the second electrical component to protect the active surface of the circuit component. Figure 2B' As shown, a first dielectric material 14 is formed between the circuit component 12 and the first electrical component 11 and the connecting circuit 13 , and a third dielectric material 17 is formed between the circuit component 12 and the second electrical component 16 to protect the active surface of the circuit component 12 .

[0150] In some embodiments, bottom filling glue can be injected between the circuit component 12 and the first electrical component 11 , the connecting circuit 13 and the second electrical component 16 by dispensing to form the first dielectric material 14 and the third dielectric material 17 to protect the active surface of the circuit component 12 .

[0151] In some optional implementations, in the first step, providing a first package body may be implemented by the following sub-steps 11 to 19:

[0152] Sub-step 11, forming a fifth circuit layer on the second carrier.

[0153] like Figure 3AAs shown, a fifth circuit layer 24 is formed on the second carrier 23, wherein the fifth circuit layer 24 is fixed on the second carrier 23 by a first adhesive layer 25. The second carrier 23 may be a panel type or a wafer type. The second carrier 23 may include glass or other materials. The first adhesive layer 25 may be, for example, a temporary glue layer.

[0154] The fifth wiring layer 24 may be formed by, for example (but not limited to), photolithography and electroplating techniques. The fifth wiring layer 24 may also be a redistribution layer. The fifth wiring layer 24 may include, for example, gold (Au), silver (Ag), nickel (Ni), copper (Cu), other metals or alloys, or a combination of two or more of the above.

[0155] Sub-step 12: forming a connecting circuit on the fifth circuit layer, wherein the connecting circuit is electrically connected to the fifth circuit layer.

[0156] like Figure 3B As shown, a connection line 13 is formed on the fifth wiring layer 24. For example, the connection line 13 can be formed by electroplating. The connection line 13 can include, for example, gold (Au), silver (Ag), nickel (Ni), copper (Cu), other metals or alloys, or a combination of two or more of the above.

[0157] Sub-step 13, using the second dielectric material and the fourth dielectric material to bond and solidify the first electrical component and the second electrical component on the fifth circuit layer, respectively, wherein the active surface of the first electrical component and the active surface of the second electrical component are close to the fifth circuit layer.

[0158] like Figure 3C As shown, the first electrical component 11 and the second electrical component 16 are bonded and cured on the fifth circuit layer 24 by using the second dielectric material 15 and the fourth dielectric material 18. For example, the first electrical component 11 and the second electrical component 16 can be bonded and cured on the fifth circuit layer 24 by using a non-conductive adhesive as the second dielectric material 15 and the fourth dielectric material 18 by using a hot pressing process.

[0159] Sub-step 14, injecting a packaging material to form a second packaging body.

[0160] like Figure 3D As shown, the encapsulation material is injected to form a second encapsulation body 3d.

[0161] Sub-step 15 , grinding the surface of the second package body opposite to the second carrier to expose the connection circuits.

[0162] Sub-step 16, removing the second carrier.

[0163] After grinding the surface of the second package body 3d opposite to the second carrier 26 to expose the connecting line 13 and removing the second carrier, the following can be obtained: Figure 3E The second package body 3e is shown.

[0164] Here, the second carrier may be removed, for example, by a thermal process or other suitable process.

[0165] Sub-step 17, removing the fifth circuit layer in the second package body, and grinding the seventh surface to expose the electrical connectors of the first electrical component, the connecting circuits, and the electrical connectors of the second electrical component.

[0166] The seventh surface is a surface of the second package body close to the active surface of the first electrical component.

[0167] The fifth circuit layer 24 in the second package body 3e is removed, and the seventh surface 26a is ground to expose the electrical connector of the first electrical component 11, the connecting circuit 13 and the electrical connector of the second electrical component 16. Figure 3F For example, the fifth circuit layer 24 in the second package body 3e may be removed by etching or grinding.

[0168] Sub-step 18: forming a first circuit layer on the first carrier.

[0169] like Figure 3G As shown, a first circuit layer 10 is formed on a first carrier 22. The first circuit layer 10 can be fixed on the first carrier 22 by a second adhesive layer 27. The first carrier 22 can be a panel type or a wafer type. The first carrier 22 can include glass or other materials. The second adhesive layer 27 can be, for example, a temporary glue layer.

[0170] The first circuit layer 10 can be formed by, for example (but not limited to), photolithography technology and electroplating technology. The first circuit layer 10 can also be a redistribution layer. The first circuit layer 10 can include, for example, gold (Au), silver (Ag), nickel (Ni), copper (Cu), other metals or alloys, or a combination of two or more of the above. In practice, the first circuit layer 10 can be provided with different numbers of circuit layers according to actual needs.

[0171] Sub-step 19, flipping the second package body and bonding it to the first circuit layer, and electrically connecting the connecting circuit to the first circuit layer to form a first package body.

[0172] like Figure 3H As shown, Figure 3F The second package body shown is flipped over and bonded to Figure 3G The first circuit layer 10 is shown, and the connecting circuit is electrically connected to the first circuit layer to form a first package 3h. For example, here, the second package can be flipped and bonded to the first circuit layer by hot pressing, flip chip or reflow soldering, and the connecting circuit is electrically connected to the first circuit layer.

[0173] In some optional implementations, in the first step, providing a first package body can also be implemented by the following sub-steps 11' to 19':

[0174] Sub-step 11 ′: forming a first circuit layer on the first carrier.

[0175] Here, the first circuit layer can be formed on the first carrier in the same manner as in sub-step 18, specifically as follows: Figure 3G As shown, a first circuit layer 10 is formed on a first carrier 22 .

[0176] Sub-step 12': forming a connecting circuit on the first circuit layer so that the connecting circuit is electrically connected to the first circuit layer.

[0177] like Figure 4A As shown, a connection line 13 is formed on the first circuit layer 10. For example, the connection line 13 can be formed by electroplating. The connection line 13 can include, for example, gold (Au), silver (Ag), nickel (Ni), copper (Cu), other metals or alloys, or a combination of two or more of the above.

[0178] Sub-step 13 ′: bonding and curing the passive surface of the first electrical component and the passive surface of the second component onto the first surface of the first circuit layer using the first adhesive layer and the second adhesive layer respectively.

[0179] like Figure 4B As shown, the passive surface of the first electrical component 11 and the passive surface of the second component 16 are bonded and cured on the first surface 10a of the first circuit layer 10 by using the first adhesive layer 19 and the second adhesive layer 20 respectively. For example, as an example, the first adhesive layer 19 and the second adhesive layer 20 can be non-conductive glue or non-conductive film. The passive surface of the first electrical component 11 can be bonded and cured on the first surface 10a of the first circuit layer 10 through the first adhesive layer 19, and the passive surface of the second electrical component 16 can be bonded and cured on the first surface 10a of the first circuit layer 10 through the second adhesive layer 20 by hot pressing.

[0180] Sub-step 14 ′: injecting a packaging material to form a first packaging body.

[0181] The second dielectric material is a packaging material injected into the first electrical component and the connecting line, and the fourth dielectric material is a packaging material injected into the second electrical component.

[0182] like Figure 4C As shown, the packaging material is injected to form a first packaging body 4 c , wherein the second dielectric material 15 is the packaging material injected onto the first electrical component 11 and the connecting line 13 , and the fourth dielectric material 18 is the packaging material injected onto the second electrical component 16 .

[0183] Sub-step 15 ′: grinding the surface of the first package body opposite to the first carrier to expose the electrical connectors of the first electrical component, the connecting lines and the electrical connectors of the second electrical component.

[0184] like Figure 4D As shown, the surface of the first package body 4c opposite to the first carrier 22 is ground to expose the electrical connectors of the first electrical component 11, the connecting wires 13 and the electrical connectors of the second electrical component 16, thereby obtaining the first package body 4d provided in the first step.

[0185] Although the present disclosure has been described and illustrated with reference to the specific embodiments of the present disclosure, these descriptions and illustrations do not limit the present disclosure. It is clearly understood by those skilled in the art that various changes can be made, and equivalent elements can be substituted in the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the artistic reproduction in the present disclosure and the actual equipment. There may be other embodiments of the present disclosure that are not specifically described. The specification and drawings should be regarded as illustrative, not restrictive. Modifications may be made to adapt specific situations, materials, material compositions, methods or processes to the goals, spirits and scopes of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations can be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the present disclosure.

Claims

1. A semiconductor packaging device, comprising: A redistribution layer having a first surface and a second surface opposite to the first surface, wherein the second surface is provided with a conductive element; A first electrical component is disposed on the first surface, the passive surface is close to and parallel to the first surface, and the active surface is provided with an electrical connector; a bridge chip, arranged on the first electrical component, with an active surface close to an active surface of the first electrical component, the bridge chip being electrically connected to the first electrical component; A connecting line, through which the bridge chip is connected to the redistribution layer, and the length of the connecting line is greater than the height of the first electrical component; A first dielectric material is disposed between the bridge chip and the first electrical component and the connecting line and is close to the bridge chip; A second dielectric material is disposed between the bridge chip and the first electrical component and the connecting line and is close to the first electrical component, and the first dielectric material is different from the second dielectric material; A second electrical component, wherein the second electrical component and the first electrical component are arranged side by side on the first surface, the passive surface is close to and parallel to the first surface, and the active surface is provided with an electrical connector; The bridge chip is arranged on the first electrical component and the second electrical component, the active surface of the second electrical component is close to the active surface of the bridge chip, the bridge chip is electrically connected to the second electrical component, and the length of the connection line is greater than the height of the second electrical component; Wherein, the connecting line is arranged between the first electrical component and the second electrical component.

2. The semiconductor package device according to claim 1, wherein: The semiconductor packaging device further comprises: A third dielectric material is disposed between the bridge chip and the second electrical component and is close to the bridge chip; The fourth dielectric material is disposed between the bridge chip and the second electrical component and is close to the second electrical component. The third dielectric material is different from the fourth dielectric material.

3. The semiconductor package device according to claim 1, wherein: The first electrical component has a third surface and a fourth surface opposite to the third surface, the second electrical component has a fifth surface and a sixth surface opposite to the fifth surface, the third surface is close to the second electrical component and the fourth surface is far away from the second electrical component, the fifth surface is close to the first electrical component and the sixth surface is far away from the first electrical component, the connecting line is arranged between the bridge chip and the first electrical component and is close to the fourth surface and away from the third surface, or the connecting line is arranged between the bridge chip and the second electrical component and is close to the sixth surface and away from the fifth surface.

4. The semiconductor package device according to claim 1, wherein: The connecting line is a metal column.

5. The semiconductor package device according to claim 2, wherein: The first dielectric material is the same as the third dielectric material, and / or the second dielectric material is the same as the fourth dielectric material.

6. The semiconductor package device according to claim 1, wherein: The bridge chip is electrically connected to the first electrical component, including: The active surface of the bridge chip is provided with a second circuit layer, and the bridge chip is electrically connected to the electrical connector provided on the active surface of the first electrical component through the second circuit layer; alternatively, the active surface of the bridge chip is provided with a conductive element, and the bridge chip is electrically connected to the electrical connector provided on the active surface of the first electrical component through the conductive element provided on the active surface of the bridge chip.

7. The semiconductor package device according to claim 1, wherein: The bridge chip is electrically connected to the second electrical component, including: The active surface of the bridge chip is provided with a second circuit layer, and the bridge chip is electrically connected to the electrical connector provided on the active surface of the second electrical component through the second circuit layer; alternatively, the active surface of the bridge chip is provided with a conductive element, and the bridge chip is electrically connected to the electrical connector provided on the active surface of the second electrical component through the conductive element provided on the active surface of the bridge chip.

8. The semiconductor package device according to claim 1, wherein: The bridge chip is electrically connected to the first electrical component, including: The electrical connector disposed on the active surface of the first electrical component is a third circuit layer, and the bridge chip is electrically connected to the third circuit layer disposed on the active surface of the first electrical component.

9. The semiconductor package device according to claim 1, wherein: The bridge chip is electrically connected to the second electrical component, including: The electrical connection member provided on the active surface of the second electrical component is a fourth circuit layer, and the bridge chip is electrically connected to the fourth circuit layer provided on the active surface of the second electrical component.

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