DRAM memory and method of forming the same

Abstract

A DRAM memory and a method for forming the same, wherein after etching the active area and the isolation layer to form a word line groove, the isolation layer is further etched along the sidewall of the word line groove in the isolation layer to widen the width of the word line groove in the isolation layer, so that the width of the word line groove in the isolation layer is greater than the width of the word line groove in the active area; a word line structure is formed in the word line groove, and the width of the word line structure in the isolation layer is greater than the width of the word line structure in the active area. The word line structure formed by the present invention is wavy, which reduces the resistance of the word line structure on the one hand; on the other hand, a channel is formed at the boundary of the active area, that is, the conductive channel width of the device is increased, and the conduction current of the transistor of the DRAM memory is increased, thereby improving the storage reading speed and increasing the integration of the transistor of the DRAM memory.

Description

Technical Field

[0001] The present invention relates to the field of memory, and in particular to a DRAM memory and a forming method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers, consisting of many repeated storage cells. Each storage cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.

[0003] In order to improve the integration of the storage structure, the transistors in the DRAM memory usually adopt a trench-shaped transistor structure. The specific structure of the trench-shaped transistor structure includes: a semiconductor substrate; a trench located in the semiconductor substrate; a gate (or word line structure) located in the trench; and a source region and a drain region located in the semiconductor substrate on both sides of the trench. The gate of the trench-shaped transistor is connected to the word line, one of the source region and the drain region is connected to the bit line, and the other of the source region and the drain region is connected to the capacitor.

[0004] Due to the constraints of word line resistance and capacitance-related factors, the number of transistors contained in a single existing DRAM chip is limited (generally 1024), which greatly limits the integration of DRAM. Therefore, how to reduce the word line resistance and increase the conduction current of the storage cell transistor has become a key and difficult problem in DRAM development and needs to be solved urgently. Summary of the invention

[0005] The technical problem to be solved by the present invention is how to reduce the word line resistance, improve the on-current of the memory cell transistor, and increase the integration of the transistor.

[0006] To this end, the present invention provides a method for forming a DRAM memory, comprising:

[0007] Providing a semiconductor substrate, on which a plurality of discrete active regions are formed, wherein the plurality of active regions are isolated by isolation layers;

[0008] Etching the active area and the isolation layer to form word line grooves in the active area and the isolation layer;

[0009] Continue etching the isolation layer along the sidewalls of the word line trench in the isolation layer to widen the width of the word line trench in the isolation layer, so that the width of that portion of the word line trench in the isolation layer is greater than the width of that portion of the word line trench in the active area;

[0010] A word line structure is formed in the word line trench, and a width of a portion of the word line structure in the isolation layer is greater than a width of a portion of the word line structure located in the active area.

[0011] Optionally, the step of continuously etching the isolation layer along the sidewalls of the word line trench in the isolation layer adopts an isotropic wet etching process.

[0012] Optionally, the ratio of the etching rate of the isolation layer to the etching rate of the active area of ​​the etching solution used in the isotropic wet etching process is greater than 3:1.

[0013] Optionally, the material of the active region is silicon, and the material of the isolation region is silicon oxide.

[0014] Optionally, the etching solution used in the isotropic wet etching process is hydrofluoric acid.

[0015] Optionally, when the isolation layer is continuously etched along the sidewalls of the word line trench in the isolation layer, the etched width of the isolation layer is 10 nm-15 nm.

[0016] Optionally, the word line groove is formed by: forming a mask layer in the active area and the isolation layer; the mask layer has parallel openings, the extension direction of the openings is at an oblique angle to the extension direction of the active area, and each opening exposes a portion of the active area and the isolation layer surface; etching the active area and the isolation area along the openings to form a word line groove in the active area and the isolation layer; continuing to use the mask layer as a mask to continue etching the isolation layer along the side walls of the word line groove in the isolation layer to widen the width of the word line groove in the isolation layer.

[0017] Optionally, the word line structure includes a gate oxide layer located on the sidewalls and the bottom of the word line trench and a metal electrode located on the gate oxide layer and filling the word line trench.

[0018] Optionally, the gate oxide layer is formed on the sidewalls and bottom of the word line trench by oxidizing the sidewalls of the word line trench in the active area.

[0019] Optionally, two separate word line trenches are formed in each active area, and the two word line trenches divide each active area into a drain located in the middle and two sources located on both sides of the drain respectively.

[0020] The present invention also provides a DRAM memory, comprising:

[0021] A semiconductor substrate, on which a plurality of discrete active regions are formed, wherein the active regions are isolated by isolation layers;

[0022] A word line trench located in the active area and the isolation layer, wherein the width of the portion of the word line trench located in the isolation layer is greater than the width of the portion of the word line trench located in the active area;

[0023] The width of the word line structure located in the word line trench and the portion of the word line structure located in the isolation layer is greater than the width of the portion of the word line structure located in the active area.

[0024] Optionally, the width of the portion of the word line trench located in the isolation layer is greater than the width of the portion of the word line trench located in the active area by 10 nm-15 nm.

[0025] Optionally, the material of the active region is silicon, and the material of the isolation region is silicon oxide.

[0026] Optionally, the word line structure includes a gate oxide layer located on the sidewalls and the bottom of the word line trench and a metal electrode located on the gate oxide layer and filling the word line trench.

[0027] Optionally, each active region has two separate word line trenches, and the two word line trenches divide each active region into a drain located in the middle and two sources located on both sides of the drain respectively.

[0028] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0029] The method for forming a DRAM memory of the present invention comprises the following steps: after etching the active area and the isolation layer to form word line grooves in the active area and the isolation layer, the isolation layer is continuously etched along the side walls of the word line grooves in the isolation layer to widen the width of the word line grooves in the isolation layer so that the width of the portion of the word line grooves located in the isolation layer is greater than the width of the portion of the word line grooves located in the active area; a word line structure is formed in the word line groove, and the width of the portion of the word line structure located in the isolation layer is greater than the width of the portion of the word line structure located in the active area. That is, in the present invention, the isolation layer is continuously etched along the sidewall of the word line groove in the isolation layer, so that the width of the word line groove in the isolation layer is widened, so that the width of the word line groove in the isolation layer is greater than the width of the word line groove in the active area. When a word line structure is formed in the word line groove, the width of the word line structure formed in the isolation layer will be correspondingly greater than the width of the word line structure formed in the active area, that is, the word line structure formed is wavy. The word line structure with this shape, on the one hand, increases the cross-sectional area of ​​the metal electrode in the word line structure, thereby reducing the resistance of the word line structure; on the other hand, since the width of the word line structure on both sides or around the active area is greater than the width of the word line structure in the active area, the gate electrode contact area of ​​the transistor of the DRAM memory is increased (that is, the gate width of the transistor is increased), which is conducive to increasing the conduction current of the transistor of the DRAM memory, thereby improving the storage reading speed and increasing the integration of the transistor of the DRAM memory.

[0030] Furthermore, the isolation layer is continuously etched along the sidewalls of the word line grooves in the isolation layer using an isotropic wet etching process, and the ratio of the etching rate of the etching solution used in the isotropic wet etching process on the isolation layer to the etching rate on the active area is greater than 3:1, so that the width of the word line grooves in the isolation layer is increased while the width of the word line grooves in the active area remains unchanged or changes very little.

[0031] Furthermore, the word line groove is formed as follows: a mask layer is formed in the active area and the isolation layer; the mask layer has parallel openings, the extension direction of the openings is at an oblique angle to the extension direction of the active area, and each opening exposes a portion of the active area and the isolation layer surface; the active area and the isolation area are etched along the openings to form word line grooves in the active area and the isolation layer; the mask layer is continued to be used as a mask to continue etching the isolation layer along the side walls of the word line grooves in the isolation layer to widen the width of the word line grooves in the isolation layer to ensure that the top surface of the isolation layer will not be etched, and it is beneficial to maintain the accuracy and uniformity of the etched width of the isolation layer and improve the etching efficiency.

[0032] In the DRAM memory of the present invention, the width of the word line groove in the isolation layer is greater than the width of the word line groove in the active area, and the width of the word line structure in the isolation layer is greater than the width of the word line structure in the active area. That is, the word line structure in the present invention is wavy, and the word line structure with such a shape increases the cross-sectional area of ​​the metal electrode in the word line structure on the one hand, thereby reducing the resistance of the word line structure; on the other hand, since the width of the word line structure on both sides or around the active area is greater than the width of the word line structure in the active area, the gate electrode contact area of ​​the transistor of the DRAM memory is increased (that is, the gate width of the transistor is increased), which is conducive to increasing the conduction current of the transistor of the DRAM memory, thereby improving the storage reading speed and increasing the integration of the transistor of the DRAM memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1-Figure 13 It is a structural schematic diagram of the DRAM memory formation process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] As mentioned in the background art, how to reduce word line resistance and increase the on-current of memory cell transistors has become a key and difficult problem in the development of DRAM and needs to be solved urgently.

[0035] Research has found that compared with the straight gate (or word line structure) formed in the existing semiconductor substrate, the wavy word line has a larger effective cross-sectional area, which will effectively reduce the resistance of the word line, allowing the word line to be quickly driven from a low potential to a high potential, thereby improving the operating speed of the DRAM memory.

[0036] To this end, the present invention provides a DRAM memory and a method for forming the same. In the method, after etching the active region and the isolation layer to form a word line groove, the isolation layer is further etched along the sidewall of the word line groove in the isolation layer to widen the width of the word line groove in the isolation layer, and the width of the word line groove in the isolation layer is greater than the width of the word line groove in the active region. A word line structure is formed in the word line groove, and the width of the part of the word line structure located in the isolation layer is greater than the width of the part of the word line structure located in the active region.

[0037] That is to say, the present invention further etches the isolation layer along the sidewall of the word line groove in the isolation layer, so that the width of the word line groove in the isolation layer is widened, so that the width of the word line groove in the isolation layer is greater than the width of the word line groove in the active area. When forming a word line structure in the word line groove, the width of the word line structure formed in the isolation layer will be correspondingly greater than the width of the word line structure formed in the active area, that is, the word line structure formed is wavy. The word line structure with this shape, on the one hand, increases the cross-sectional area of ​​the metal electrode in the word line structure, thereby reducing the resistance of the word line structure; on the other hand, since the width of the word line structure on both sides or around the active area is greater than the width of the word line structure in the active area, the gate electrode contact area of ​​the transistor of the DRAM memory is increased (that is, the gate width of the transistor is increased), which is conducive to increasing the on-current of the transistor of the DRAM memory, thereby improving the storage reading speed and increasing the integration of the transistor of the DRAM memory.

[0038] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0039] Figure 1 3D structure reference diagram of a DRAM memory according to an embodiment of the present invention, wherein the material filled in the isolation region and other structures irrelevant to the technical solution of the present invention are removed in order to clearly show the technical solution of the present invention. Figure 2-Figure 13 It is a structural schematic diagram of the DRAM memory formation process according to an embodiment of the present invention.

[0040] refer to Figure 1 , Figure 2 and Figure 3 , Figure 2 This is a top view of the structure. Figure 3 for Figure 2 The schematic cross-sectional structure diagram along the cutting line AB direction provides a semiconductor substrate 201 , on which a plurality of discrete active regions 202 are formed.

[0041] The material of the semiconductor substrate 201 may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or it may also be other materials, such as III-V group compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate 201 is silicon. Certain impurity ions are doped into the semiconductor substrate as required, and the impurity ions may be N-type impurity ions or P-type impurity ions. In one embodiment, the doping includes well region doping and source and drain region doping.

[0042] The formation process of the active area 202 is as follows: a first mask layer (not shown in the figure) is formed on the semiconductor substrate 201, and the first mask layer has a plurality of first openings distributed in parallel; using the first mask layer as a mask, the semiconductor substrate 201 is etched along the first openings to form a plurality of discrete long strip active areas in the semiconductor substrate 201, and a first groove is provided between adjacent long strip active areas; the long strip active areas are etched to form a plurality of second grooves in the long strip active areas, and the second grooves divide each long strip active area into a plurality of active areas.

[0043] In other embodiments, the active region 202 may be formed by an epitaxial process.

[0044] In this embodiment, Figure 1 As shown, the D1 direction can be used as the extension direction of the active region, and the positions of the active regions 202 in adjacent rows can have a certain misalignment.

[0045] refer to Figure 1 , Figure 4 and Figure 5 , Figure 4 This is a top view of the structure. Figure 5 for Figure 4 The schematic cross-sectional structure diagram along the cutting line AB shows that a plurality of active regions 202 are isolated from each other by forming an isolation layer 203 .

[0046] The material of the isolation layer 203 can be silicon oxide, silicon nitride, silicon oxynitride or other suitable isolation materials. In this embodiment, the material of the isolation layer 203 is silicon nitride.

[0047] The isolation layer 203 completely fills the first trench and the second trench between the active regions 202 , and the top surface of the isolation layer 203 may be flush with the top surface of the active region 202 .

[0048] In one embodiment, the formation process of the isolation layer 203 includes: forming an isolation material layer covering the active area 202, and the isolation material layer fills the first trench and the second trench; planarizing and removing the isolation material layer above the top surface of the active area 202, and forming the isolation layer 203 in the first trench and the second trench.

[0049] In another embodiment, the formation process of the isolation layer 203 includes: using the first mask layer as a mask, etching the semiconductor substrate 201 along the opening, forming a plurality of discrete long strip active regions in the semiconductor substrate 201, and then filling the first trench with an isolation material layer; then planarizing and removing the isolation material layer and the first mask layer above the long strip active region to form a first isolation layer in the first trench; forming a second mask layer on the long strip active region and the first isolation layer, the second mask layer having a plurality of second openings exposing a portion of the surface of the long strip active region, etching the long strip active region along the second openings to form a plurality of second trenches in the long strip active region, the second trenches dividing each long strip active region into a plurality of active regions 202; filling the second trenches with the isolation material layer; removing the isolation material layer and the second mask layer above the top surface of the active region 202 to form a second isolation layer in the second trench, the first isolation layer and the second isolation layer constituting the isolation layer 203.

[0050] refer to Figure 1 , Figure 6 and Figure 7 , Figure 6 This is a top view of the structure. Figure 7 for Figure 6 The cross-sectional structure schematic diagram along the cutting line AB direction shows that the active area 202 and the isolation layer 203 are etched to form a word line trench 204 in the active area 202 and the isolation layer 203 .

[0051] In this embodiment, there are two word line trenches 204 in each active area 202 to facilitate the subsequent formation of a double trench transistor. Specifically, the two word line trenches 204 divide each active area 202 into a drain in the middle and two sources on both sides of the drain.

[0052] The depth of the word line trench 204 is less than the thickness of the isolation layer 203 and greater than the thickness of the active area 202 . The word line trench 204 is a straight line, and each word line trench 204 can cross multiple active areas 202 and the isolation layer 203 between the active areas 202 .

[0053] In one embodiment, the word line trench 204 is formed by forming a mask layer (not shown) in the active area 202 and the isolation layer 203; the mask layer has parallel openings, and the extension direction of the openings (for example Figure 6 D2 direction) and the extension direction of the active area 202 (for example Figure 6 The active area 202 and the isolation layer 203 are partially exposed by each opening; the active area 202 and the isolation layer 203 are etched along the openings to form word line grooves 204 in the active area 202 and the isolation layer 203.

[0054] In one embodiment, the word line trench 204 may be etched into the active area 202 and the isolation layer 203 by an anisotropic dry etching process. Specifically, the anisotropic dry etching process may be a plasma etching process, so that the width of the word line trench 204 formed in the isolation layer 203 is equal to or similar to the width of the word line trench 204 formed in the active area 202. The width of the word line trench 204 is the vertical distance between two opposite side walls of the word line trench, or the width of the word line trench 204 along the active area 202. Figure 6 The dimension in the D1 direction.

[0055] refer to Figure 8 and Fig. 9 , Figure 8 This is a top view of the structure. Fig. 9 for Figure 8 Schematic diagram of the cross-sectional structure along the cutting line AB direction, the isolation layer 203 is continuously etched along the side wall of the word line groove 204 in the isolation layer 203 to widen the width of the word line groove 204 in the isolation layer 203, so that the width W1 of that part of the word line groove 204 in the isolation layer 203 is greater than the width W2 of that part of the word line groove 204 in the active area 202.

[0056] In the present application, the isolation layer 203 is continuously etched along the sidewall of the word line groove 204 in the isolation layer 203 to widen the width of the word line groove 204 in the isolation layer 203, so that the width of the word line groove 204 in the isolation layer 203 is greater than the width of the word line groove 204 in the active area 202. When a word line structure is subsequently formed in the word line groove 204, the width of the word line structure in the isolation layer 203 will be correspondingly greater than the width of the word line structure in the active area 202, that is, the word line structure in the isolation layer 203 is formed. The word line structure formed is wavy. On the one hand, the word line structure with this shape increases the cross-sectional area of ​​the metal electrode in the word line structure, thereby reducing the resistance of the word line structure; on the other hand, since the width of the word line structure on both sides or around the active area is greater than the width of the word line structure in the active area, the gate electrode contact area of ​​the transistor of the DRAM memory is increased (that is, the gate width of the transistor is increased), which is beneficial to increase the on-current of the transistor of the DRAM memory, thereby improving the storage reading speed and increasing the integration of the transistor of the DRAM memory.

[0057] In one embodiment, the isolation layer is continuously etched along the sidewalls of the word line grooves in the isolation layer using an isotropic wet etching process, and the etching rate of the etching solution used in the isotropic wet etching on the isolation layer is greater than the etching rate on the active area 202, so that while the width of the word line grooves 204 in the isolation layer 203 is widened, the sidewalls of the word line grooves 204 in the active area 202 will not be etched or the etching amount is small, so that the final isolation groove 204 includes two connected parts, specifically including a first part located in the isolation layer 203 (or the part located in the isolation layer 203) and a second part located in the active area 202 (or the part located in the active area), the first part is connected to the second part, and the width W1 of the first part is greater than the width W2 of the second part.

[0058] In one embodiment, the ratio of the etching rate of the etching solution used in the isotropic wet etching process on the isolation layer 203 to the etching rate on the active area 202 is greater than 3:1, so that while the width of the word line groove 204 in the isolation layer 203 is increased, the width of the word line groove in the active area 202 remains unchanged or changes very little.

[0059] In one embodiment, when the isolation layer 203 is continuously etched along the sidewall of the word line trench 204 in the isolation layer 203 , the etched width of the isolation layer 203 is 10 nm-15 nm.

[0060] In this embodiment, the material of the active region 202 is silicon, the material of the isolation region 203 is silicon oxide, and the etching solution used in the isotropic wet etching process is hydrofluoric acid.

[0061] In one embodiment, when the isolation layer is continuously etched along the sidewalls of the word line grooves in the isolation layer to widen the width of the word line grooves in the isolation layer, the mask layer used in forming the word line grooves is continuously used as a mask to ensure that the top surface of the isolation layer will not be etched, and to help maintain the accuracy and uniformity of the etched width of the isolation layer 203 and improve the etching efficiency. Fig.10 , Fig.11 , Fig.12 and Fig.13 , Fig.10 This is a top view of the structure. Fig.11 for Fig.10 Schematic diagram of the cross-sectional structure along the cutting line AB. Fig.12 This is a top view of the structure. Fig.13 for Fig.12 A schematic cross-sectional structure diagram along the cutting line AB direction shows that a word line structure 205 is formed in the word line trench.

[0062] The width W1 of the word line structure formed in the isolation layer 203 will be correspondingly greater than the width W2 of the word line structure in the active area 202, that is, the word line structure formed is wavy. The word line structure with this shape, on the one hand, increases the cross-sectional area of ​​the metal electrode in the word line structure, thereby reducing the resistance of the word line structure; on the other hand, because the width of the word line structure on both sides or around the active area is greater than the width of the word line structure in the active area, the gate electrode contact area of ​​the transistor of the DRAM memory is increased (that is, the gate width of the transistor is increased), which is beneficial to increase the on-current of the transistor of the DRAM memory, thereby improving the storage reading speed and increasing the integration of the transistor of the DRAM memory.

[0063] In one embodiment, the word line structure 205 includes a gate oxide layer located on the sidewalls and bottom of the word line trench and a metal electrode located on the gate oxide layer and filling the word line trench. Fig.10 and Fig.11 , by oxidizing the sidewalls of the word line trenches in the active area 202, a gate oxide layer 2051 is formed on the sidewalls and bottom of the word line trenches. Fig.12 and Fig.13 , metal is filled on the gate oxide layer 2051 to form a metal electrode 2052. In the step of further etching the sidewall of the isolation layer 203, the sidewall of the active region 202 may be exposed, such as Figure 8 The area indicated by the arrow in the middle may cause conduction between adjacent active areas 202 in the same row after the metal electrode is deposited. Therefore, in the step of forming the gate oxide layer 2051, the present invention also forms a gate oxide layer 2051 in the exposed active area to play an insulating role and avoid conduction between adjacent active areas 202 in the same row.

[0064] In one embodiment, before forming the metal electrode, a high-K dielectric layer may be formed on the sidewalls of the word line trench; and a metal electrode is formed on the high-K dielectric layer, and the metal electrode fully fills the word line trench.

[0065] The material of the high-K dielectric layer may be HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3 or BaSrTiO. The material of the metal electrode may be one or more of W, Al, Cu, Ti, Ag, Au, Pt and Ni.

[0066] The method further includes: forming a capacitor connected to the source on the isolation layer 203 ; and forming a bit line connected to the drain on the isolation layer 203 .

[0067] The present invention also provides a DRAM memory, please refer to Fig.12 and Fig.13 ,include:

[0068] A semiconductor substrate 201, on which a plurality of discrete active regions 202 are formed, wherein the active regions 202 are isolated from each other by isolation layers 202;

[0069] A word line trench 204 is formed in the active area 202 and the isolation layer 203, wherein the width of the portion of the word line trench 204 located in the isolation layer 203 is greater than the width of the portion of the word line trench 204 located in the active area 202;

[0070] A word line structure 205 is formed in the word line trench 204 , and a width W1 of a portion of the word line structure 205 in the isolation layer 203 is greater than a width W2 of a portion of the word line structure 205 in the active region 202 .

[0071] In one embodiment, the width of the portion of the word line trench 204 in the isolation layer 203 is greater than the width of the portion of the word line trench 204 in the active area 202 by 10 nm to 15 nm.

[0072] In one embodiment, the material of the active region 202 is a semiconductor material, and the material of the isolation region 203 is silicon oxide.

[0073] In one embodiment, the word line structure 205 includes a gate oxide layer 2051 located on the sidewalls and the bottom of the word line trench 204 and a metal electrode 2052 located on the gate oxide layer and filling the word line trench.

[0074] In one embodiment, two separate word line trenches 204 are formed in each active area 202 , and the two word line trenches 204 divide each active area into a drain located in the middle and two sources located on both sides of the drain.

[0075] It should be noted that other limitations or descriptions about the DRAM memory in this embodiment are not repeated in this embodiment. Please refer to the corresponding limitations or descriptions in the aforementioned DRAM memory formation process embodiment for details.

[0076] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for forming a DRAM memory, characterized in that: include: Providing a semiconductor substrate, on which a plurality of discrete active regions are formed, wherein the plurality of active regions are isolated by isolation layers; Etching the active area and the isolation layer to form word line grooves in the active area and the isolation layer; Continue etching the isolation layer along the sidewalls of the word line trench in the isolation layer to expose at least a portion of the sidewalls of the active area, so that the width of the word line trench in the isolation layer becomes wider, so that the width of that portion of the word line trench in the isolation layer is greater than the width of that portion of the word line trench in the active area; Oxidizing the sidewalls and bottom of the word line trench in the active area to form a gate oxide layer on the sidewalls and bottom of the word line trench in the active area; and oxidizing the sidewalls of the portion of the active region exposed in the isolation layer to form the gate oxide layer on the sidewalls of the portion of the active region exposed in the isolation layer; forming a word line structure in the word line trench, the word line structure comprising a gate oxide layer located on the sidewall and bottom of the word line trench and a metal electrode located on the gate oxide layer and filling the word line trench; The width of the portion of the word line structure in the isolation layer is greater than the width of the portion of the word line structure in the active area.

2. The method for forming a DRAM memory according to claim 1, wherein: The isotropic wet etching process is used to continuously etch the isolation layer along the sidewalls of the word line trench in the isolation layer.

3. The method for forming a DRAM memory according to claim 2, wherein: The ratio of the etching rate of the etching solution used in the isotropic wet etching process on the isolation layer to the etching rate on the active area is greater than 3:

1.

4. The method for forming a DRAM memory according to claim 2, wherein: The material of the active region is silicon, and the material of the isolation layer is silicon oxide.

5. The method for forming a DRAM memory according to claim 4, wherein: The etching solution used in the isotropic wet etching process is hydrofluoric acid.

6. The method for forming a DRAM memory according to claim 1, wherein: When the isolation layer is continuously etched along the sidewalls of the word line trench in the isolation layer, the isolation layer is etched to a width of 10 nm to 15 nm.

7. The method for forming a DRAM memory according to claim 1 or 2, wherein: The process of forming the word line trench is as follows: forming a mask layer in the active area and the isolation layer; The mask layer has parallel openings, the extension direction of the openings forms an oblique angle with the extension direction of the active area, and each opening exposes a portion of the active area and the isolation layer surface; Etching the active area and the isolation area along the opening to form word line grooves in the active area and the isolation layer; The isolation layer is continuously etched along the sidewalls of the word line trench in the isolation layer using the mask layer as a mask, so that the width of the word line trench in the isolation layer becomes wider.

8. The method for forming a DRAM memory according to claim 1, wherein: Two separate word line trenches are formed in each active region, and the two word line trenches divide each active region into a drain located in the middle and two sources located at both sides of the drain respectively.

9. A DRAM memory, characterized in that: include: A semiconductor substrate, on which a plurality of discrete active regions are formed, wherein the active regions are isolated by isolation layers; A word line groove located in the active area and the isolation layer, wherein the word line groove located in the isolation layer at least exposes a portion of the sidewall of the active area, and the width of the portion of the word line groove located in the isolation layer is greater than the width of the portion of the word line groove located in the active area; The word line structure includes a gate oxide layer located on the sidewall and bottom of the word line trench in the active area, a gate oxide layer located on the sidewall of the portion of the active area exposed in the isolation layer, and a metal electrode located on the gate oxide layer and filling the word line trench; The width of the portion of the word line structure located in the isolation layer is greater than the width of the portion of the word line structure located in the active area.

10. The DRAM memory according to claim 9, wherein: The width of the portion of the word line trench located in the isolation layer is greater than the width of the portion of the word line trench located in the active area by 10 nm to 15 nm.

11. The DRAM memory according to claim 9, wherein: The material of the active region is silicon, and the material of the isolation layer is silicon oxide.

12. The DRAM memory according to claim 9, wherein: Each active region has two separate word line trenches, and the two word line trenches divide each active region into a drain located in the middle and two sources located at both sides of the drain respectively.

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