A MEMS microphone wafer-level packaging structure

Abstract

The embodiment of the present invention provides a wafer-level packaging structure of a MEMS microphone, comprising: a first silicon substrate, a second silicon substrate and an ASIC chip; the first silicon substrate is sealed and connected to the second silicon substrate; the ASIC chip is arranged on a side of the second silicon substrate away from the first silicon substrate; the second silicon substrate comprises a first region and a second region surrounding the first region; the first region comprises a plurality of blind holes; the first silicon substrate comprises a through-hole region, the through-hole region is arranged opposite to the first region; a back electrode and a diaphragm are arranged on a side of the first silicon substrate adjacent to the second silicon substrate, the back electrode and the diaphragm at least cover the through-hole region, and the back electrode is arranged on a side of the diaphragm adjacent to the second silicon substrate; the back electrode is electrically connected to the ASIC chip via a first lead arranged in the second region, and the diaphragm is electrically connected to the ASIC chip via a second lead arranged in the second region. The wafer-level packaging structure of a MEMS microphone provided by the embodiment of the present invention can reduce the packaging area of ​​the MEMS microphone, and meet the market demand for miniaturized packaging of MEMS microphones.

Description

Technical Field

[0001] The present invention relates to the field of MEMS microphones, and in particular to a MEMS microphone wafer-level packaging structure. Background Art

[0002] MEMS microphones are microphones manufactured based on MEMS technology. They convert voice signals into electrical signals and are widely used in mobile phones, computers, cameras, camcorders and smart home products. MEMS microphones have good high temperature resistance and can withstand the high temperature test of surface assembly technology. The existing MEMS microphone structure uses a circuit board and a shell to form a cavity to form a MEMS microphone package. A solder pad can be set on the outer surface of the circuit board to fix the MEMS microphone and electrically connect it to the external circuit. A MEMS acoustic chip and an ASIC chip are installed inside the cavity. The ASIC chip includes at least a bias voltage terminal, an input terminal, an output terminal, a power supply terminal and a ground terminal. One electrode of the MEMS acoustic chip is electrically connected to the input terminal of the ASIC chip, and the other electrode is electrically connected to the bias voltage terminal of the ASIC chip. A sound hole that runs through the inside and outside of the cavity and is used to receive external sound signals is set on the package of the MEMS microphone.

[0003] The packaging process currently widely used in MEMS microphones cannot meet the needs of product miniaturization. Summary of the invention

[0004] The MEMS microphone wafer-level packaging structure provided by the embodiment of the present invention can reduce the packaging area of ​​the MEMS microphone, thereby meeting the market demand for miniaturized packaging of the MEMS microphone.

[0005] An embodiment of the present invention provides a MEMS microphone wafer-level packaging structure, including: a first silicon substrate, a second silicon substrate and an ASIC chip;

[0006] The first silicon substrate is sealed and connected to the second silicon substrate;

[0007] The ASIC chip is arranged on a side of the second silicon substrate away from the first silicon substrate;

[0008] The second silicon substrate includes a first region and a second region surrounding the first region; the first region includes a plurality of blind holes;

[0009] The first silicon substrate includes a through-hole area, and the through-hole area is arranged opposite to the first area; a back pole and a diaphragm are arranged on a side of the first silicon substrate adjacent to the second silicon substrate, and the back pole and the diaphragm at least cover the through-hole area, and the back pole is arranged on a side of the diaphragm adjacent to the second silicon substrate; the back pole is electrically connected to the ASIC chip through a first lead arranged in the second area, and the diaphragm is electrically connected to the ASIC chip through a second lead arranged in the second area.

[0010] Optionally, the first silicon substrate further includes a first sealing ring, and the second silicon substrate further includes a second sealing ring; the first sealing ring and the second sealing ring are arranged opposite to each other; and the first silicon substrate and the second silicon substrate are sealed by welding the first sealing ring and the second sealing ring.

[0011] Optionally, the second area of ​​the second silicon substrate includes a first through hole and a second through hole; the first through hole and the second through hole respectively penetrate the second silicon substrate; the first lead penetrates the first through hole to be connected to the ASIC chip, and the second lead penetrates the second through hole to be connected to the ASIC chip.

[0012] Optionally, the side of the second silicon substrate away from the first silicon substrate further includes a first reverse ball planting substrate, a second reverse ball planting substrate, a first solder ball, a second solder ball, a third lead and a fourth lead;

[0013] The first solder ball is disposed on a surface of the first reverse ball planting substrate away from the second silicon substrate, and the second solder ball is disposed on a surface of the second reverse ball planting substrate away from the second silicon substrate;

[0014] The third lead is electrically connected to the first reverse ball planting substrate and the ASCI chip respectively, and the fourth lead is electrically connected to the second reverse ball planting substrate and the ASCI chip respectively.

[0015] Optionally, the second silicon substrate further includes a first insulating layer and a second insulating layer;

[0016] The first insulating layer is disposed on the sidewalls of the first through hole and the second through hole, and is used to insulate the first lead and the second lead from the second silicon substrate;

[0017] The second insulating layer is disposed on a side of the first lead and the second lead away from the insulating layer, and the second insulating layer fills up the first through hole and the second through hole respectively.

[0018] Optionally, the second insulating layer is a solder resist layer.

[0019] Optionally, the first silicon substrate includes a third insulating layer, and the third insulating layer is respectively arranged on the sidewall of the through hole area, the side of the back electrode away from the second silicon substrate, and the side of the diaphragm close to the second silicon substrate.

[0020] Optionally, the ASIC chip includes a first conductive pin and a second conductive pin; the first conductive pin is electrically connected to the first lead; and the second conductive pin is electrically connected to the second lead.

[0021] Optionally, the first silicon substrate and the second silicon substrate have the same shape and cross-sectional dimensions.

[0022] Optionally, the first silicon substrate includes a fifth lead and a sixth lead; the fifth lead is connected to the back electrode and the first lead respectively; the sixth lead is connected to the diaphragm and the second lead respectively.

[0023] The MEMS microphone wafer-level packaging structure provided by the embodiment of the present invention stacks a first silicon substrate, a second silicon substrate and an ASIC chip in sequence, connects the back electrode and the ASIC chip via two ends of a first lead, and connects the diaphragm and the ASIC chip via two ends of a second lead to ensure the normal operation of the MEMS microphone. The MEMS microphone wafer-level packaging structure provided by the embodiment of the present invention can reduce the packaging area of ​​the MEMS microphone, thereby meeting the market demand for miniaturized packaging of MEMS microphones. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of a first silicon substrate structure of a MEMS microphone wafer-level packaging structure provided by an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of a second silicon substrate structure of a MEMS microphone wafer-level packaging structure provided by an embodiment of the present invention;

[0026] Figure 3 A schematic diagram of an ASIC chip structure of a MEMS microphone wafer-level packaging structure provided by an embodiment of the present invention;

[0027] Figure 4 A schematic structural diagram of a MEMS microphone wafer-level packaging structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the embodiments of the present invention, rather than to limit the embodiments of the present invention. It is also necessary to explain that, for ease of description, only parts related to the embodiments of the present invention are shown in the accompanying drawings, rather than all structures.

[0029] Figure 1 A schematic diagram of a first silicon substrate structure of a MEMS microphone wafer-level packaging structure provided by an embodiment of the present invention, Figure 2 A schematic diagram of a second silicon substrate structure of a MEMS microphone wafer-level packaging structure provided by an embodiment of the present invention, Figure 3 A schematic diagram of an ASIC chip structure of a MEMS microphone wafer-level packaging structure provided by an embodiment of the present invention, Figure 4 A schematic diagram of a MEMS microphone wafer-level packaging structure provided by an embodiment of the present invention. Figure 1 , Figure 2 , Figure 3 and Figure 4 The MEMS microphone wafer-level packaging structure provided by the embodiment of the present invention includes: a first silicon substrate 110, a second silicon substrate 120 and an ASIC chip 130; the first silicon substrate 110 is sealed and connected to the second silicon substrate 120; the ASIC chip 130 is arranged on a side of the second silicon substrate 120 away from the first silicon substrate 110; the second silicon substrate 120 includes a first area and a second area surrounding the first area; the first area includes a plurality of blind holes 20; the first silicon substrate 110 includes a through-hole area 10, and the through-hole area 10 is arranged opposite to the first area; a back electrode 11 and a diaphragm 12 are arranged on a side of the first silicon substrate 110 adjacent to the second silicon substrate 120, the back electrode 11 and the diaphragm 12 at least cover the through-hole area 10, and the back electrode 11 is arranged on a side of the diaphragm 12 adjacent to the second silicon substrate 120; the back electrode 11 is electrically connected to the ASIC chip 130 through a first lead 21 arranged in the second area, and the diaphragm 12 is electrically connected to the ASIC chip 130 through a second lead 22 arranged in the second area.

[0030] Specifically, refer to Figure 1 and Figure 4 There is a distance of several microns between the diaphragm 12 and the back electrode 11 in the first silicon substrate 110, forming a capacitor 13. When there is sound from the outside, the sound pressure signal is sensed by the diaphragm 12 through the through hole area 10 of the first silicon substrate 110, and the diaphragm 12 vibrates, so that the distance between the diaphragm 12 and the back electrode 11 will change, thereby causing the capacitor 13 to change. The ASIC chip 130 receives the capacitance change through the first lead 21 and the second lead 22, and the ASIC chip 130 converts the capacitance 13 change into a voltage signal change, and then outputs it after amplification. Reference Figure 2, there are multiple blind holes 20 in the first area, and the multiple blind holes 20 form an acoustic cavity to ensure that the signal-to-noise ratio of the MEMS microphone can meet the use requirements. The depth of the blind hole 20 is not greater than the depth of the silicon substrate to increase the mechanical strength of the wafer-level packaging structure of the MEMS microphone. When the depth of the blind hole 20 changes, the signal-to-noise ratio of the MEMS microphone will also change, that is, the signal-to-noise ratio of the MEMS microphone can be adjusted within a certain range through the packaging process parameters. The material of the diaphragm 12 can be silicon material, and the material of the back electrode 11 can be silicon nitride. The blind hole 20 is formed by dry etching, and a straight hole process is used. The straight hole process can reduce the upper opening size of the hole, thereby ensuring that there is enough space for wiring on the surface of the second silicon substrate 120. A plurality of small holes are also provided on the back electrode 11.

[0031] The MEMS microphone wafer-level packaging structure provided in the embodiment of the present invention stacks the first silicon substrate 110, the second silicon substrate 120 and the ASIC chip 130 in sequence, and connects the back electrode 11 and the ASIC chip 130 respectively through the two ends of the first lead 21, and connects the diaphragm 12 and the ASIC chip 130 respectively through the two ends of the second lead 22 to ensure the normal operation of the MEMS microphone. The MEMS microphone wafer-level packaging structure provided in the embodiment of the present invention can reduce the packaging area of ​​the MEMS microphone and meet the market demand for miniaturized packaging of MEMS microphones.

[0032] Optional, continue to refer to Figure 1 , Figure 2 and Figure 4 The first silicon substrate 110 further includes a first sealing ring 14, and the second silicon substrate 120 further includes a second sealing ring 23; the first sealing ring 14 and the second sealing ring 23 are arranged opposite to each other; the first silicon substrate 110 and the second silicon substrate 120 are sealed and connected by welding the first sealing ring 14 and the second sealing ring 23.

[0033] Specifically, the first sealing ring 14 and the second sealing ring 23 prevent the sound pressure signal from leaking out of the MEMS microphone wafer-level packaging structure. The first sealing ring 14 and the second sealing ring 23 are welded and connected by solder 40, so that the first silicon substrate 110 and the second silicon substrate 120 are stacked and sealed.

[0034] Optional, continue to refer to Figure 2 and Figure 4 The second region of the second silicon substrate 120 includes a first through hole 24 and a second through hole 25; the first through hole 24 and the second through hole 25 respectively penetrate the second silicon substrate 120; the first lead 21 penetrates the first through hole 24 and is connected to the ASIC chip 130, and the second lead 22 penetrates the second through hole 25 and is connected to the ASIC chip 130.

[0035] Specifically, the first lead 21 and the second lead 22 are respectively arranged in the first through hole 24 and the second through hole 25 to reduce the surface wiring area of ​​the second silicon substrate 120 and ensure that the second silicon substrate 120 has enough space for wiring. The first lead 21 and the second lead 22 are respectively connected to the ASIC chip 130 through the solder 40.

[0036] Optional, continue to refer to Figure 2 and Figure 4 The side of the second silicon substrate 120 away from the first silicon substrate 110 also includes a first reverse ball planting substrate 26, a second reverse ball planting substrate 27, a first solder ball 28, a second solder ball 29, a third lead and a fourth lead; the first solder ball 28 is arranged on the surface of the first reverse ball planting substrate 26 away from the second silicon substrate 120, and the second solder ball 29 is arranged on the surface of the second reverse ball planting substrate 27 away from the second silicon substrate 120; the third lead is electrically connected to the first reverse ball planting substrate 26 and the ASCI chip 130 respectively, and the fourth lead is electrically connected to the second reverse ball planting substrate 27 and the ASCI chip 130 respectively.

[0037] Specifically, the first solder ball 27 and the second solder ball 28 are used to connect to an external device and receive signals transmitted by the external device or transmit some signals to the external device, and the first reverse solder ball substrate 26 and the second reverse solder ball substrate 27 are respectively used to connect the first solder ball 28 and the second solder ball 29. The first solder ball 28 is electrically connected to the ASCI chip 130 through the third lead, and the second solder ball 29 is electrically connected to the ASCI chip 130 through the fourth lead.

[0038] It should be noted that the third lead and the fourth lead are not shown in the figure, which is not a limitation of the present invention. The third lead and the fourth lead can be set in any manner as long as the third lead can be electrically connected to the first reverse ball-planting substrate and the ASCI chip, and the fourth lead can be electrically connected to the second reverse ball-planting substrate and the ASCI chip respectively.

[0039] Optional, continue to refer to Figure 2 and Figure 4 The second silicon substrate 120 also includes a first insulating layer 30 and a second insulating layer 31; the first insulating layer 30 is arranged on the side walls of the first through hole 24 and the side walls of the second through hole 25, and is used to insulate the first lead 21 and the second lead 22 from the second silicon substrate 120; the second insulating layer 31 is arranged on the side of the first lead 21 and the second lead 22 away from the insulating layer, and the second insulating layer 31 fills the first through hole 24 and the second through hole 25 respectively.

[0040] Specifically, the first insulating layer 30 is also disposed on a side of the second silicon substrate 120 away from the ASIC chip. The function of the first insulating layer 30 is to prevent the signal transmitted by the first lead 21 and the second lead 22 from being input into the second silicon substrate 120 and causing signal loss. The second insulating layer 31 fills the first through hole 24 and the second through hole 25 after the first lead 21 and the second lead 22 are manufactured.

[0041] Optionally, the second insulating layer is a solder resist layer.

[0042] Specifically, the solder cannot be fixed on the solder resist layer. The function of the solder resist layer is to prevent the solder from falling into the first through hole and the second through hole and forming a conductive loop with the first lead 21 or the second lead 22 .

[0043] Optional, continue to refer to Figure 1 and Figure 4 The first silicon substrate 110 includes a third insulating layer 15 , which is respectively arranged on the sidewall of the through hole region 10 , the side of the back electrode 11 away from the second silicon substrate 120 , and the side of the diaphragm 12 close to the second silicon substrate 120 .

[0044] Specifically, the third insulating layer 15 is used to prevent the signal transmitted by the back electrode 11 and the diaphragm 12 from being transmitted into the first silicon substrate 110 .

[0045] Optional, continue to refer to Figure 3 and Figure 4 The ASIC chip 130 includes a first conductive pin 131 and a second conductive pin 132 ; the first conductive pin 131 is electrically connected to the first lead 21 ; the second conductive pin 132 is electrically connected to the second lead 22 .

[0046] Specifically, the ASIC chip 130 is stacked with the second silicon substrate 120, and receives signals transmitted by the first lead 21 and the second lead 22 through the first conductive pin 131 and the second conductive pin 132, respectively, or transmits power signals to the first lead 21 and the second lead 22 through the first conductive pin 131 and the second conductive pin 132, respectively.

[0047] Optionally, the first silicon substrate and the second silicon substrate have the same shape and cross-sectional dimensions.

[0048] Specifically, the first silicon substrate and the second silicon substrate have the same shape and cross-sectional dimensions, which can further reduce the volume of the MEMS microphone wafer-level packaging structure, so that the MEMS microphone wafer-level packaging structure can be developed and manufactured towards miniaturization to meet the market demand for miniaturized MEMS microphone products.

[0049] Optional, continue to refer to Figure 1 and Figure 4The first silicon substrate 110 includes a fifth lead 16 and a sixth lead 17; the fifth lead 16 is connected to the back electrode 11 and the first lead 21 respectively; the sixth lead 17 is connected to the diaphragm 12 and the second lead 22 respectively.

[0050] Specifically, the fifth lead 16 is connected to the first lead 21 via solder 40, and the sixth lead 17 is connected to the second lead 22 via solder 40. The fifth lead 16 is used to transmit the power signal transmitted by the first lead 21 to the back electrode 11, and the sixth lead 17 is used to transmit the change in capacitance detected by the diaphragm 12 to the second lead 22.

[0051] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the embodiments of the present invention are not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the embodiments of the present invention. Therefore, although the embodiments of the present invention are described in more detail through the above embodiments, the embodiments of the present invention are not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the embodiments of the present invention, and the scope of the embodiments of the present invention is determined by the scope of the appended claims.

Claims

1. A MEMS microphone wafer-level packaging structure, characterized in that: include: A first silicon substrate, a second silicon substrate and an ASIC chip; The first silicon substrate is sealed and connected to the second silicon substrate; The ASIC chip is arranged on a side of the second silicon substrate away from the first silicon substrate; The second silicon substrate includes a first region and a second region surrounding the first region; the first region includes a plurality of blind holes; The first silicon substrate comprises a through-hole region, and the through-hole region is arranged opposite to the first region; a back electrode and a diaphragm are arranged on a side of the first silicon substrate adjacent to the second silicon substrate, and the back electrode and the diaphragm at least cover the through-hole region, and the back electrode is arranged on a side of the diaphragm adjacent to the second silicon substrate; the back electrode is electrically connected to the ASIC chip via a first lead arranged in the second region, and the diaphragm is electrically connected to the ASIC chip via a second lead arranged in the second region; The first silicon substrate further includes a first sealing ring, and the second silicon substrate further includes a second sealing ring; the first sealing ring and the second sealing ring are arranged opposite to each other; the first silicon substrate and the second silicon substrate are sealed and connected by welding the first sealing ring and the second sealing ring; The first silicon substrate comprises a third insulating layer, and the third insulating layer is respectively arranged on the sidewall of the through hole region, the side of the back electrode away from the second silicon substrate, and the side of the diaphragm close to the second silicon substrate.

2. The MEMS microphone wafer-level packaging structure according to claim 1, characterized in that: The second region of the second silicon substrate includes a first through hole and a second through hole; the first through hole and the second through hole penetrate the second silicon substrate respectively; the first lead penetrates the first through hole to connect to the ASIC chip, and the second lead penetrates the second through hole to connect to the ASIC chip.

3. The MEMS microphone wafer-level packaging structure according to claim 2, characterized in that: The second silicon substrate further includes a first reverse ball planting substrate, a second reverse ball planting substrate, a first solder ball, a second solder ball, a third lead and a fourth lead on a side away from the first silicon substrate; The first solder ball is disposed on a surface of the first reverse ball planting substrate away from the second silicon substrate, and the second solder ball is disposed on a surface of the second reverse ball planting substrate away from the second silicon substrate; The third lead is electrically connected to the first reverse ball-planting substrate and the ASIC chip respectively, and the fourth lead is electrically connected to the second reverse ball-planting substrate and the ASIC chip respectively.

4. The MEMS microphone wafer-level packaging structure according to claim 2, characterized in that: The second silicon substrate further includes a first insulating layer and a second insulating layer; The first insulating layer is disposed on the sidewalls of the first through hole and the second through hole, and is used to insulate the first lead and the second lead from the second silicon substrate; The second insulating layer is disposed on a side of the first lead and the second lead away from the insulating layer, and the second insulating layer fills up the first through hole and the second through hole respectively.

5. The MEMS microphone wafer-level packaging structure according to claim 4, characterized in that: The second insulating layer is a solder resist layer.

6. The MEMS microphone wafer-level packaging structure according to claim 1, characterized in that: The ASIC chip comprises a first conductive pin and a second conductive pin; the first conductive pin is electrically connected to the first lead; and the second conductive pin is electrically connected to the second lead.

7. The MEMS microphone wafer-level packaging structure according to claim 1, characterized in that: The first silicon substrate and the second silicon substrate have the same shape and cross-sectional size.

8. The MEMS microphone wafer-level packaging structure according to claim 1, characterized in that: The first silicon substrate includes a fifth lead and a sixth lead; the fifth lead is connected to the back electrode and the first lead respectively; the sixth lead is connected to the diaphragm and the second lead respectively.

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